Patent Application
20130051117
This application is related to co-pending application having docket number 00100.10.0562, filed on even date, having inventors William En et al., titled “INTEGRATED CIRCUIT WITH BACKSIDE PASSIVE VARIABLE RESISTANCE MEMORY AND METHOD FOR MAKING THE SAME”, owned by instant assignee; and co-pending application having docket number 00100.10.0563, filed on even date, having inventors William En et al., titled “INTEGRATED CIRCUIT WITH FACE-TO-FACE BONDED PASSIVE VARIABLE RESISTANCE MEMORY AND METHOD FOR MAKING THE SAME”, owned by instant assignee.
The disclosure relates generally to an integrated circuit and to a method for making the same.
Dynamic random access memory (DRAM) and flash memory are two dominant memory technologies generally accepted to be nearing the end of their scaling lifetime, and the search is on for a replacement that can scale beyond DRAM and flash memory, while maintaining low latency and energy efficiency. Passive variable resistance memory, also known as resistive non-volatile memory, is emerging as a ubiquitous next generation of flash replacement technology (FRT). Passive variable resistance memory includes but is not limited to memristors, phase-change memory, and magnetoresistive memory (e.g., spin-torque transfer magnetoresistive memory). The key behind the passive variable resistance memory is storing state in the form of resistance instead of charge.
Similar to DRAM and flash memory, passive variable resistance memory may be used as on-chip memory integrated with processors, such as central processing units (CPUs) or graphic processing units (GPUs), in the forms of cache memory and/or main memory. It is known to place the passive variable resistance memory either laterally on the same die of the processor or on a separate die connected laterally to the processor die through a circuit board. Either implementation, however, has issues with cost and distance of the memory to where it is needed on the processor. As the passive variable resistance memory and the processor are laterally arranged, the die area and packaging size may be increased, and the memory access may be slowed down due to the relative long lateral connection distance.
Accordingly, there exists a need for an improved integrated circuit with passive variable resistance memory and a method for making the same.
The embodiments will be more readily understood in view of the following description when accompanied by the below figures and wherein like reference numerals represent like elements, wherein:
Briefly, in one example, an integrated circuit includes memory control logic (e.g., CMOS logic circuit) and vertically integrated passive variable resistance memory disposed above the memory control logic. The passive variable resistance memory, also known as resistive non-volatile memory, may be for example memristors, phase-change memory, or magnetoresistive memory. Each memory cell of the passive variable resistance memory is electrically connected to the memory control logic through at least one vertical interconnect accesses (vias). For example, the operation (e.g., write/read) of each passive variable resistance memory cell is controlled by the memory control logic. The integrated circuit may also include processor logic operatively coupled to the memory control logic.
Among other advantages, the method for making the integrated circuit with vertically integrated passive variable resistance memory provides a simple and inexpensive way to integrate the next generation of FRT (e.g., passive variable resistance memory) with the existing processors to improve the processor performance. This method allows for the FRT processing to be done after the CMOS logic devices (e.g., processor logic and/or memory control logic) are fabricated to avoid integration problems and to separate the FRT material contamination from the CMOS logic devices. In addition, compared with known integration solutions, the vertically integrated passive variable resistance memory eliminates any die area increase and enables faster memory access by both reducing the connection distance and allowing for the increased number of parallel connections. Other advantages will be recognized by those of ordinary skill in the art.
In one example, after forming the memory control logic, the method forms a dielectric layer above the memory control logic. The method then forms a lower electrode layer above the dielectric layer. For example, the method may pattern the lower electrode layer to form a plurality of word lines for the passive variable resistance memory. Each word line is electrically connected to the memory control logic through at least one of the plurality of vias. The method then forms a memory layer above the lower electrode layer. For example, the method may pattern the memory layer to form a plurality of memory regions for each of the plurality of passive variable resistance memory cells. The method then forms an upper electrode layer above the memory layer. For example, the method may pattern the upper electrode layer to form a plurality of bit lines for the passive variable resistance memory. Each bit line is electrically connected to the memory control logic through at least one of the plurality of vias. Each memory region of the memory layer is disposed at a place where each word line and bit line overlap, and passive variable resistance memory cell may be part of a crosspoint array. In this example, the resistance of each memory region changes based on a first electrical signal applied to the plurality of word lines and a second electrical signal applied to the plurality of bit lines by the memory control logic through the plurality of vias.
In another example, the method forms multiple layers of passive variable resistance memory cells. For example, the method may form a second dielectric layer above the first upper electrode layer to separate the first and second layers of passive variable resistance memory cells. The method then forms a second lower electrode layer above the second dielectric layer and a second memory layer above the second lower electrode layer. The method also forms a second upper electrode layer above the second memory layer.
In still another example, the method may also pattern the upper electrode layer to form at least one extend contact pad, which is electrically connected to the processor logic through at least one of the plurality of vias.
Among other advantages, the method for making the integrated circuit with vertically integrated passive variable resistance memory provides a simple and inexpensive way to integrate the next generation of FRT (e.g., passive variable resistance memory) with the existing processors to improve the processor performance. This method allows for the FRT processing to be done after the CMOS logic devices (e.g., processor logic and/or memory control logic) are fabricated to avoid integration problems and to separate the FRT material contamination from the CMOS logic devices. In addition, compared with known integration solutions, the vertically integrated passive variable resistance memory eliminates any die area increase and enables faster memory access by both reducing the connection distance and allowing for the increased number of parallel connections. Moreover, the method for making the integrated circuit with vertically integrated passive variable resistance memory provides flexibility for adopting various types of passive variable resistance memory such as but not limited to memristor, phase-change memory, or magnetoresistive memory. Other advantages will be recognized by those of ordinary skill in the art.
The integrated circuit 108 also includes passive variable resistance memory 306 having a plurality of passive variable resistance memory cells disposed above the memory control logic 304. That is, in this example, the passive variable resistance memory 306 is vertically integrated with fabricated processor logic 302 and memory control logic 304. The passive variable resistance memory 306 may include passive variable resistance devices such as but not limited to memristors, phase-change memory, magnetoresistive memory, or any other suitable passive variable resistance memory. For example, memristor is essentially a two-terminal variable resistor, with resistance dependent upon the amount of charge that passed between the terminals. As to phase-change memory, it comprises a heating resistor and chalcogenide between electrodes that can change its resistivity in response to thermal heating caused by current injection. For magnetoresistive memory, it stores information in the form of a magnetic tunnel junction, which separates two ferromagnetic materials with a layer of a thin insulating material. The storage state of each magnetoresistive memory cell changes when one layer switches to align with or oppose the direction of its counterpart layer, which then affects the junction's resistance.
In this example, the passive variable resistance memory 306 serves as on-die memory for the processor logic 302, such as processor registers, on-die cache memory (e.g., L1, L2, and L3 caches), or main memory. Each memory cell of the passive variable resistance memory 306 is electrically connected to the memory control logic 304 through at least one of a plurality of vias 308, 310. The memory control logic 304 controls the operation (e.g., write/read) of the passive variable resistance memory 306 by control signals (e.g., voltage/current) through the vias 308, 310. Although two vias 308, 310 between the passive variable resistance memory 306 and the memory control logic 304 are shown in
Referring to
Since more layers are formed above the existing memory control logic 304 and processor logic 302 to build the passive variable resistance memory 306, one or more extend contact pads 312 may be formed on the same layer of the uppermost metal electrode of the passive variable resistance memory 306. In one example as shown in
Referring now to
At block 602, the lower electrode layer 502 is formed above the dielectric layer 500. The lower electrode layer 502 may be formed using any suitable metal or semiconductor materials such as but not limited to platinum, copper, gold, aluminum, titanium, iridium, iridium oxide, ruthenium, or silver, by thin-film deposition techniques such as CVD, thermal evaporation, sputtering, MBE, or electroplating. Proceeding to block 604, the memory layer 504 is formed above the lower electrode layer 502. The memory layer 504 is formed by thin-film deposition techniques such as CVD, thermal evaporation, sputtering, MBE, electroplating, spin-coating, or any other suitable techniques. The material of the memory layer 504 may be any suitable variable resistance material that is capable of storing state by resistance. Depending on the specific type of passive variable resistance memory 306, the material of the memory layer 504 may include, for example, one or more thin-film oxides (e.g., TiO2, SiO2, NiO, CeO2, VO2, V2O5, Nb2O5, Ti2O3, WO3, Ta2O5, ZrO2, IZO, ITO, etc.) for memristors, chalcogenide for phase-change memory, and ferromagnetic materials (e.g., CoFeB incorporated in MgO) for magnetoresistive memory. Proceeding to block 606, the upper electrode layer 506 is formed above the memory layer 504. The material and fabrication technique of the upper electrode layer 506 is for example the same as of the lower electrode layer 502. However, it is understood that different materials and/or thin-film deposition techniques may be applied to the lower and upper electrode layers 502, 506 if necessary. As discussed previously, blocks 600-606 may be repeated to form multiple layers of passive variable resistance memory cells in the vertical direction to increase the storage size of the passive variable resistance memory 306 without increasing the die area. The uppermost electrode layer (e.g., the second upper electrode layer 514 in
It is known in the art that memory may be implemented by an array of memory cells. Each memory cell of the array includes a memory region as a place to store state, which represents one bit of information. As shown in
In this example embodiment, each passive variable resistance memory cell (e.g. one bit) may be a memristor of any suitable design. Since a memristor includes a memory region 700 (e.g., a layer of TiO2) between two metal electrodes (e.g., platinum wires), memristors could be accessed in a crosspoint array style (i.e., crossed-wire pairs) with alternating current to non-destructively read out the resistance of each memory cell. A crosspoint array is an array of memory regions 700 that can connect each wire in one set of parallel wires (word lines 702) to every member of a second set of parallel wires (bit lines 704) that intersects the first set (usually the two sets of wires are perpendicular to each other, but this is not a necessary condition). In other words, each memory cell may be, for example, part of a crosspoint array. The memristor disclosed herein may be fabricated using a wide range of material deposition and processing techniques. One example is disclosed in corresponding U.S. Patent Application Publication No. 2008/0090337, having a title “ELECTRICALLY ACTUATED SWITCH”, which is incorporated herein by reference.
In this example, first, a lower electrode (e.g., word line 702) is fabricated using conventional techniques such as photolithography or electron beam lithography, or by more advanced techniques, such as imprint lithography. This may be, for example, the bottom wire (word line 702) of a crossed-wire pair as shown in
In this example, the next component of the memristor to be fabricated is the non-covalent interface layer 804, and may be omitted if greater mechanical strength is required, at the expense of slower switching at higher applied voltages. In this case, a layer of some inert material is deposited. This could be a molecular monolayer formed by a Langmuir-Blodgett (LB) process or it could be a self-assembled monolayer (SAM). In general, this interface layer 804 may form only weak van der Waals-type bonds to the lower electrode (e.g., word line 702) and the primary layer 806 of the memory region 700. Alternatively, this interface layer 804 may be a thin layer of ice deposited onto a cooled integrated circuit die substrate. The material to form the ice may be an inert gas such as argon, or it could be a species such as CO2. In this case, the ice is a sacrificial layer that prevents strong chemical bonding between the lower electrode (e.g., word line 702) and the primary layer 806 of the memory region 700, and is lost from the system by heating later the integrated circuit die substrate in the processing sequence to sublime the ice away. One skilled in this art can easily conceive of other ways to form weakly bonded interfaces between the lower electrode (e.g., word line 702) and the primary layer 806 of the memory region 700.
Next, the material for the primary layer 806 of the memory region 700 is deposited. This can be done by a wide variety of conventional physical and chemical techniques, including evaporation from a Knudsen cell, electron beam evaporation from a crucible, sputtering from a target, or various forms of chemical vapor or beam growth from reactive precursors. The film may be in the range from 1 to 30 nanometers (nm) thick, and it may be grown to be free of dopants. Depending on the thickness of the primary layer 806, it may be nanocrystalline, nanoporous, or amorphous in order to increase the speed with which ions can drift in the material to achieve doping by ion injection or undoping by ion ejection from the primary layer 806. Appropriate growth conditions, such as deposition speed or temperature, may be chosen to achieve the chemical composition and local atomic structure desired for this initially insulating or low conductivity primary layer 806.
The next layer is the dopant source layer (i.e., secondary layer 808) for the primary layer 806, which may also be deposited by any of the techniques mentioned above. This material is chosen to provide the appropriate doping species for the primary layer 806. This secondary layer 808 is chosen to be chemically compatible with the primary layer 806, e.g., the two materials should not react chemically and irreversibly with each other to form a third material. One example of a pair of materials that can be used as the primary and secondary layers 806, 808 is TiO2 and TiO2-x, respectively. TiO2 is a semiconductor with an approximately 3.2 eV bandgap. It is also a weak ionic conductor. A thin film of TiO2 creates the tunnel barrier, and the TiO2-x forms an ideal source of oxygen vacancies to dope the TiO2 and make it conductive.
In this example, finally, an upper electrode (e.g., bit line 704) is fabricated above the secondary layer 808 of the memory region 700, in a manner similar to which the lower electrode (e.g., word lines 702) was created. This may be, for example, the top wire (bit line 704) of the crossed-wire pair as shown in
Proceeding to block 902, the lower electrode layer 502 is patterned to form a plurality of word lines 702 for the passive variable resistance memory 306, wherein each word line 702 is electrically connected to the memory control logic 800 through at least one of the plurality of vias 308. The word line 702 may be the bottom wire of the crossed-wire pair as shown in
Also, integrated circuit design systems (e.g., work stations) are known that create wafers with integrated circuits based on executable instructions stored on a computer readable medium such as but not limited to CDROM, RAM, other forms of ROM, hard drives, distributed memory, etc. The instructions may be represented by any suitable language such as but not limited to hardware descriptor language (HDL), Verilog or other suitable language. As such, the logic and circuits described herein may also be produced as integrated circuits by such systems using the computer readable medium with instructions stored therein. For example, an integrated circuit with the aforedescribed logic and structure may be created using such integrated circuit fabrication systems. The computer readable medium stores instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit. The designed integrated circuit includes processor logic and at least one extend contact pad electrically connected to the processor logic through at least one of a plurality of vias. The designed integrated circuit also includes memory control logic operatively coupled to the processor logic and a plurality of passive variable resistance memory cells of passive variable resistance memory disposed above the memory control logic. Each of the plurality of passive variable resistance memory cells is electrically connected to the memory control logic through at least one of the plurality of vias. The designed integrated circuit may also include any other structure as disclosed herein.
Among other advantages, the method for making the integrated circuit with vertically integrated passive variable resistance memory provides a simple and inexpensive way to integrate the next generation of FRT (e.g., passive variable resistance memory) with the existing processors to improve the processor performance. This method allows for the FRT processing to be done after the CMOS logic devices (e.g., processor logic and/or memory control logic) are fabricated to avoid integration problems and to separate the FRT material contamination from the CMOS logic devices. In addition, compared with known integration solutions, the vertically integrated passive variable resistance memory eliminates any die area increase and enables faster memory access by both reducing the connection distance and allowing for the increased number of parallel connections. Moreover, the method for making the integrated circuit with vertically integrated passive variable resistance memory provides flexibility for adopting various types of passive variable resistance memory such as but not limited to memristor, phase-change memory, or magnetoresistive memory. Other advantages will be recognized by those of ordinary skill in the art.
The above detailed description of the invention and the examples described therein have been presented for the purposes of illustration and description only and not by limitation. It is therefore contemplated that the present invention cover any and all modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and claimed herein.
