The present disclosure relates to an integrated electronic device, which includes a redistribution region and has a high resilience to mechanical stresses.
As is known, in the field of technologies for fabricating semiconductor circuits, reference is generally made to the redistribution layer (RDL) in order to indicate an additional metal layer of an integrated circuit (“chip”) formed within a die, which allows the input/output pads (I/O) formed within the same die to be rendered electrically accessible. In other words, the redistribution layer is a metal layer connected to the I/O pads, to which the wires which allow the ‘wire bonding’ may, for example, be connected in different positions with respect to the positions in which the pads are disposed. The redistribution layer thus allows, for example, the processes of electrical connection between chips to be simplified.
One example of use of the redistribution layer is shown schematically in
In detail, the integrated electronic device 10 is formed within a die 4, which includes a body of semiconductor material 6, which is bounded by an upper surface Sup and, although not shown, may include regions with different types and levels of doping. Furthermore, the integrated electronic device 10 comprises a frontal structure 8, which extends over the upper surface Sup.
The frontal structure 8 comprises a plurality of dielectric layers, disposed in a stack; for example, in
The frontal structure 8 furthermore comprises a number of first metallizations M1, to which reference is henceforth made as proximal metallizations M1, as well as a number of second and third metallizations M2, M3, to which reference is henceforth respectively made as intermediate metallizations M2 and as distal metallizations M3. The intermediate metallizations M2 extend, at a distance, between the proximal metallizations M1 and the distal metallizations M3.
The distal metallizations M3 extend through the third dielectric layer 14, hence they open out onto the fourth dielectric layer 16.
The intermediate metallizations M2 extend through the fifth dielectric layer 17, hence they open out onto the fourth and onto the sixth dielectric layer 16, 18.
The proximal metallizations M1 extend through the seventh dielectric layer 19, hence they open out onto the sixth 18 and onto the eighth dielectric layer 20.
The frontal structure 8 also comprises a number of contact regions CR formed by metal material, which extend through the tenth dielectric layer 20 in such a manner as to open out onto the semiconductor body 6, with which they are in direct contact. Furthermore, the contact regions CR are in contact with corresponding first metallizations M1, disposed on top of these.
The frontal structure 8 furthermore comprises a plurality of first vias V1, to which reference is henceforth made as proximal vias V1, as well as a number of second and third vias V2, V3, to which reference is henceforth respectively made as intermediate vias V2 and as distal vias V3. Each proximal via V1 electrically connects a proximal metallization M1 and a corresponding intermediate metallization M2; each intermediate via V2 electrically connects an intermediate metallization M2 and a corresponding distal metallization M3.
Each distal via V3 extends into a corresponding hole T, which passes through the first and the second dielectric layer 11, 12. In this regard, the first dielectric layer 11 is typically formed from silicon nitride (SiN); the first dielectric layer 11 is bounded on top by a surface Sfront, to which reference is henceforth made as frontal surface Sfront. The second dielectric layer 12 is formed, for example, from silicon oxide. The sum of the thicknesses of the dielectric layers 11 and 12 may for example be greater than 1 μm.
The bottom of the hole T is thus bounded by a corresponding distal metallization M3, whereas the sidewall of the hole T is bounded by the first and by the second dielectric layer 11, 12. Furthermore, the bottom and the sidewall of the hole T are covered, in direct contact, by a first patterned barrier layer 22, which can for example have a thickness greater than 100 nm and may be composed of titanium (Ti) or tantalum (Ta), or else made of an alloy containing titanium or tantalum (for example, TiN, TiW, TaNTa). The first patterned barrier layer 22 furthermore extends in part over the top of the frontal surface Sfront, in direct contact with the first dielectric layer 11.
The first patterned barrier layer 22 is, in turn, covered by a further layer 24, to which reference is henceforth also made as patterned seed layer 24.
The patterned seed layer 24 is typically formed from copper and may for example have a thickness greater than 10 nm. The patterned seed layer 24 thus extends into the inside of the hole T, in such a manner as to cover the portions of the first patterned barrier layer 22 which cover the bottom and the sidewall of the hole T. Furthermore, the patterned seed layer 24 extends over the top of the portions of the first patterned barrier layer 22 which extend over the top of the first dielectric layer 11.
The frontal structure 8 furthermore comprises a conductive region 25, to which reference is henceforth made as redistribution layer 25.
The redistribution layer 25 is formed from the same conductive material as that forming the distal vias V3. The redistribution layer 25 is thus typically formed from copper, is patterned and overlies the distal vias V3, with which it forms a single monolithic region. Furthermore, the redistribution layer 25 may for example have a thickness greater than 1 μm.
The redistribution layer 25 also extends over the top of the portions of the patterned seed layer 24 disposed on top of the frontal surface Sfront. In more detail, the patterned seed layer 24 also forms the aforementioned monolithic region, together with the redistribution layer 25 and the distal vias V3.
The frontal structure 8 furthermore comprises a first coating layer 30, which covers the top and the sides of the redistribution layer 25, as far as making contact with portions of the first dielectric layer 11. The first coating layer 30 is typically formed from nickel or from one of its alloys (for example NiP, NiPW, NiPMo).
In greater detail, the first coating layer 30 covers laterally the portions of the patterned seed layer 24 which extend over the top of the frontal surface Sfront, as well as the portions of the first patterned barrier layer 22 which extend over the top of the frontal surface Sfront. As a consequence, lower portions of the first coating layer 30 make contact, aside from the first dielectric layer 11, with portions of the first patterned barrier layer 22 which extend over the top of the frontal surface Sfront, as well as overlying portions of the patterned seed layer 24.
The frontal structure 8 furthermore comprises a second coating layer 32, which is typically formed from a noble metal, such as for example gold, palladium or a combination of both (Pd/Au); the combined thickness of the first and second coating layers 30, 32 may for example be greater than 1 μm. Typically, in the step of fabrication, the second coating layer 32 is formed without applying electric fields (“electroless” deposition technique).
In detail, the second coating layer 32 is deposited on top of the first coating layer 30, with which it is in direct contact. The second coating layer 32 thus surrounds the redistribution layer 25 on the top and sides, at a distance, until it makes contact with the first dielectric layer 11.
In practice, the first and the second coating layers 30, 32 form a capping structure, which covers the redistribution layer 25 and makes contact with the first dielectric layer 11.
For practical reasons, the first coating layer 30 is formed by a material (nickel) having a greater hardness compared with the material (copper) which forms the redistribution layer 25, the latter material having a higher conductivity. The first coating layer 30 provides rigidity to the frontal structure 8 during the bonding steps, so as to prevent the deformation of the redistribution layer 25. Furthermore, the first coating layer 30 serves as a barrier against the migration/electromigration of the material forming the redistribution layer 25.
As far as, on the other hand, the second coating layer 32 is concerned, this is formed by a noble metal and thus prevents the underlying metals from being subjected to oxidation or corrosion.
Compared with the first patterned barrier layer 22, this is metal and furthermore serves as a barrier against the migration to the first dielectric layer 11 of the material that forms the redistribution layer 25. Furthermore, the first patterned barrier layer 22 improves the adhesion between the patterned seed layer 24 and the underlying layers.
In light of the above, because of the different mechanical characteristics of the materials that form the redistribution layer 25, the first dielectric layer 11 and the first and second coating layers 30, 32, it is possible for the integrated electronic device 10 to be subjected to excessive mechanical stresses, which may compromise its operation. In particular, the stresses arise for example in the case in which the fabrication process includes the execution of steps with a high thermal budget.
In one embodiment of the present disclosure, an integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region of a first metal material forms a via region which extends into a hole passing through the frontal dielectric layer and an overlaid redistribution region which extends over the frontal surface. A barrier structure includes at least a first barrier region of a second metal material which extends into the hole and surrounds the via region. The first barrier region furthermore extends over the frontal surface. A first coating layer of a third metal material covers the top and the sides of an upper portion of the redistribution region at a distance from the frontal surface. A second coating layer of a fourth metal material extends at a distance from the frontal surface and covers the first coating layer and covers laterally a lower portion of the redistribution region which is disposed on top of portions of the barrier structure which extend over the frontal surface.
For a better understanding of the present disclosure, embodiments thereof are now described, purely by way of non-limiting example and with reference to the appended drawings, in which:
In the following, the present integrated electronic device is described, without any loss of generality, with reference to the differences compared with that shown in
A first embodiment of the present integrated electronic device is shown in
This having been said, the first coating layer, here indicated with 41, covers the top and the sides of an upper portion of the redistribution layer 25 and is disposed at a distance from the first dielectric layer 11, i.e., it is physically separated from the latter. Furthermore, the first coating layer 41 is physically separated from the first patterned barrier layer 22 and from the patterned seed layer 24, given that it extends at the bottom to a height which is higher than the maximum height reached by the patterned seed layer 24. Consequently, the first coating layer 41 leaves a lower portion of the redistribution layer 25 laterally exposed, together with portions of the patterned seed layer 24 and of the first patterned barrier layer 22, these portions being laterally offset with respect to the hole T and being disposed on top of the frontal surface Sfront.
The second coating layer, here indicated with 42, entirely covers the first coating layer 41 and is physically separated from the first dielectric layer 11.
In particular, the second coating layer 42 extends at the bottom as far as laterally covering the exposed portions of the redistribution layer 25 and of the patterned seed layer 24, but leaves exposed portions of the first patterned barrier layer 22. In other words, the second coating layer 42 extends at the bottom to a minimum height which is not higher than the maximum height reached by the first patterned barrier layer 22; therefore, the second coating layer 42 makes contact with the first patterned barrier layer 22.
In practice, in the frontal structure of the integrated electronic device 40, indicated with 48, the first and the second coating layers 41, 42 do not make contact with the first dielectric layer 11, thus reducing the mechanical stress exerted on the passivation structure 21. In an equivalent manner, the integrated electronic device 40 is lacking points at which the first patterned barrier layer 22, the first coating layer 41 and the first dielectric layer 11 are in contact; these points represent points at which the structure formed by the redistribution layer 25 and by the first and second coating layers 41, 42 exerts the maximum mechanical stress during the processes at high temperature.
The embodiment shown in
Initially, as shown in
Subsequently, as shown in
Subsequently, as shown in
The first barrier layer 22′ and the seed layer 24′ are respectively formed from the same materials as the first patterned barrier layer 22 and as the patterned seed layer 24. Furthermore, the first barrier layer 22′ and the seed layer 24′ may both have a thickness greater than 100 nm.
Subsequently, as shown in
The sacrificial layer 50 has a thickness for example of less than 100 nm and may be quickly removed both by means of a dry etch and by means of a wet etch. The sacrificial layer 50 is formed, for example by means of chemical vapor deposition, from silicon nitride, which is deposited for example using a low temperature process, or else from silicon oxide.
Subsequently, as shown in
In greater detail, the window W is such that it exposes a portion of the sacrificial layer 50 covering the portion of seed layer 24′ disposed inside of the hole T and portions of the seed layer 24′ that laterally protrude from the hole T over the frontal surface Sfront.
Subsequently, as shown in
Subsequently, as shown in
In more detail, the redistribution layer 25 and the distal vias V3 form a single monolithic region together with the seed layer 24′, although, for the sake of clarity, the latter layer is shown as separate.
Subsequently, as shown in
For example, the first coating layer 41 is formed on the exposed metal surfaces by means of a deposition technique known as electroless' deposition.
In greater detail, the first coating layer 41 covers the top and, in part, the sides of the redistribution layer 25, but does not make contact with the first barrier layer 22′ and the seed layer 24′, thanks to the protection provided by the sacrificial layer 50.
Subsequently, as shown in
Subsequently, as shown in
In more detail, the etching of the exposed portions of the seed layer 24′ takes place in such a manner as to obtain an etch rate close to zero with regard to the portions of the first barrier layer 22′ that are exposed with this etch. Furthermore, for simplicity of visualization, the effects of this etch as regards the exposed portions of the redistribution layer 25 are not shown; furthermore, the effects on the first coating layer 41 are ignored.
In even further detail, the etching of the exposed portions of the first barrier layer 22′ takes place in such a manner as to obtain an etch rate of approximately zero with regard to the exposed portions of the redistribution layer 25, of the patterned seed layer 24 and of the coating layer 41.
For practical reasons, the redistribution layer 25 and the portions of the patterned seed layer 24 disposed on top of the frontal layer Sfront form a single redistribution region. Similarly, the portion of the patterned seed layer 24 disposed inside of the hole T forms a kind of vertical conductive region together with the distal via V3.
The subsequent formation of the second coating layer 42 thus leads to what is shown in
According to a different embodiment, shown in
The second patterned barrier layer 162 is formed by a material having an etch rate lower than the etch rate of the first patterned barrier layer 122. For example, the second patterned barrier layer 162 may be formed by an alloy of titanium and tungsten having a different percentage of titanium compared with the alloy that forms the first barrier layer 122, or else may be formed by any given material from amongst, for example, titanium nitride (TiN), titanium (Ti), tantalum (Ta) or an alloy of tantalum and tantalum nitride (TaNTa). Furthermore, the second patterned barrier layer 162 has a thickness in the range for example between 4 nm and 40 nm.
In the embodiment shown in
The first coating layer, here indicated with 141, also covers the top and sides of an upper portion of the redistribution layer 25 and is physically separated from the first and from the second patterned barrier layers 122, 162, and also from the patterned seed layer 124, given that the lower part extends down to a minimum height which is higher than the maximum height reached by the patterned seed layer 124.
The second coating layer, here indicated with 142, entirely covers the first coating layer 141 and furthermore covers laterally the portions of the redistribution layer 25 and of the patterned seed layer 124 left exposed by the first coating layer 141, which are disposed on top of the frontal surface Sfront and are laterally offset with respect to the hole T.
More particularly, referring to the protruding surface Sext to indicate the surface that bounds from above the portion of the second patterned barrier layer 162 which laterally protrudes with respect to the patterned seed layer 124, the second coating layer 142 extends at the bottom until it entirely covers the protruding surface Sext, with which it is in direct contact. The second coating layer 142 may, in turn, laterally protrude with respect to the second patterned barrier layer 162.
The embodiment shown in
The embodiment shown in
In detail, subsequent to the operations described with reference to
Subsequently, as shown in
Subsequently, the same operations described with reference to
Subsequently, as shown in
Subsequently, as shown in
Subsequently, as shown in
Following this, as shown in
Subsequently, as shown in
In more detail, the aforementioned selective etches of the portions of the first and of the second barrier layer 122′, 162′ take place in such a manner as not to etch, approximately, either the residual dielectric region 151 or the exposed portions of the seed layer 124′. Furthermore, these etches may take place based on the same chemistry (for example, hydrogen peroxide or a mixture of hydrogen peroxide and ammonium hydroxide) such that, as previously mentioned, the second barrier layer 162′ is formed by a material having a lower etch rate than the etch rate of the first barrier layer 122′. It is however possible for these etches to take place on the basis of different chemistries.
As previously mentioned, for simplicity of description, it may be assumed that, to a first approximation, the etch of the first barrier layer 122′ comprises a negligible etching of the residual material of the second barrier layer.
Subsequently, as shown in
Subsequently, as shown in
Subsequently, the second coating layer 142 is formed, for example by means of an electroless deposition technique, such that it grows on the exposed surfaces of the first coating layer 41 and laterally coats the lower portion of the redistribution layer 25 and the patterned seed layer 124, in such a manner as to obtain the situation shown in
According to a different embodiment, shown in
The third patterned barrier layer 272 is formed by a material having an etch rate higher than the etch rate of the second patterned barrier layer 262. For example, the third patterned barrier layer 272 could be formed by an alloy of titanium and tungsten, or else could be formed by any given material from amongst, for example, titanium nitride (TiN), titanium (Ti), tantalum (Ta) or an alloy of tantalum and tantalum nitride (TaNTa).
In addition, the second patterned barrier layer 262 protrudes laterally both with respect to the underlying first patterned barrier layer (here indicated with 222), with which it bounds the recess 99, and with respect to the overlaid third patterned barrier layer 272. Furthermore, without any loss of generality, the patterned seed layer 224 and the third patterned barrier layer 272 can have the same shape as viewed from above. Again, without any loss of generality, the third patterned barrier layer 272 may protrude laterally with respect to the first patterned barrier layer 222.
In practice, the embodiment shown in
The first coating layer, here indicated with 241, again covers an upper portion of the redistribution layer 25 on the top and sides and is physically separated from the first, from the second and from the third patterned barrier layers 222, 262, 272, and also from the patterned seed layer 224, given that it extends at the bottom down to a minimum height which is higher than the maximum height reached by the patterned seed layer 224.
The second coating layer, here indicated with 242, entirely covers the first coating layer 241 and furthermore covers laterally a lower portion of the redistribution layer 25 and the portions of the patterned seed layer 224 and of the third patterned barrier layer 272 which extend over the frontal surface Sfront, as far as covering the protruding surface Sext, i.e., until contact is made with the overhanging portions of the second patterned barrier layer 262.
The embodiment shown in
The embodiment shown in
In detail, subsequent to the operations described with reference to
Subsequently, operations analogous to those described with reference to
Subsequently, as shown in
Subsequently, as shown in
In greater detail, the three successive etches of the third, of the second and of the first barrier layer 272′, 262′ and 222′ may be carried out based on the same chemistry (for example, hydrogen peroxide or a mixture of hydrogen peroxide and ammonium hydroxide).
Next, as shown in
Subsequently, the second coating layer 242 is formed, for example by means of electroless deposition, such that it grows on the exposed surfaces of the first coating layer 241, in such a manner as to obtain the situation shown in
The advantages that are offered by the present integrated electronic device are clearly apparent from the preceding description. In particular, the present integrated electronic device disposes of a frontal structure such that the passivation structure is subjected to lower mechanical stresses, compared with known devices. Furthermore, in the case in which more than one barrier layer is present, the protruding barrier layer represents a sort of buffer layer, which can give way in the case of excessive stresses, in such a manner as to allow the relaxing of these stresses without further damage being caused inside of the integrated electronic device.
As shown in
In more detail, the lead frame 506 comprises a pad 507, on which the individual die 504 rests, and a plurality of terminals 512, each of which extends in part inside of the packaging region 509 and in part outside. Furthermore, the terminals 512 are electrically coupled to the individual die 504 through the conducting wires 510, which implement corresponding wire bondings and make contact with the redistribution layer 25/palladium layer (detail not visible in
Finally, it will be clear that modifications and variants may be applied to the present integrated electronic device and to the related fabrication process, without straying from the scope of the present disclosure.
For example, the passivation structure may be different compared with that described. Furthermore, the first and the second coating layer, the first patterned barrier layer and, where present, the second and the third patterned barrier layer may have different thicknesses with respect to those described and may be formed from materials different from those described.
It is furthermore possible for the vias formed in a monolithic manner with the redistribution layer to be different from the distal vias. More generally, the level of the vias integrated with the redistribution layer is irrelevant. Even more generally, the same reference to RDL technology, intended as characteristic thicknesses and materials, is irrelevant for the purposes of the present integrated electronic device.
There are furthermore possible embodiments in which a further metal layer, formed for example from gold, extends over the second coating layer.
With regard to the fabrication process, some of the steps described may be carried out in a different order with respect to that described. Furthermore, it is possible for the fabrication process to include steps not described hereinabove, such as for example a step for processing the edges of the die and a thermal treatment, which are for example carried out after having formed the redistribution layer, prior to forming the first coating layer.
The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
Number | Date | Country | Kind |
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102017000087309 | Jul 2017 | IT | national |