Patent Application
20160095221
Disclosed embodiments are directed to integration of electronic elements on backside or a second side of a die which is opposite to an active side or a first side of the die. Exemplary aspects include electronic elements such as thin-film transistors, input/output transistors, diodes, passive devices, etc., on the second side, and through vias such as through silicon vias (TSVs) to connect the first side to the second side.
Advances in the design and manufacture of semiconductor devices have led to shrinking sizes of semiconductor packages, wafers, and dies/chips. As processing needs for modern computer systems, particularly in the area of mobile processing systems increase, there is an ever-increasing demand for integration of a large number of electronic elements on each semiconductor die. Due to limited surface area on the active surface of a semiconductor die, the integration, placement, and routing of electronic elements and components on the semiconductor die presents a well-recognized problem.
For example, conventional integrated circuit designs may use wire-bonding to connect a chip or die, which is mounted upright, to external circuitry or a semiconductor package. Electronic devices/elements/integrated circuit components of the chip are integrated on an active side of the chip. The wire-bonds require input/output (I/O) connections, pads, etc., which are also formed on the active side of the chip, since the chip is mounted face-up on a printed circuit board (PCB), for example. These I/O connections consume relatively large portions of an already limited surface area on the active side.
Another conventional integrated circuit design option involves flip-chip packaging. In a flip-chip, solder balls are formed on a backside of a chip, which is opposite to the active side. Metal connection pads are formed on the active side and connections are made by wire-bonding or through vias through a semiconductor substrate of the chip to the solder balls. Electrical connections to external circuitry are made through the solder balls which may attach to a ball grid array (BGA). However, conventional flip-chip technology also requires placement of I/O connections, metal connection pads to the solder balls, etc., on the active side of the die. Apart from forming the solder balls, the backside of the chip is not utilized for integration of any additional components in conventional flip-chip technology.
Some conventional approaches also include placement of selected components of an integrated circuit or system on a chip (SoC) on a secondary die or chip. For example, I/O ports and/or other electronic elements of an integrated circuit on a first chip may be placed on a second chip in an effort to overcome limitations on surface area on the first chip. However, such solutions introduce additional challenges involved with inter-chip placement and routing, and the interconnections between the two chips may introduce undesirable delays and inefficiencies which may not be tolerated by high performance processing needs.
Additionally, advanced chip design may also involve integration of electronic elements operating in different voltage domains and/or other operating conditions, and the above-discussed approaches do not provide effective solutions to handle such design considerations with shrinking device technologies. Accordingly, there is a need in the art for improved semiconductor device integration techniques which can overcome at least the aforementioned drawbacks in existing solutions.
Embodiments of the invention are directed to systems and methods for integration of electronic elements on a backside of a semiconductor die. For example, exemplary systems and methods include a first semiconductor die with a substrate having a first side and a second side opposite to the first side. A first set of electronic elements is integrated on the first side. A second set of electronic elements is integrated on the second side. One or more through-substrate vias through the substrate are used to couple one or more of the first set of electronic elements and one or more of the second set of electronic elements. The through-substrate vias may be through-silicon vias (TSVs) or a through-glass vias (TGVs). The first semiconductor die may be stacked with a second semiconductor die, with the first side or the second side of the first semiconductor die interfacing an active side of the second semiconductor die.
Accordingly, an exemplary aspect includes a semiconductor device comprising a first semiconductor die with a substrate, the substrate comprising a first side and a second side opposite to the first side. A first set of electronic elements is integrated on the first side and a second set of electronic elements is integrated on the second side. One or more through-substrate vias through the substrate couple one or more of the first set of electronic elements and one or more of the second set of electronic elements.
Another exemplary aspect includes a method of forming a semiconductor device, the method comprising: forming a substrate of a first semiconductor die with a first side and a second side opposite to the first side, integrating a first set of electronic elements on the first side, integrating a second set of electronic elements on the second side, and forming one or more through-substrate vias through the substrate for coupling one or more of the first set of electronic elements and one or more of the second set of electronic elements.
Yet another exemplary aspect includes a system comprising a first semiconductor die with a first side and a second side opposite to the first side, a first set of electronic elements integrated on the first side and a second set of electronic elements integrated on the second side. The system further includes means for coupling one or more of the first set of electronic elements and one or more of the second set of electronic elements.
The accompanying drawings are presented to aid in the description of embodiments of the invention and are provided solely for illustration of the embodiments and not limitation thereof.
Aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternate embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.
The term “embodiments of the invention” does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Further, many embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that specific circuits (e.g., application specific integrated circuits (ASICs)), one or more processors executing program instructions, or a combination of both, may perform the various actions described herein. Additionally, the sequences of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the invention may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, the corresponding form of any such embodiments may be described herein as, for example, “logic configured to” perform the described action.
Aspects of this disclosure relate to integration of electronic elements and integrated circuit components on at least two sides a semiconductor die, or in other words, two faces of the semiconductor die. The sides and faces may be relative to a substrate of the semiconductor die. As such, an exemplary semiconductor die includes a first side and a second side. Without limitation, the first side can include a conventional active side of a die and the second side can include a conventional backside of the die. The second side or the backside is on the opposite side of the substrate as the first side or the active side. However, departing from conventional designs, the second side of a die in this disclosure includes much more than the conventional backside of semiconductor dies. For example, in aspects of this disclosure, the second side also includes electronic elements or integrated circuit components, in contrast to conventional backsides of semiconductor devices which are limited to aforementioned circuit connections, solder balls, etc.
Accordingly, in this disclosure, the use of the terms “active side” and “backside” are merely utilized for the sake of explanation, in order to provide distinctions of exemplary aspects with conventional designs. It will be understood that the use of the term “active” with reference to the first side is not meant to convey that the second side excludes active components. Thus, in exemplary aspects, both the first and second sides may include electronic elements and integrated circuit components. In other words, exemplary aspects of this disclosure pertain to improvements over conventional designs, where such conventional designs limit integration of electronic elements to a conventional active side and at best utilize the conventional backside of a die for interconnects, solder balls, and the like.
In more detail, the first side of the exemplary semiconductor die includes a first set of one or more electronic elements and the second side includes a second set of one or more electronic elements. As used herein, the term “electronic elements” are meant to include semiconductor devices such as transistors, gates, and other such components of integrated circuits. The term “electronic elements” includes active devices such as transistors, as well as, passive devices such as inductors, capacitors, etc. More importantly, the term “electronic elements” in this disclosure excludes circuit components such as metallization layers, wires, nets, interconnects, solder balls, etc., whose main function is for providing electrical connections. Thus, references to the electronic elements integrated on the first/second sides, for example, are meant to preclude solder balls in the aforementioned conventional flip-chip design, although in exemplary aspects, solder balls may also be integrated in addition to the electronic elements on the first/second sides.
Further, the exemplary semiconductor die also includes through vias for coupling the first side and the second side, and more specifically, for electrically coupling at least one of the first set of electronic elements and at least one of the second set of devices. In one non-limiting example, the semiconductor die may be formed of a silicon substrate as known in the art, in which case the through vias may be through-silicon vias (TSVs). In another non-limiting example, the semiconductor die may be formed of a glass substrate, in which case the through vias may be through-glass vias (TGVs). One of skill in the art will be able to extend aspects of this disclosure to other known technologies for forming the semiconductor dies, as well as the through vias, without departing from the scope of this disclosure. Further, the through vias may include only a part of an electrical connection between an electronic element of the first set and an electronic element of the second set, as there may be metal wires on the first and/or second side to complete the electrical connection. In other words, the through vias need not provide the only interconnection path between the first and second set of electronic elements, and as such, may serve the purposes of electrically coupling the first and second sides in conjunction with metal wires, nets, interconnects as known in the art.
Accordingly, by integrating electronic elements on the second side of the semiconductor die, exemplary aspects exploit additional surface area on the semiconductor die which was previously not utilized on the conventional backside of semiconductor dies. In some non-limiting examples, the second side may be particularly well-suited for electronic elements such as thin-film transistors (TFTs), I/O transistors or gates (which may include I/O TFTs), diodes (including thin-film diodes), passive devices such as parallel plate capacitors, etc. The second side may also include electronic elements related to electrostatic discharge (ESD) protection of the semiconductor die. Accordingly, the second set of electronic elements integrated on the second side of the semiconductor die may include, without limitation, electronic elements made from thin-film technologies, passive devices, and/or ESD elements. Thus, these second set of electronic elements may be moved out of the first side of the semiconductor die in order to relieve congestion on the first side. The first set of electronic elements integrated on the first side may include conventional electronic elements (e.g., conventional transistors such as complementary metal oxide semiconductor (CMOS) transistors) which are part of an integrated circuit or system on a chip. However, the first set of electronic elements is not limited in this manner, and may also include thin-film devices and passive devices in some aspects. The nature and type of electronic elements which are integrated on either the first or second side may be specific to particular design needs and not limited to the above examples. For example, a designer may take into consideration the placement and routing requirements for a particular semiconductor die and apportion electronic elements between the first and second sides which can be coupled by one or more through vias.
In additional aspects, the above semiconductor die with the first and second sides as above may also be stacked with one or more other semiconductor dies. Through silicon stacking (TSS) as known in the art may be used for the stacking. The one or more other semiconductor dies may be conventional semiconductor dies with a conventional active side and a conventional backside, or they may be, without limitation, exemplary semiconductor dies with first and second sides of electronic components as discussed above. Moreover, since the exemplary semiconductor die has electronic elements on both the first and second sides, either the first or the second side may be configured to interface another semiconductor die for the stacking. The above and additional aspects will be further explained with reference now to the figures.
With reference to
In the illustrated example, semiconductor die 100 may be a silicon die, and as such, substrate 104 may be formed of silicon. Accordingly, substrate 104 includes one or more through vias representatively illustrated as through-silicon via (TSV) 112. TSV 112 is configured to electrically couple components of first side 102 to components of second side 106. More specifically, TSV 112 may couple one or more metal layers or interconnects 110b on first side 102 and one or more metal layers or interconnects 108d on second side 106. Further, in some aspects, substrate 104 need not be dedicated to only through vias, but may also be used to form additional integrated circuit components such as trench capacitors 114.
With reference now to
As shown, die 202 is a conventional chip, without limitation, and as such, may be stacked with semiconductor die 100 in a flip-chip manner. Accordingly, the face or active side of die 202 may be interfaced with second side 106 which includes the conventional backside of semiconductor die 100. Thus, this stacking is also referred to as a “face-to-back stacking” where the face of the tier 2 die is stacked with the backside of the tier 1 die, relating the illustrated structure to legacy or conventional terms. More particularly, exemplary semiconductor package includes die 202 stacked to semiconductor die 100 by means of a first ball grid array including solder balls 204. Solder balls 204 are connected to interconnects 108d, which may be coupled to TSV 112. TSV 112 provides coupling of second side 106 to first side 102 of semiconductor die 100, as previously discussed. Thus, TSV 112 provides a means for coupling first side 102 of semiconductor die 100 to die 202 in a TSS fashion. Further, in some aspects, semiconductor die 100 may be further stacked to a third die (not shown) interfacing first side 102, or as in the illustrated aspects, attached to package substrate 208 through a second ball grid array including solder balls 206. Solder balls 206 may couple package substrate 208 to interconnects 110b on first side 102 of semiconductor die 100. Additionally, semiconductor package 200 may include mold 210 to encapsulate both dies, semiconductor die 100 and die 202.
Referring to
In contrast to semiconductor package 200 of
Thus, as shown in the TSS stacking examples of
With reference now to
Next, the chip may be configured as a flip-chip and carrier mounted; a thin TSV section may be revealed/exposed if a TSV is already present—Block 404. Following this, a thin film transistor (TFT) base coat may be applied on a second side (e.g., second side 106) or backside of the chip, with blanket isolation for forming TFT devices—Block 406. Trenches may be patterned for trench capacitors (e.g., trench capacitors 114) on the second side—Block 408. Deposition and patterning may be performed for electronic elements on the second side, such as, for gates of transistors (e.g., 108a), top electrodes for parallel plate capacitors (108b), etc.—Block 410. If the oxide for the parallel plate capacitors are different from the oxides for the gates of transistors, separate patterning and film deposition may be performed for these different oxides—Block 412. Next the TFT transistors, body of diodes (e.g., 108c) and bottom electrodes for the parallel plate capacitors may be patterned—Block 414. Deposition of the films may be performed for the transistors, diodes, trench capacitors, and parallel plate capacitor's bottom electrode—Block 416. In Block 416, an amorphous transparent conductive oxide (ATCO) film may be used for the bottom electrode in some aspects.
Interlayer dielectric (ILD) may be deposited on the second side or backside to form contacts (e.g., for the face-to-back configuration illustrated in
Passivation is performed on the second side or back side and bumps/micro-bumps or BGA including solder balls 204 are added—Block 426. The semiconductor die processed as above can now be assembled for stacking (for example in the TSS stacking example of face-to-back stacking in FIG. 2)—Block 428. The semiconductor die can now be stacked with a second die (e.g., die 202), as in the above discussed sections.
It will be appreciated that embodiments include various methods for performing the processes, functions and/or algorithms disclosed herein. For example, as illustrated in
In
In
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Accordingly, an embodiment of the invention can include a computer readable media embodying a method for forming a semiconductor die with electronic elements integrated on a backside of the semiconductor die. Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the invention.
While the foregoing disclosure shows illustrative embodiments of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
