The present invention relates generally to semiconductor fabrication and, more particularly, to fabrication of interconnects having substantially curvilinear interconnect interfaces.
Integrated circuits are manufactured by fabricating electronic devices in a semiconductor substrate. Multi-level interconnections are formed to connect the devices to create desired circuits.
Aluminum and aluminum alloys are the most widely used interconnection metallurgies for integrated circuits. However, in response to the scaling of feature sizes to submicron and deep-submicron technology nodes, copper is also employed as an interconnection metal due to its low electric resistivity and its high resistance to electromigration (EM) and stress voiding.
However, copper implementation can suffer from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. The diffusion can cause corrosion of the copper, which can result in loss of adhesion, delamination, void formation, and electric failure of the parent circuitry. A copper diffusion barrier is therefore employed for most copper interconnects. For example, a diffusion barrier is formed between copper components and inter-layer dielectrics, other insulators, and silicon substrates.
Damascene processing is often employed to form such copper conductors and copper diffusion barriers. However, during damascene processing, copper residue and other residue materials can adhere to the openings in which interconnects and other copper components are to be formed. The residue materials can contaminate the dielectric layer and reduce the reliability of the interconnects. The residue materials can also be detrimental to the quality of interfaces between conductive lines and plugs, thereby decreasing device reliability.
Accordingly, what is needed is an interconnect structure and method of manufacturing thereof that addresses the above-discussed issues.
The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
Referring to
Thus, referring to
The substrate 210 may comprise an elementary semiconductor such as crystal silicon, polycrystalline silicon, amorphous silicon, and/or germanium. The substrate 210 may also or alternatively comprise a compound semiconductor such as silicon carbide and/or gallium arsenic. The substrate 210 may also or alternatively comprise an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, and/or GaInP, or any combination and/or alloy thereof. Furthermore, the substrate 210 may be or comprise a bulk semiconductor such as bulk silicon, and such a bulk semiconductor may include an epi silicon layer. The substrate 210 may also be or comprise a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, or a thin-film transistor (TFT) substrate. The substrate 210 may also comprise a multiple silicon structure or a multilayer compound semiconductor structure.
The conductive layer 220 may be or comprise aluminum, an aluminum alloy, copper, a copper alloy, tungsten, combinations and/or alloys thereof, and/or other conductive materials. The conductive layer 220 may be a conductive feature connecting semiconductor devices, integrated circuit devices and/or components, and/or interconnects therein. The depth d1 of the conductive layer 220 may range between about 1500 Å and about 5000 Å. For example, in one embodiment, the depth d1 is about 3500 Å.
The substrate 210 provided in step 110 may include a dielectric layer 230 overlying the semiconductor substrate 210 and the conductive layer 220. The dielectric layer 230 may be an etch stop layer and/or a diffusion barrier layer, and may comprise one or more individual layers. The dielectric layer 230 may be or comprise silicon nitride and/or other dielectric and/or etch stop materials.
Referring to
As shown in
If necessary or desired, the exposed portion of the dielectric layer 230 proximate the opening 320 may also be removed, such as by dry etching and/or other processes, to expose a portion of the underlying conductive layer 220. Removal of the dielectric layer 230 may employ a chemistry comprising CH4 as a primary gas, possibly mixed with O2 and N2 to adjust the etching rate and selectivity.
Referring to
In one embodiment, the barrier layer 410 may be formed prior to removing a portion of the dielectric layer 230. In such an embodiment, a bottom portion of the barrier layer 410 and a portion of the dielectric layer 230 may be sequentially removed, such as by dry etching and/or sputtering.
The bottom portion of the barrier layer 410 proximate the conductive layer 220, whether formed prior to or after removing a portion of the dielectric layer 230, may be removed by in-situ sputtering utilizing SIP or IMP. Consequently, at least a portion of the conductive layer 220 may be exposed.
Referring to
The recess 510 may be formed by etching the conductive layer 220, possibly by in-situ sputtering utilizing SIP or IMP. For example, commercial SIP PVD systems or IMP PVD systems provide cleaning models of controllable argon ion (Ar+) sputtering mechanism to recess the exposed conductive layer 220 to a predetermined thickness.
As shown in
In one embodiment, the profile 520A is formed by etching the conductive layer 220 utilizing SIP, possibly employing an SIP-PVD system, such as the INOVA HCM provided by Novellus Systems, Inc., of San Jose, Calif. The SIP-PVD system may also be employed to deposit diffusion barrier layers and/or seed layers, such as in embodiments in which the recess 510A is or comprises a high-aspect via opening, as described below. An SIP-PVD system may generate Ar ions which reach and bombard the conductive layer 220. The Ar ions are directed by adjusting a bias of the SIP system to initially bombard the sidewalls of the opening 320 and then be refracted to bombard the conductive layer 220, thereby resulting in the profile 520A.
Similarly, the bias of the SIP-PVD system can be adjusted to direct Ar ions bombarding the conductive layer 220 to form an opening 510B with a substantially curvilinear, concave profile 520B as shown in
The depths d3, d4, d5 of each of these profiles may be at least 200 Å, and may range between about 300 Å and about 800 Å. In one embodiment, the depths d3, d4, d5 range between about 500 Å and about 700 Å. The profiles 520A, 520B, 520C, 520D of the recessed conductive layer 220 are determined by the incident angle of Ar ions, which may be tuned according to the SIP bias or magnetic field adjustment and the aspect ratio of the opening 320. The incident angle may also affect the parallelism of the sidewalls of the profile, such that the sidewalls may be substantially parallel or, as with the trapezoidal profile 520D, such that the sidewalls are not substantially parallel. For example, the sidewalls of the trapezoidal profile 520D may be angularly offset by an angle ranging up to about 30°.
Referring to
Referring to
The contact interface between the conductive layer 220 and the conductive plugs 710A-710D is increased by the recess 510 in the conductive layer 220. The contact area of the interface may further be modified by tuning the incident angle of Ar ions. Moreover, the conductive material proximate the bottom of the conductive layer 220 which may become damaged during etching operations may be removed during the formation of the recess 510 and subsequently filled with newly grown or otherwise deposited conductive material. Thus, stress migration (SM) and electromigration (EM) resistance of interconnects formed thereof may be improved.
Thus, the present disclosure provides a method of fabricating an interconnect structure, including providing a semiconductor substrate having a first conductive layer thereon, and forming a dielectric layer overlying the semiconductor substrate and the first conductive layer. An opening is formed in the dielectric layer extending to the first conductive layer. A portion of the first conductive layer is removed through the opening to form a recess having a substantially curvilinear profile. The opening and the recess are filled with a second conductive layer. In one embodiment, the method includes forming a diffusion barrier layer at least partially lining the opening by employing one of a self-ionized plasma (SIP) system and an ionized metal plasma (IMP) system. Moreover, the conductive layer may be recessed by in-situ recessing employing one of the SIP system and the IMP system.
The present disclosure also provides an interconnect structure including, in one embodiment, a first conductive layer located in a substrate, and a dielectric layer overlying the first conductive layer and having an opening extending to the first conductive layer. A second conductive layer is located in the opening and contacts a portion of the first conductive layer, wherein an interface between the first and second conductive layers substantially conforms to a substantially curvilinear profile.
An integrated circuit device is also introduced in the present disclosure. In one embodiment, the integrated circuit device includes a plurality of semiconductor devices coupled to a substrate, and an interconnect structure coupling ones of the plurality of semiconductor devices. The interconnect structure includes a plurality of first conductive layers and a dielectric layer overlying ones of the plurality of first conductive layers and having a plurality of openings each extending to one of the plurality of first conductive layers. The interconnect structure also includes a plurality of second conductive layers located in ones of the plurality of openings and each contacting a portion of one of the plurality of first conductive layers, wherein each interface between corresponding ones of the first and second conductive layers substantially conforms to a substantially curvilinear profile.
Although embodiments of the present disclosure have been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.