Patent Application
20210242154
The present disclosure is generally directed to semiconductor devices, and in several embodiments, more particularly to interconnect structures for die-to-substrate and/or three-dimensional integration interconnects.
Microelectronic devices, such as memory devices, microprocessors, and light emitting diodes, typically include one or more semiconductor dies mounted to a substrate and encased in a protective covering. The semiconductor dies include functional features, such as memory cells, processor circuits, interconnecting circuitry, etc. Semiconductor die manufacturers are under increasing pressure to reduce the volume occupied by semiconductor dies while increasing the capacity and/or speed of the resulting encapsulated assemblies. To meet these demands, semiconductor die manufacturers often stack multiple semiconductor dies vertically on top of each other to increase the capacity or performance of a microelectronic device within the limited volume on the circuit board or other element to which the semiconductor dies are mounted. For vertically stacked semiconductor dies, through-silicon vias (TSV) are often used. Such TSVs on adjacent semiconductor dies are typically electrically connected to each other using direct physical coupling in which the bond pads of one die are directly bonded to the bond pads of the other.
Individual or stacked semiconductor dies are typically electrically connected through metal bond pads on the dies, or by pillars formed on the bond pads. When the dies are electrically connected to a substrate, the pads or pillars typically form a connection to exposed traces in the substrate using solder bumps attached to the metal pads or pillars. During assembly, the solder bumps are reflowed to form the connection from die-to-substrate (D2S). Conventional assembly methods typically result in a solder connection confined to the tip of the metal pillar and the top side of the trace in the substrate. Often, the bond pads of each semiconductor die are spaced closely together such that when solder is reflowed during the stacking process to form the solder bumps, the solder can form an electrical “bridge” between adjacent metal pillars to electrically connect adjacent pillars and short the semiconductor device.
The technology disclosed herein relates to semiconductor devices, systems with semiconductor devices, and related methods for manufacturing semiconductor devices. The term “semiconductor device” generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. Furthermore, the term “semiconductor device” can refer to a finished device or to an assembly or other structure at various stages of processing before becoming a finished device.
Depending upon the context in which it is used, the term “substrate” can refer to a structure that supports electronic components (e.g., a die), such as a wafer-level substrate, a singulated die-level substrate, or another die for die-stacking applications. A person having ordinary skill in the relevant art will recognize that suitable steps of the methods described herein can be performed at the wafer-level or at the die level. Furthermore, unless the context indicates otherwise, structures disclosed herein can be formed using conventional semiconductor-manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating, and/or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, chemical-mechanical planarization, or other suitable techniques.
In several embodiments, a semiconductor die includes at least one contact (e.g., bond pads or portions of TSVs that extend through the die) exposed at a surface. In these embodiments, an interconnect structure is electrically coupled to the contact for forming electrical connections with other components of the semiconductor device. In some embodiments, the interconnect structure includes conductive metal pillars on the bond pads of the die that are configured to electrically couple to traces exposed in the substrate (e.g., another die in a die-stacking application, a printed circuit board, a die-level or wafer-level substrate, etc.). As noted above, such connections are typically referred to as D2S connections.
In some conventional interconnect structures, pillars are formed on bond pads of a die. The pillars are electrically coupled to traces in a substrate by reflowing or reforming solder material at the tip of the pillar. The solder material contacts a surface on the pillars and a surface on the traces to form an electrical connection. In these configurations, the limited surface area of the pillars and traces that interfaces the solder material causes a relatively weak structural connection. D2S interconnect methods are vulnerable to a variety of reliability issues during assembly, including misalignment, solder bridging, solder slumping, incomplete wetting, die warpage, edge or corner connections, coefficient of thermal expansion mismatch, and low mechanical strength, among others. As array configurations increase in density, the bond pads of each die can have a greater pitch, which increases the tendency of encountering the above difficulties.
In some embodiments described herein, an additional conductive structure is formed at an end of the pillar opposite the die. The additional structure includes a trace receiver configured for retention of the solder material. As will be described in greater detail below, such trace receivers are formed with one or more voids or cavities having at least one opening, and in several embodiments the void or cavity has a shape complementary to the shape of the traces in the substrate (e.g., the cavity of the trace receiver generally corresponds to the size, shape, pitch, depth, etc., of the surfaces of the trace). For example, the receivers can be a generally elongate bar with three substantially rectilinear sides exposed in the substrate such that the cavity has a C-shaped opening facing away from the pillar toward the trace. In these embodiments, the size and shape of the cavity in the trace receiver may be configured to allow a solder material gap between the trace receiver and the trace when the die is placed in an assembled position relative to the substrate. In other embodiments, the shape of the void or cavity is any shape suitable to interface the traces in the substrate (e.g., a curved interior surface).
Among other advantages over conventional technology, the trace receiver configuration described herein (a) aids in alignment of the pillars with the traces, (b) provides greater mechanical stability, (c) can withstand multiple reflows of the solder material when assembling multi-die stacks, (d)n can accommodate a higher degree of die warpage, (e) reduces solder bridging, (f) allows tighter pitch interconnect and substrate designs, (g) assists in non-conductive film processing (NCF), and (h) allows for tighter bond line control. The configurations of the present technology may be described herein in reference to TSV and/or three-dimensional integration (3DI); however, the present technology also applies to other interconnect types, including flip chip bonding (FC), direct chip attachment (DCA), and D2S, among others. The description of the present technology in conjunction with a specific configuration should not be construed as limiting the applications of the present technology.
The description and illustration of the shapes of the trace receivers and traces herein are exemplary, and should not be construed as limiting the scope of the present disclosure. In this regard, in several embodiments, the shape of the traces in the substrate is any shape created by suitable manufacturing processes to expose conductive material enabling an electrical connection, and such a shape may vary between substrates, traces on the same substrate, and/or adjacent traces. Likewise, in other embodiments, the shape of the cavity in the trace receiver is any suitable shape configured to enable an electrical connection with the traces, and may not necessarily be shaped complementarily to the shape of the traces (e.g., an arcuate cavity in the trace receiver is compatible with a substantially rectilinear trace, etc.). In these embodiments, the trace receiver is sized and shaped to electrically connect to the trace and form a bond having an increased mechanical strength compared to conventional technology. Further, the cavity in the trace receiver is configured to substantially confine the solder material to the cavity such that solder to solder shorting and electrical bridging is prevented.
As used herein, the terms “vertical,” “lateral,” “upper,” and “lower” can refer to relative directions or positions of features in the semiconductor devices in view of the orientation shown in the Figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of a page than another feature. These terms, however, should be construed to include semiconductor devices having other orientations, such as inverted or inclined orientations where top/bottom, over/under, above/below, up/down, left/right, and distal/proximate can be interchanged depending on the orientation. Moreover, for ease of reference, identical reference numbers are used to identify similar or analogous components or features throughout this disclosure, but the use of the same reference number does not imply that the features should be construed to be identical. Indeed, in many examples described herein, identically numbered features have a plurality of embodiments that are distinct in structure and/or function from each other. Furthermore, the same shading may be used to indicate materials in cross section that can be compositionally similar, but the use of the same shading does not imply that the materials should be construed to be identical unless specifically noted herein.
The present disclosure may also reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the new technology. Also, in this regard, the present disclosure may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. For the purposes of the present disclosure, the phrase “at least one of A, B, and C,” for example, means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C), including all further possible permutations when greater than three elements are listed.
In some embodiments of the present technology, the substrate 120 includes a dielectric material 124, (e.g., a passivation material, a polyimide material, solder resist/mask, and/or other materials used to cover a top surface of a semiconductor device) and conductive traces 122 having peripheral surfaces 128 and a distal surface 132. The insulating material 124 at least partially covers a surface of the substrate 120 and is locally removed to form an open area 126 to at least partially expose the conductive traces 122. The insulating material 124 may be removed to a depth that exposes the peripheral surfaces 128 of the traces 122.
The semiconductor die 110 generally includes a plurality of electrically conductive contacts 112 exposed at a surface of the semiconductor die 110 that are electrically coupled to an integrated circuit of the semiconductor die 110 and are configured to be electrically coupled to another semiconductor die of a die stack or a another type of substrate (e.g., a printed circuit board). In some embodiments, the contacts 112 are bond pads, while in other embodiments, the contacts 112 can be a portion of a via (e.g., a TSV) that extends partially or completely through the semiconductor die 110. The integrated circuitry of the semiconductor die 110 can include a memory circuit (e.g., a dynamic random memory (DRAM)), a controller circuit (e.g., a DRAM controller), a logic circuit, and/or other circuits or combinations of circuits.
In some embodiments, the interconnect assembly 130 includes conductive (e.g., metal) pillars 114 projecting from the contacts 112 on the semiconductor die 110 and extending in a direction generally perpendicular to the semiconductor die 110. However, in other embodiments, the pillars 114 extend at an angle between 85° and 90° from the semiconductor die 110. In further embodiments, pillars 114 extend at an angle between 88° and 90° from the semiconductor die 110. The pillars 114 may have a length configured to provide desired spacing between the semiconductor die 110 and the substrate 120 when the semiconductor device 100 is assembled.
In conventional semiconductor devices, the pillar is generally electrically connected to the traces using an exposed solder material (e.g., the solder material is not retained by any structure). In contrast, embodiments of the present technology include trace receivers 140 at the ends of the pillars 114 that are configured to retain a quantity of a solder material 142. The trace receivers 140 may have a length in a direction corresponding to a longitudinal axis of the trace 122 that is smaller than the length of the exposed trace 122 in the substrate 120 (see, e.g.,
As shown in
The cavity 144 of individual trace receivers 140 may be at least partially filled with the solder material 142 to form the electrical connection with the traces 122 upon assembly of the semiconductor device 100. The solder material 142 may conform to the shape of the cavity 144 to generally correspond to the shape of the trace 122 (e.g.,
The components of the interconnect assembly 130 are generally formed from conductive materials, such as copper, nickel, gold, etc., and combinations thereof. In some embodiments, the pillar 114 and the trace receiver 140 may be formed using any suitable patterning method, such as using subtractive processing with a photomask to form a pit in which the trace receiver 140 can be plated.
From the foregoing, it will be appreciated that specific embodiments of the new technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the present disclosure. Accordingly, the invention is not limited except as by the appended claims. Furthermore, certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the present disclosure. Accordingly, the present disclosure and associated technology can encompass other embodiments not expressly shown or described herein.
