The following description relates to integrated circuits (“ICs”). More particularly, the following description relates to manufacturing IC dies and wafers.
Microelectronic elements often comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide, commonly called a semiconductor wafer. A wafer can be formed to include multiple integrated chips or dies on a surface of the wafer and/or partly embedded within the wafer. Dies that are separated from a wafer are commonly provided as individual, prepackaged units. In some package designs, the die is mounted to a substrate or a chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board (PCB). For example, many dies are provided in packages suitable for surface mounting.
Packaged semiconductor dies can also be provided in “stacked” arrangements, wherein one package is provided, for example, on a circuit board or other carrier, and another package is mounted on top of the first package. These arrangements can allow a number of different dies or devices to be mounted within a single footprint on a circuit board and can further facilitate high-speed operation by providing a short interconnection between the packages. Often, this interconnect distance can be only slightly larger than the thickness of the die itself. For interconnection to be achieved within a stack of die packages, interconnection structures for mechanical and electrical connection may be provided on both sides (e.g., faces) of each die package (except for the topmost package).
Additionally, dies or wafers may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes. This can include stacking a layer of one or more dies, devices, and/or wafers on a larger base die, device, wafer, substrate, or the like, stacking multiple dies or wafers in a vertical or horizontal arrangement, and various combinations of both.
Dies or wafers may be bonded in a stacked arrangement using various bonding techniques, including direct dielectric bonding, non-adhesive techniques, such as ZiBond® or a hybrid bonding technique, such as DBI®, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), an Xperi company. The bonding includes a spontaneous process that takes place at ambient conditions when two prepared surfaces are brought together (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety).
When bonding stacked dies using a direct bonding technique, it is usually desirable that the surfaces of the dies to be bonded be extremely flat and smooth. For instance, in general, the surfaces should have a very low variance in surface topography (i.e., nanometer scale variance), so that the surfaces can be closely mated to form a lasting bond. One or more bonding surfaces of the dies or wafers is usually planarized, using chemical-mechanical polishing (CMP), or the like, to achieve the extremely flat and smooth surface(s) desired for bonding.
Respective mating surfaces of the dies or wafers to be bonded (which may comprise silicon, or another suitable material) often include conductive interconnect structures (which may be metal) embedded within an inorganic dielectric layer (e.g., such as an oxide, nitride, oxynitride, oxycarbide, carbides, nitrocarbides, diamond, diamond like materials, glasses, ceramics, glass-ceramics, and the like) at the bonding surface.
The conductive interconnect structures may be formed by damascene techniques (for example), and may include structures having varying widths and sizes. The conductive interconnect structures can be arranged and aligned at the bonding surface so that conductive interconnect structures from the respective die surfaces are joined during the bonding. The joined interconnect structures form continuous conductive interconnects (for signals, power, heat transmission, mechanical stability, etc.) between the stacked dies or wafers.
The exposed surfaces of embedded conductive interconnect structures may also be planarized, separately or together with the bonding surfaces of the dies or wafers. The profile and/or topography of the exposed surfaces of the conductive interconnect structures can be important to forming reliable continuous conductive interconnects between the dies or wafers, as well as important to forming reliable dielectric-to-dielectric bonds between the dies or wafers.
The detailed description is set forth with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.
For this discussion, the devices and systems illustrated in the figures are shown as having a multiplicity of components. Various implementations of devices and/or systems, as described herein, may include fewer components and remain within the scope of the disclosure. Alternatively, other implementations of devices and/or systems may include additional components, or various combinations of the described components, and remain within the scope of the disclosure.
Overview
Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.
In some embodiments, one or more protective layers may also be deposited within unintentional or intentionally recessed portions of conductive interconnect structures to prevent or eliminate atom migration (e.g., to suppress surface mobility) within the recessed portions. Protective layers may include conductive or nonconductive materials in various embodiments.
Various implementations and arrangements are discussed with reference to electrical and electronics components and varied carriers. While specific components (i.e., dies, wafers, integrated circuit (IC) chip dies, substrates, etc.) are mentioned, this is not intended to be limiting, and is for ease of discussion and illustrative convenience. The techniques and devices discussed with reference to a wafer, die, substrate, or the like, are applicable to any type or number of electrical components, circuits (e.g., integrated circuits (IC), mixed circuits, ASICS, memory devices, processors, etc.), groups of components, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.), and the like, that may be coupled to interface with each other, with external circuits, systems, carriers, and the like. Each of these different components, circuits, groups, packages, structures, and the like, can be generically referred to as a “microelectronic component.” For simplicity, unless otherwise specified, components being bonded to another component will be referred to herein as a “die.”
Referring to
As shown at
Referring to
In general, the higher the metal pattern density, the greater the erosion. Similarly, the larger the area of the exposed surface of the conductive interconnects 114, the deeper the dishing defect 116. Both result in a notable variance in the overall surface topography of the die or wafer. The variance may be enough to weaken a direct bond or reduce the reliability of the bond at the locations of the surface variance (including reducing the reliability of metal to metal bonds).
While some recessing may be desirable, as discussed further below, a consequence of undesirable dishing on the exposed surface of conductive interconnect structures 114 can include the need for higher than desirable temperatures to bond the prepared devices 118. This can limit the types of devices that can be bonded or limit the size of the interconnects 114 used. Further, some interconnect structures 114 with large surface areas can experience dishing 116 that may be too deep to form a reliable diffusion bond. For instance, the metal of the structure 114 may not expand enough at annealing temperatures to form the bond. If a bond is formed, it may be defective and unreliable.
For example, in some cases as shown at
An example of an attempt at mitigating the effects of excessive dishing 116 is shown by the process 200 at
As shown at block D, interconnect structures 204 with smaller widths (L2) and smaller exposed surface areas than the larger widths (L1) and larger surface areas of the interconnect structures 114 can be formed (using single or dual damascene processes, for instance) in the added layer 202. The new interconnect structures 204 extend through the added bonding layer 202 and make electrical contact with the dished conductive structures 114 below. The goal is to reduce the exposed metal area on the new bonding layer 202 to reduce surface variance for a more reliable direct bond with stacked substrates 206 (see block E). However, the process of adding an additional bonding layer 202 can add 10 or more manufacturing steps, greatly increasing the cost of the devices 118 produced. Further, the new interconnect structures 204 (for example with a width L2) tend to be much smaller in area than the original structures 114 (for example with a width L1) below, often negatively affecting electrical connection properties and limiting wiring design freedom.
Example Implementations
In various implementations, innovative techniques and devices are used to mitigate the effects of dishing and recesses 116 in the surface of interconnect structures 114 of various sizes (including large area structures, for instance having a width or diameter of 10 microns or more), to form reliable low temperature metallic bonds. The techniques and devices are effective to prepare a direct bonding surface 112 on dies and wafers having embedded conductive interconnect structures 114 with varying widths (e.g., diameters), dimensions, and sizes, including mixed sizes on a single die surface 112, for instance structures having a width or diameter of 1 micron to over 1000 microns. Further, the techniques and devices allow the use of a standard manufacturing technique for surface 112 preparation on such varied dies and wafers. In the implementations, an embedded layer 304 (see
Referring to
As discussed above, in some examples a damascene technique, or the like, may be used to form embedded conductive structures 114 in the insulating layer 102 of the die or wafer. A barrier layer 106 may be deposited over one or more cavities 104 within the insulating layer 102, followed by a seed layer 108, prior to depositing the material of the conductive interconnect structures 114, such that the barrier layer 106 is disposed between the conductive interconnect structures 114 and the insulating layer 102. The cavities 104 may be of different sizes (i.e., volumes and widths), having different areas and located with various spacing relative to each other, as desired and/or by design. A barrier layer 106 may be comprised of tantalum or titanium or cobalt containing materials, for example, or other conductive materials, to prevent or reduce diffusion of the material of the conductive interconnect structures 114 into the insulating layer 102.
As shown at
Forming a bonding surface 112 includes finishing the surface 112 of the insulating layer 102 to meet dielectric roughness specifications and any metallic layers (e.g., copper traces, structures, pads, etc.) to meet recess specifications, to prepare the surface 112 for direct bonding. In other words, the bonding surface 112 is formed to be as flat and smooth as possible, with very minimal surface topography variance.
Referring to
However, as discussed above, a result of a discontinuity in the properties (difference in mechanical properties, polishing rates, etc.) of the conductive material 110 (e.g., metal, for example copper, aluminum, etc.) of the interconnect structures 114 and the insulator material 102 (e.g., silicon dioxide, etc.) of the die or wafer surface, and their respective interactions with the polishing pad, polishing slurry, and other process parameters, the planarizing can produce dielectric erosion 402 (see
In various implementations, as shown at
For instance, as shown at
In some cases, as shown at
In other cases, where the embedded layer 304 comprises a conductive material, the embedded layer 304 has the previously discussed qualities (e.g., suppressing surface mobility within the recess, forming a desirable bonding surface with low surface topography variance, etc.), and also assists in conducting the signal, power, etc. at the unified conductive structure 310. The conductive material (e.g., tungsten, an alloy of tungsten, a nickel alloy, or the like) of the embedded layer 304 may be selected to have predetermined low surface mobility tendencies, reducing or avoiding atom migration. In some cases it may be preferable for the melting point of the embedded layer 304 to be higher than that of the material 110 of the conductive interconnect structure 114. In some cases, the embedded layer 304 may be comprised of multiple metals or like materials.
The embedded layer 304 disclosed herein is distinguished from the sealing layer, as described in U.S. Pat. No. 8,809,123 to Liu et al., which has properties such that when the sealing layer (such as germanium, tin, or the like) is combined with the material of the conductive pads (e.g., copper) and heated to a predetermined temperature, a metal in a eutectic phase is formed. In contrast, the embedded layer 304 of the instant disclosure lines or coats the portion (e.g., the recess 116) of the exposed surface of the conductive interconnect structure 114, reducing the gap of the recess 116 to form a more flat bonding surface and covering the exposed metal of the interconnect structure 114 to suppress atom migration at the recess 116.
Referring to
In various implementations, the thickness of the embedded layer 304 is greater than a thickness of the barrier layer 106 deposited during the damascene process. For instance, the embedded layer 304 may have a thickness of about 15 to 30 nanometers over the surface of the recess 116. In other implementations, the embedded layer 304 may be thicker than 30 nanometers for some recesses 116. For instance, the depth of the recess 116 may be about 1 to 5 microns, in some examples. In some implementations, the thickness of the embedded layer 304 is less than a width (or diameter) of the recess 116.
In various embodiments, a width (or diameter) of the surface area of the embedded layer 304 is less than a width (or diameter) of the otherwise exposed surface of the conductive interconnect structure 114. For instance, a width or diameter of the embedded layer 304 may be less than 50%, 20%, 10%, 5%, or 2% of a width or diameter of the surface of the conductive interconnect structure 114, in various examples.
In some embodiments, the spacing of the interconnect structures 114 may be reduced for greater wiring design freedom. For example, previous ratios of pad pitch to pad width (or diameter) have been kept larger, on the order of 2:1 and 3:1 for some larger pads, due to increased interconnect 114 dishing and dielectric 102 erosion with closer ratios. In the embodiments, the pitch of the interconnect 114 pads may be reduced to less than 2. In this embodiment, a distance between two adjacent interconnect pads 114 is less than a width of the interconnect 114 pad when using the disclosed techniques and devices. For one example, a set of adjacent 20 micron interconnect 114 pads may now have a pitch of about 25 microns when applying the disclosed techniques and devices.
Referring to
In an embodiment, as shown at
In another example (as also shown at
In a further embodiment, referring to
As shown at
Referring to
At block C, portions 502 of the dielectric 102 can be selectively removed as desired (e.g., about 30-100 nm), using a selective wet etch for example, leaving the conductive structure 114 protruding from the insulating layer 102. At block D, the embedded layer 304 is deposited over the surface of the insulating layer 102, including the interconnect structures 114. The embedded layer 304 may contact at least a portion of the metal sidewall 504 of the interconnect structures 114 and/or the barrier layer 106. The embedded layer 304 can be planarized (CMP, for example) to the point of revealing the highest point(s) of the interconnect structures 114, while retaining a flat surface with minimal surface topography variance, as discussed above and shown at block E. The passivation layer 606, which may comprise a preferred bonding layer, a protective layer, and/or a functional layer for the die 302 comprises the planarized embedded layer 304 remaining on the insulating layer 102.
In general, when directly bonding dies or wafers having bonding surfaces containing a combination of a dielectric layer 102 and one or more metal features, such as the embedded conductive interconnect structures 114, the dielectric surfaces 102 bond first and the metal 110 of the features 114 expands afterwards, as the metal 110 is heated during annealing. The expansion of the metal 110 can cause the metal 110 from both dies 302 to join into a unified conductive structure 310 (metal-to-metal bond). While both the insulating layer 102 and the metal 110 are heated during annealing, the coefficient of thermal expansion (CTE) of the metal 110 relative to the CTE of the insulating layer 102 generally dictates that the metal 110 expands much more than the insulating layer 102 at a particular temperature (e.g., ˜300 C). For instance, the CTE of copper is 16.7, while the CTE of fused silica is 0.55, and the CTE of silicon (e.g., base 604) is 2.56. In some cases, the greater expansion of the metal 110 relative to the insulating layer 102 can be problematic for direct bonding stacked dies 302.
Some embedded conductive interconnect structures 114 may extend partially into the insulating layer 102 below the prepared bonding surface 112. For instance, some patterned metal features may be about 0.5-3 microns thick. Other conductive interconnect structures 114 may comprise thicker (e.g., deeper) structures, including metal through silicon vias (TSVs) or the like, that may extend partly or fully through the insulating layer 102 and include a larger volume of metal 110. For instance, a TSV may extend about 100 microns or more, depending on the thickness of the substrate. In some applications, it may be desirable to form large diameter metal structures 114, for instance having a width or diameter of 10 microns to over 100 microns, which would also include a larger volume of metal 110. As mentioned above, the metal 110 of these structures 114 expands when heated. In some cases, the metal 110 expansion can cause undesirable localized stress, including potential delamination of the bonding surfaces at the location of the structures 114. In a worst-case, the stress of the expanded metal 110 may separate the bonded dielectric surfaces 112 of the stacked dies 302.
Also, it can be relatively expensive to form fully-filled large cavities 104 with metal or other conductive material 110. For example, filling TSV arrays having a diameter of 5 microns and a depth of 100 microns by electroplating methods may require 10 to 20 minutes of metal plating time. However, filling TSV arrays having a diameter of 20 microns and a similar depth may require plating times between 120 to 400 minutes or even longer. The longer plating times reduces the throughput of the plating tool for filling larger cavities 104. Similarly, it can cost more to planarize the larger metal filled cavities 104 to remove unwanted metal on the bonding surface. In practice, the larger the metal filled cavity 104 the greater the mismatch stress due to differences in the coefficient of thermal expansion (CTE) between the coated metal 110 and the insulating layer 102. In the case of large metal TSVs, the larger the diameter of the via, the larger the keep out zone for devices in the device portion of the substrate.
Referring to
For example, in various embodiments, an opening 702 may be intentionally formed in a conductive interconnect structure 114. The opening 702 may extend a predetermined depth below the surface of the conductive interconnect 114. For a given metal coating time, the volume of opening of 702A can be larger than that of 702B and the volume of opening 702B can be larger than 702C. The volume of the opening 702 may be selected based on the material 110 of the conductive interconnect 114, its thickness or volume of material 110, and its anticipated expansion during annealing. In various embodiments the opening 702 may include any recessed portion, gap, cavity, hollow, or the like in the conductive interconnect structure 114 that provides room for the material 110 of the interconnect structure 114 to expand into. A suitably sized opening 702 can reduce or eliminate the stress of the expanding material 110 on the bond joint 306 of the stacked dies 302 or wafers, since the metal 110 can expand into the opening 702. The width of the opening 702 may range for example between less than 100 nm to over 20 microns. With an opening 702 of predetermined size, it can still allow the material 110 of respective interconnect structures 114 to reliably join and form continuous conductive interconnects 310 between the stacked dies 302 or wafers.
In various embodiments, the opening 702 may be intentionally formed to have a desired preselected volume (e.g., to accommodate excessive stresses resulting from the mismatch in the thermal expansion of the coated metal 110 in the cavity 104 and the surrounding insulator 102 materials). In other embodiments, the opening 702 may be allowed to form as part of processing the bonding surface 306 of the die 302 or wafer. In such cases, the volume of the opening 702 may be predictable based on the processes and materials involved.
For example, in some embodiments, the opening 702 may be formed intentionally while the conductive interconnect structure 114 is formed. For instance, as shown at
As shown at
The bonding surface 306 of the die 302 or wafer or substrate of interest is planarized (using chemical-mechanical polishing (CMP), or the like) to prepare the dielectric surface 102 and conductive interconnect structures 114 for bonding. This includes removing the unwanted layer of plating 110 and other conducting barrier layer 106 from the damascene process from the dielectric bonding surface 306, as illustrated in
The bonding surface 306 of the die 302 or wafer may be ready for bonding to another like die 302 or wafer, or to some other prepared substrate 704, to form a bonded device 312. In various embodiments, the substrate 704 may comprise the same or a dissimilar or a different material than the die 302. For instance, the substrate 704 may comprise a dielectric, a glass, a semiconductor, or other material. After the bonding operation, in which the planar portion or portions of the conductive interconnect structures 114 (114A, 114B and 114C) on the bonding surface 306 are directly bonded to the prepared surface of the opposing substrate 704, the remaining openings 702′ are occluded within the conductive interconnect structures 114, as depicted in
In an alternate process, as shown at
In various embodiments, the protective layer 802 may comprise a dielectric material, such as SiO2, SiC, SiN, SiC/SiO2, SiN/SiO2, SiN/polysilicon, inorganic dielectric/organic dielectric or the like. For example, the protective layer 802 may be comprised of the same or a different dielectric as the insulating layer 102 of the die 302 or wafer surface. In other embodiments, the protective layer 802 may be comprised of a conductive material, such as tungsten, an alloy of tungsten, a nickel alloy, tantalum or titanium and the various alloys, for example TaN/Ta or Ta/TaN, Ti/TiN, cobalt, CoP, NiP, CoWP, CoP/NiP or the like. Still further, the protective layer 802 may include a low CTE material, a silicon containing material, such as doped or undoped polysilicon (which may form a silicide), or other suitable material. Still further, multiple coats or layers of insulating and/or conductive materials may be used.
The protective layer may be deposited by PVD methods or from electrolytic or by electroless plating baths or other techniques. Alternatively, the protective layer 802 may include multiple coats or layers of insulating and/or conductive materials. In some applications, the protective layer 802 may comprise a conformal coating of one or more materials. One of the benefits of the protective layer 802 is to suppress the surface mobility of metal atoms at the surface of the conductive layer 110, adjacent to the protective layer 802 within the opening 702, improving the reliability of the bonded interconnect 114. Thus the protective layer 802 can act as a bonding surface for a portion of the conductive interconnect 114.
In an embodiment, the thickness of the protective layer 802 is less than the thickness of the conductive layer 110 within the respective cavities 104 bounded with the protective layer 802 and the barrier layer 106. In other embodiments, the protective layer 802 may be thicker than the conductive layer 110. After planarization of the bonding surface 306, including removing unwanted materials from the bonding surface 306, the remaining openings 702′ (702A′, 702B′ and 702C′) in the surfaces of the interconnect structures 114 retain the protective layer 802 on the interior surfaces of the remaining openings 702′, which can have predetermined volumes.
The die 302 or wafer may be prepared for bonding to another like die 302 or wafer (as shown at
In various cases, as shown at
In other words, in an example embodiment, as shown at
In some applications, with wafers or dies 302 comprising TSVs or through electrodes, after the bonding operation as shown in
Further embodiments are shown at
Additionally, as shown at
In an implementation, as shown at
Referring to
For example, as shown at
As shown at
As shown at
In various other embodiments, other techniques may be used to vary the surface of a conductive interconnect structure 114, to mitigate the effects of metal expansion. For instance, in some examples, the surface of a conductive interconnect structure 114 may be selectively etched (via acid etching, plasma oxidation, etc.) to provide a desired opening 702 depth. In a further embodiment, a conductive interconnect structure 114 may be selected, formed, or processed to have an uneven top surface. For example, the top surface of the conductive interconnect structure may be rounded, domed, convex, concave, irregular, or otherwise non-flat.
Example Processes
The order in which the processes are described is not intended to be construed as limiting, and any number of the described process blocks in the processes can be combined in any order to implement the processes, or alternate processes. Additionally, individual blocks may be deleted from the processes without departing from the spirit and scope of the subject matter described herein. Furthermore, the processes can be implemented in any suitable hardware, software, firmware, or a combination thereof, without departing from the scope of the subject matter described herein. In alternate implementations, other techniques may be included in the processes in various combinations and remain within the scope of the disclosure.
In an implementation, at block 1302, the process 1300 includes forming one or more first embedded conductive interconnect structures (such as conductive interconnect structures 114, for example) in a first substrate (such as die 302, for example).
At block 1304, the process includes planarizing a first surface of the first substrate to form a planarized topography comprising the first surface and a surface of the one or more first embedded conductive interconnect structures. At block 1306, the process includes depositing a first embedded layer (such as embedded layer 304, for example) over the first surface of the first substrate and the one or more first embedded conductive interconnect structures.
At block 1308, the process includes planarizing the first embedded layer until revealing the surface of the one or more first embedded conductive interconnect structures and forming a bonding surface of the first embedded layer, a first recessed portion of the one or more first embedded conductive interconnect structures at least partially filled with a portion of the first embedded layer, the portion of the first embedded layer covering a surface of the first recessed portion of the one or more first embedded conductive interconnect structures.
In an implementation, the process includes suppressing a surface mobility of atoms of a material of the first recessed portion by covering the surface of the first recessed portion with the first embedded layer.
In an implementation, the process includes forming one or more second embedded conductive interconnect structures in a second substrate; planarizing a first surface of the second substrate to form a planarized topography comprising the first surface of the second substrate and a surface of the one or more second embedded conductive interconnect structures; bonding the first surface of the second substrate to the bonding surface of the first substrate via direct bonding without adhesive; and directly bonding the one or more second embedded conductive interconnect structures to the one or more first embedded conductive interconnect structures.
In a further implementation, the process includes depositing a second embedded layer over the first surface of the second substrate and the one or more second embedded conductive interconnect structures; and planarizing the second embedded layer until revealing the surface of the one or more second embedded conductive interconnect structures and forming a second bonding surface of the second bonding layer, a first recessed portion of the one or more second embedded conductive interconnect structures at least partially filled with a portion of the second embedded layer, the portion of the second embedded layer covering a surface of the first recessed portion of the one or more second embedded conductive interconnect structures.
In an implementation, the process further includes bonding the portion of the second embedded layer to the portion of the first embedded layer via direct bonding without adhesive.
As an alternate implementation, the process includes forming one or more first embedded conductive interconnect structures in a first substrate; planarizing a first surface of the first substrate to form a planarized topography comprising the first surface and a surface of the one or more first embedded conductive interconnect structures; selectively removing a portion of the first surface such that the one or more first embedded conductive interconnect structures protrudes above the first surface of the first substrate; depositing a first embedded layer over the first surface of the first substrate and the one or more first embedded conductive interconnect structures, the first embedded layer contacting a portion of a side wall of the one or more first embedded conductive interconnect structures; and planarizing the first embedded layer until revealing the surface of the one or more first embedded conductive interconnect structures and forming a bonding surface of the first embedded layer and the surface of the one or more first embedded conductive interconnect structures.
In an implementation, at block 1402, the process 1400 includes forming one or more first cavities in a first surface of a first substrate.
At block 1404, the process includes forming one or more first embedded conductive interconnect structures within the one or more first cavities, including forming one or more of the first embedded conductive interconnect structures to have a first recessed portion in an exposed surface of the one or more first embedded conductive interconnect structures.
In an implementation, the process includes forming the one or more first embedded conductive interconnect structures and the first recessed portion by partially filling the one or more first cavities using a damascene process. In an embodiment, the one or more first embedded conductive interconnect structures comprise a conformal metal coating over one or more interior surfaces of the one or more first cavities.
In an implementation, the process includes depositing a protective layer over the first recessed portion of the one or more first embedded conductive interconnect structures. In a further implementation, the process includes depositing one or more additional layers over the protective layer, at least one of the one or more additional layers including a dielectric material.
At block 1406, the process includes planarizing the first surface of the first substrate to form a first planarized bonding surface comprising the first surface and the exposed surface of the one or more first embedded conductive interconnect structures
In an implementation, the process includes forming one or more second embedded conductive interconnect structures in a second substrate, including forming one or more of the second embedded conductive interconnect structures to have a second recessed portion in an exposed surface of the one or more second embedded conductive interconnect structures; planarizing a first surface of the second substrate to form a second planarized bonding surface comprising the first surface of the second substrate and the exposed surface of the one or more second embedded conductive interconnect structures; bonding the second planarized bonding surface of the second substrate to the first planarized bonding surface of the first substrate via direct bonding without adhesive; and directly bonding the one or more second embedded conductive interconnect structures to the one or more first embedded conductive interconnect structures.
In a further implementation, the process includes depositing a protective layer over the second recessed portion of the one or more second embedded conductive interconnect structures. In an example the process includes suppressing a surface mobility of atoms of a material of the second recessed portion by covering the surface of the second recessed portion with the protective layer. In another example the process includes controlling a direction of expansion of the material of the one or more second embedded conductive interconnect structures by covering the surface of the second recessed portion with the protective layer.
As an alternate implementation, the process includes forming one or more first cavities in a first surface of a first substrate; forming one or more first embedded conductive interconnect structures with one or more openings within the one or more first cavities; and forming a planar surface comprising one or more of the first embedded conductive interconnect structures having one or more openings.
As another alternate implementation, the process includes forming one or more first cavities in a first surface of a first substrate; forming one or more first embedded conductive interconnect structures with one or more openings within the one or more first cavities; forming a planar surface comprising one or more of the first embedded conductive interconnect structures having one or more openings; and directly bonding the planar surface of the interconnect structures with openings to the prepared surface of a second substrate.
In various embodiments, some process steps may be modified or eliminated, in comparison to the process steps described herein.
The techniques, components, and devices described herein are not limited to the illustrations of
Although the implementations of the disclosure have been described in language specific to structural features and/or methodological acts, it is to be understood that the implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing example devices and techniques.
This application claims the benefit under 35 U.S.C. § 119(e)(1) of U.S. Provisional Application No. 62/748,653, filed Oct. 22, 2018, and of U.S. Provisional Application No. 62/902,207, filed Sep. 18, 2019, which are both hereby incorporated by reference in their entirety.
Number | Name | Date | Kind |
---|---|---|---|
4612083 | Yasumoto et al. | Sep 1986 | A |
4818728 | Rai et al. | Apr 1989 | A |
4904328 | Beecher et al. | Feb 1990 | A |
4939568 | Kato et al. | Jul 1990 | A |
4998665 | Hayashi | Mar 1991 | A |
5087585 | Hayashi | Feb 1992 | A |
5236118 | Bower et al. | Aug 1993 | A |
5322593 | Hasegawa et al. | Jun 1994 | A |
5413952 | Pages et al. | May 1995 | A |
5419806 | Huebner | May 1995 | A |
5442235 | Parrillo et al. | Aug 1995 | A |
5489804 | Pasch | Feb 1996 | A |
5501003 | Bernstein | Mar 1996 | A |
5503704 | Bower et al. | Apr 1996 | A |
5504376 | Sugahara et al. | Apr 1996 | A |
5516727 | Broom | May 1996 | A |
5563084 | Ramm et al. | Oct 1996 | A |
5610431 | Martin | Mar 1997 | A |
5696406 | Ueno | Dec 1997 | A |
5734199 | Kawakita et al. | Mar 1998 | A |
5753536 | Sugiyama et al. | May 1998 | A |
5771555 | Eda et al. | Jun 1998 | A |
5821692 | Rogers et al. | Oct 1998 | A |
5866942 | Suzuki et al. | Feb 1999 | A |
5985739 | Plettner et al. | Nov 1999 | A |
5998808 | Matsushita | Dec 1999 | A |
6008126 | Leedy | Dec 1999 | A |
6054363 | Sakaguchi et al. | Apr 2000 | A |
6063968 | Hubner et al. | May 2000 | A |
6071761 | Jacobs | Jun 2000 | A |
6080640 | Gardner et al. | Jun 2000 | A |
6097096 | Gardner et al. | Aug 2000 | A |
6123825 | Uzoh et al. | Sep 2000 | A |
6147000 | You et al. | Nov 2000 | A |
6183592 | Sylvester | Feb 2001 | B1 |
6218203 | Khoury et al. | Apr 2001 | B1 |
6232150 | Lin et al. | May 2001 | B1 |
6258625 | Brofman et al. | Jul 2001 | B1 |
6259160 | Lopatin et al. | Jul 2001 | B1 |
6265775 | Seyyedy | Jul 2001 | B1 |
6297072 | Tilmans et al. | Oct 2001 | B1 |
6316786 | Mueller et al. | Nov 2001 | B1 |
6322600 | Brewer et al. | Nov 2001 | B1 |
6333120 | DeHaven et al. | Dec 2001 | B1 |
6333206 | Ito et al. | Dec 2001 | B1 |
6348709 | Graettinger et al. | Feb 2002 | B1 |
6359235 | Hayashi | Mar 2002 | B1 |
6374770 | Lee | Apr 2002 | B1 |
6409904 | Uzoh et al. | Jun 2002 | B1 |
6423640 | Lee et al. | Jul 2002 | B1 |
6465892 | Suga | Oct 2002 | B1 |
6515343 | Shroff et al. | Feb 2003 | B1 |
6528894 | Akram et al. | Mar 2003 | B1 |
6552436 | Burnette et al. | Apr 2003 | B2 |
6555917 | Heo | Apr 2003 | B1 |
6579744 | Jiang | Jun 2003 | B1 |
6583515 | James et al. | Jun 2003 | B1 |
6589813 | Park | Jul 2003 | B1 |
6593645 | Shih et al. | Jul 2003 | B2 |
6600224 | Farquhar et al. | Jul 2003 | B1 |
6624003 | Rice | Sep 2003 | B1 |
6627814 | Stark | Sep 2003 | B1 |
6632377 | Brusic et al. | Oct 2003 | B1 |
6642081 | Patti | Nov 2003 | B1 |
6656826 | Ishimaru | Dec 2003 | B2 |
6660564 | Brady | Dec 2003 | B2 |
6667225 | Hau-Riege et al. | Dec 2003 | B2 |
6720212 | Robl et al. | Apr 2004 | B2 |
6759738 | Fallon et al. | Jul 2004 | B1 |
6828686 | Park | Dec 2004 | B2 |
6837979 | Uzoh et al. | Jan 2005 | B2 |
6847527 | Sylvester et al. | Jan 2005 | B2 |
6864585 | Enquist | Mar 2005 | B2 |
6867073 | Enquist | Mar 2005 | B1 |
6887769 | Kellar et al. | May 2005 | B2 |
6902987 | Tong et al. | Jun 2005 | B1 |
6908027 | Tolchinsky et al. | Jun 2005 | B2 |
6909194 | Farnworth et al. | Jun 2005 | B2 |
6960492 | Miyamoto | Nov 2005 | B1 |
6962835 | Tong et al. | Nov 2005 | B2 |
6974769 | Basol et al. | Dec 2005 | B2 |
7037755 | Enquist | May 2006 | B2 |
7045453 | Canaperi et al. | May 2006 | B2 |
7078811 | Suga | Jul 2006 | B2 |
7105980 | Abbott et al. | Sep 2006 | B2 |
7109063 | Jiang | Sep 2006 | B2 |
7109092 | Tong | Sep 2006 | B2 |
7126212 | Enquist et al. | Oct 2006 | B2 |
7193239 | Leedy | Mar 2007 | B2 |
7193423 | Dalton et al. | Mar 2007 | B1 |
7247948 | Hedler et al. | Jul 2007 | B2 |
7335572 | Tong et al. | Feb 2008 | B2 |
7354798 | Pogge et al. | Apr 2008 | B2 |
7385283 | Wu | Jun 2008 | B2 |
7387944 | Tong et al. | Jun 2008 | B2 |
7485968 | Enquist et al. | Feb 2009 | B2 |
7553744 | Tong et al. | Jun 2009 | B2 |
7750488 | Patti et al. | Jul 2010 | B2 |
7803693 | Trezza | Sep 2010 | B2 |
7807549 | Tong et al. | Oct 2010 | B2 |
7998335 | Feeney et al. | Aug 2011 | B2 |
8183127 | Patti et al. | May 2012 | B2 |
8241961 | Kim et al. | Aug 2012 | B2 |
8314007 | Vaufredaz | Nov 2012 | B2 |
8349635 | Gan et al. | Jan 2013 | B1 |
8357931 | Schieck et al. | Jan 2013 | B2 |
8377798 | Peng et al. | Feb 2013 | B2 |
8435421 | Keleher et al. | May 2013 | B2 |
8441131 | Ryan | May 2013 | B2 |
8476146 | Chen et al. | Jul 2013 | B2 |
8476165 | Trickett et al. | Jul 2013 | B2 |
8482132 | Yang et al. | Jul 2013 | B2 |
8501537 | Sadaka et al. | Aug 2013 | B2 |
8524533 | Tong et al. | Sep 2013 | B2 |
8620164 | Heck et al. | Dec 2013 | B2 |
8647987 | Yang et al. | Feb 2014 | B2 |
8697493 | Sadaka | Apr 2014 | B2 |
8716105 | Sadaka et al. | May 2014 | B2 |
8802538 | Liu | Aug 2014 | B1 |
8809123 | Liu | Aug 2014 | B2 |
8841002 | Tong | Sep 2014 | B2 |
8916448 | Cheng et al. | Dec 2014 | B2 |
8988299 | Kam et al. | Mar 2015 | B2 |
9040385 | Chen et al. | May 2015 | B2 |
9064937 | Edelstein et al. | Jun 2015 | B2 |
9082627 | Tong et al. | Jul 2015 | B2 |
9093350 | Endo et al. | Jul 2015 | B2 |
9142517 | Liu | Sep 2015 | B2 |
9171756 | Enquist et al. | Oct 2015 | B2 |
9184125 | Enquist et al. | Nov 2015 | B2 |
9224704 | Landru | Dec 2015 | B2 |
9230941 | Chen et al. | Jan 2016 | B2 |
9257399 | Kuang et al. | Feb 2016 | B2 |
9299736 | Chen et al. | Mar 2016 | B2 |
9312229 | Chen et al. | Apr 2016 | B2 |
9331032 | Liu et al. | May 2016 | B2 |
9331149 | Tong et al. | May 2016 | B2 |
9337235 | Chen et al. | May 2016 | B2 |
9343330 | Brusic et al. | May 2016 | B2 |
9343369 | Du et al. | May 2016 | B2 |
9368866 | Yu | Jun 2016 | B2 |
9385024 | Tong et al. | Jul 2016 | B2 |
9394161 | Cheng et al. | Jul 2016 | B2 |
9425155 | Liu et al. | Aug 2016 | B2 |
9431368 | Enquist et al. | Aug 2016 | B2 |
9437572 | Chen et al. | Sep 2016 | B2 |
9443796 | Chou et al. | Sep 2016 | B2 |
9461007 | Chun et al. | Oct 2016 | B2 |
9496239 | Edelstein et al. | Nov 2016 | B1 |
9536848 | England et al. | Jan 2017 | B2 |
9559075 | Baloglu et al. | Jan 2017 | B1 |
9559081 | Lai et al. | Jan 2017 | B1 |
9620481 | Edelstein et al. | Apr 2017 | B2 |
9656852 | Cheng | May 2017 | B2 |
9723716 | Meinhold | Aug 2017 | B2 |
9728521 | Tsai et al. | Aug 2017 | B2 |
9741620 | Uzoh et al. | Aug 2017 | B2 |
9799587 | Fujii et al. | Oct 2017 | B2 |
9852988 | Enquist et al. | Dec 2017 | B2 |
9859254 | Yu et al. | Jan 2018 | B1 |
9865581 | Jang et al. | Jan 2018 | B2 |
9881882 | Hsu et al. | Jan 2018 | B2 |
9893004 | Yazdani | Feb 2018 | B2 |
9899442 | Katkar | Feb 2018 | B2 |
9929050 | Lin | Mar 2018 | B2 |
9941241 | Edelstein et al. | Apr 2018 | B2 |
9941243 | Kim et al. | Apr 2018 | B2 |
9953941 | Enquist | Apr 2018 | B2 |
9960129 | Liu | May 2018 | B2 |
9960142 | Chen et al. | May 2018 | B2 |
10002844 | Wang et al. | Jun 2018 | B1 |
10026605 | Doub et al. | Jul 2018 | B2 |
10075657 | Fahim et al. | Sep 2018 | B2 |
10103122 | Liu et al. | Oct 2018 | B2 |
10147641 | Enquist et al. | Dec 2018 | B2 |
10204893 | Uzoh et al. | Feb 2019 | B2 |
10211166 | Matsuo | Feb 2019 | B2 |
10269708 | Enquist et al. | Apr 2019 | B2 |
10269756 | Uzoh | Apr 2019 | B2 |
10276619 | Kao et al. | Apr 2019 | B2 |
10276909 | Huang et al. | Apr 2019 | B2 |
10312275 | Hynecek | Jun 2019 | B2 |
10431614 | Gambino et al. | Oct 2019 | B2 |
10446456 | Shen et al. | Oct 2019 | B2 |
10446487 | Huang et al. | Oct 2019 | B2 |
10446532 | Uzoh et al. | Oct 2019 | B2 |
10840205 | Fountain, Jr. et al. | Nov 2020 | B2 |
20020000328 | Motomura et al. | Jan 2002 | A1 |
20020003307 | Suga | Jan 2002 | A1 |
20020025665 | Juengling | Feb 2002 | A1 |
20020074670 | Suga | Jun 2002 | A1 |
20020094661 | Enquist et al. | Jul 2002 | A1 |
20020113241 | Kubota et al. | Aug 2002 | A1 |
20030092220 | Akram | May 2003 | A1 |
20030109083 | Ahmad | Jun 2003 | A1 |
20030129796 | Bruchhaus et al. | Jul 2003 | A1 |
20030157748 | Kim et al. | Aug 2003 | A1 |
20040084414 | Sakai et al. | May 2004 | A1 |
20040157407 | Tong et al. | Aug 2004 | A1 |
20040217483 | Hedler et al. | Nov 2004 | A1 |
20040262772 | Ramanathan et al. | Dec 2004 | A1 |
20050104224 | Huang et al. | May 2005 | A1 |
20050181542 | Enquist | Aug 2005 | A1 |
20060024950 | Choi et al. | Feb 2006 | A1 |
20060057945 | Hsu et al. | Mar 2006 | A1 |
20070045780 | Akram | Mar 2007 | A1 |
20070096294 | Ikeda et al. | May 2007 | A1 |
20070111386 | Kim et al. | May 2007 | A1 |
20070145367 | Chen | Jun 2007 | A1 |
20070212870 | Yang et al. | Sep 2007 | A1 |
20070222048 | Huang | Sep 2007 | A1 |
20070295456 | Gudeman et al. | Dec 2007 | A1 |
20080073795 | Kohl et al. | Mar 2008 | A1 |
20080122092 | Hong | May 2008 | A1 |
20090140404 | Chen | Jun 2009 | A1 |
20090197408 | Lehr et al. | Aug 2009 | A1 |
20090200668 | Yang et al. | Aug 2009 | A1 |
20100164066 | Di Franco | Jul 2010 | A1 |
20100261332 | Kim | Oct 2010 | A1 |
20110074040 | Frank et al. | Mar 2011 | A1 |
20110290552 | Palmateer et al. | Dec 2011 | A1 |
20120013013 | Sadaka et al. | Jan 2012 | A1 |
20120068355 | Aoki | Mar 2012 | A1 |
20120211894 | Aoyagi | Aug 2012 | A1 |
20120212384 | Kam et al. | Aug 2012 | A1 |
20120252189 | Sadaka et al. | Oct 2012 | A1 |
20120319280 | Suganuma et al. | Dec 2012 | A1 |
20130020704 | Sadaka | Jan 2013 | A1 |
20130075900 | Shim et al. | Mar 2013 | A1 |
20130221527 | Yang et al. | Aug 2013 | A1 |
20130256913 | Black et al. | Oct 2013 | A1 |
20130307165 | Wang et al. | Nov 2013 | A1 |
20130320556 | Liu et al. | Dec 2013 | A1 |
20130328186 | Uzoh et al. | Dec 2013 | A1 |
20140131869 | Pendse | May 2014 | A1 |
20140175655 | Chen et al. | Jun 2014 | A1 |
20140191418 | Cheng et al. | Jul 2014 | A1 |
20140225795 | Yu | Aug 2014 | A1 |
20140252635 | Tran et al. | Sep 2014 | A1 |
20140264948 | Chou et al. | Sep 2014 | A1 |
20140332980 | Sanders et al. | Nov 2014 | A1 |
20150064498 | Tong | Mar 2015 | A1 |
20150108644 | Kuang et al. | Apr 2015 | A1 |
20150155263 | Farooq et al. | Jun 2015 | A1 |
20150206823 | Lin et al. | Jul 2015 | A1 |
20150214191 | Lee et al. | Jul 2015 | A1 |
20150228621 | Kumar et al. | Aug 2015 | A1 |
20160049384 | Lu et al. | Feb 2016 | A1 |
20160086923 | Best | Mar 2016 | A1 |
20160343682 | Kawasaki | Nov 2016 | A1 |
20170053897 | Lai et al. | Feb 2017 | A1 |
20170062366 | Enquist | Mar 2017 | A1 |
20170162535 | Rinne | Jun 2017 | A1 |
20170179029 | Enquist et al. | Jun 2017 | A1 |
20170194271 | Hsu et al. | Jul 2017 | A1 |
20170358551 | Liu et al. | Dec 2017 | A1 |
20180175012 | Wu et al. | Jun 2018 | A1 |
20180182639 | Uzoh et al. | Jun 2018 | A1 |
20180182665 | Uzoh et al. | Jun 2018 | A1 |
20180182666 | Uzoh et al. | Jun 2018 | A1 |
20180190580 | Haba et al. | Jul 2018 | A1 |
20180190583 | DeLaCruz et al. | Jul 2018 | A1 |
20180204798 | Enquist et al. | Jul 2018 | A1 |
20180219038 | Gambino et al. | Aug 2018 | A1 |
20180226371 | Enquist | Aug 2018 | A1 |
20180226375 | Enquist et al. | Aug 2018 | A1 |
20180240860 | Yang et al. | Aug 2018 | A1 |
20180273377 | Katkar et al. | Sep 2018 | A1 |
20180286805 | Huang et al. | Oct 2018 | A1 |
20180323177 | Yu et al. | Nov 2018 | A1 |
20180323227 | Zhang et al. | Nov 2018 | A1 |
20180331066 | Uzoh et al. | Nov 2018 | A1 |
20190057756 | Kim et al. | Feb 2019 | A1 |
20190088535 | Yan et al. | Mar 2019 | A1 |
20190096741 | Uzoh et al. | Mar 2019 | A1 |
20190096842 | Fountain, Jr. et al. | Mar 2019 | A1 |
20190109042 | Katkar et al. | Apr 2019 | A1 |
20190115277 | Yu et al. | Apr 2019 | A1 |
20190131277 | Yang et al. | May 2019 | A1 |
20190157334 | Wei et al. | May 2019 | A1 |
20190189603 | Wang et al. | Jun 2019 | A1 |
20190198407 | Huang et al. | Jun 2019 | A1 |
20190198409 | Katkar et al. | Jun 2019 | A1 |
20190265411 | Huang et al. | Aug 2019 | A1 |
20190319007 | Uzoh | Oct 2019 | A1 |
20190333550 | Fisch | Oct 2019 | A1 |
20190348336 | Katkar et al. | Nov 2019 | A1 |
20190385966 | Gao et al. | Dec 2019 | A1 |
20200013637 | Haba | Jan 2020 | A1 |
20200013765 | Fountain, Jr. et al. | Jan 2020 | A1 |
20200035630 | Kameshima | Jan 2020 | A1 |
20200075534 | Gao et al. | Mar 2020 | A1 |
20200194396 | Uzoh | Jun 2020 | A1 |
20200227367 | Haba et al. | Jul 2020 | A1 |
20200294908 | Haba et al. | Sep 2020 | A1 |
20200328162 | Haba et al. | Oct 2020 | A1 |
20200328164 | DeLaCruz et al. | Oct 2020 | A1 |
20200328165 | DeLaCruz et al. | Oct 2020 | A1 |
20200365575 | Uzoh et al. | Nov 2020 | A1 |
20200371154 | DeLaCruz et al. | Nov 2020 | A1 |
20200395321 | Katkar et al. | Dec 2020 | A1 |
20210098412 | Haba et al. | Apr 2021 | A1 |
Number | Date | Country |
---|---|---|
105140144 | Dec 2015 | CN |
106653720 | May 2017 | CN |
106920795 | Jul 2017 | CN |
107731668 | Feb 2018 | CN |
107993927 | May 2018 | CN |
107993928 | May 2018 | CN |
109155301 | Jan 2019 | CN |
109417073 | Mar 2019 | CN |
109417075 | Mar 2019 | CN |
109417077 | Mar 2019 | CN |
109643643 | Apr 2019 | CN |
109844915 | Jun 2019 | CN |
0 465 227 | Jan 1992 | EP |
2 863 420 | Apr 2015 | EP |
61-030059 | Feb 1986 | JP |
01-168040 | Jul 1989 | JP |
4-259249 | Sep 1992 | JP |
05-029183 | Feb 1993 | JP |
5-198739 | Aug 1993 | JP |
6-13456 | Jan 1994 | JP |
6-260594 | Sep 1994 | JP |
H07-66093 | Mar 1995 | JP |
H7-249749 | Sep 1995 | JP |
7-283382 | Oct 1995 | JP |
8-78645 | Mar 1996 | JP |
8-125121 | May 1996 | JP |
8-186235 | Jul 1996 | JP |
9-120979 | May 1997 | JP |
10-135404 | May 1998 | JP |
10-223636 | Aug 1998 | JP |
10-242383 | Sep 1998 | JP |
11-186120 | Jul 1999 | JP |
2000-100679 | Apr 2000 | JP |
2000-260934 | Sep 2000 | JP |
2000-299379 | Oct 2000 | JP |
2000-311982 | Nov 2000 | JP |
2001-102479 | Apr 2001 | JP |
2001-326326 | Nov 2001 | JP |
2002-026123 | Jan 2002 | JP |
2002-516033 | May 2002 | JP |
2002-353416 | Dec 2002 | JP |
2002-368159 | Dec 2002 | JP |
2003-023071 | Jan 2003 | JP |
2004-200547 | Jul 2004 | JP |
2005-086089 | Mar 2005 | JP |
2005-093486 | Apr 2005 | JP |
2005-135988 | May 2005 | JP |
2013-33786 | Feb 2013 | JP |
2013-033900 | Feb 2013 | JP |
2018-160519 | Oct 2018 | JP |
2019-129199 | Aug 2019 | JP |
10-2011-0079222 | Jul 2011 | KR |
10-2012-0106366 | Sep 2012 | KR |
10-2015-0097798 | Aug 2015 | KR |
476145 | Feb 2002 | TW |
WO 0161743 | Aug 2001 | WO |
WO 03054954 | Jul 2003 | WO |
2005-043584 | May 2005 | WO |
WO 2006100444 | Sep 2006 | WO |
WO 2012013162 | Feb 2012 | WO |
WO 2016185883 | Nov 2016 | WO |
WO 2017151442 | Sep 2017 | WO |
WO 2017155002 | Sep 2017 | WO |
WO 2019146427 | Aug 2019 | WO |
Entry |
---|
International Search Report and Written Opinion, dated Mar. 25, 2020, for PCT Application No. PCT/US2019/057252, dated Oct. 21, 2019, 12 pages. |
Ker, Ming-Dou et al., “Fully Process-Compatible Layout Design on Bond Pad to Improve Wire Bond Reliability in CMOS ICs,” IEEE Transactions on Components and Packaging Technologies, Jun. 2002, vol. 25, No. 2, pp. 309-316. |
Moriceau, H. et al., “Overview of Recent Direct Wafer Bonding Advances and Applications”, Advances in Natural Sciences—Nanoscience and Nanotechnology, 2010, 12 pages. |
Nakanishi, H. et al., “Studies on SiO2—SiO2 Bonding with Hydrofluoric Acid. Room Temperature and Low Stress Bonding Technique for MEMS,” Tech. Research Lab., 200, Elsevier Science S.A., 8 pages. |
Oberhammer et al., “Sealing of Adhesive Bonded Devices on Wafer Level,” in Sensors and Actuators A, vol. 110, No. 1-3, pp. 407-412, Feb. 29, 2004, see pp. 407-412; and figures 1(a)-1(I), 6 pages. |
Plobi et al., “Wafer Direct Bonding: Tailoring Adhesion Between Brittle Materials,” Materials Science and Engineering Review Journal, 1999, 88 pages. |
Amirfeiz et al., “Formation of silicon structures by plasma-activated wafer bonding,” Journal of the Electrochemical Society, 2000, vol. 147, No. 7, pp. 2693-2698. |
Appeal Decision of Rejection dated Apr. 12, 2016 in Japanese Patent Application No. 2008-526104, in 14 pages. |
Aspar, B. et al., “The smart-cut process: Status and developments,” Proc. Electrochem Soc., 1999, vol. 99-53, pp. 48-59. |
Bower, R. et al., “Low temperature Si3N4 direct bonding,” Appl. Phys. Lett., Jun. 28, 1993, vol. 62, No. 26, pp. 3485-3487. |
Canadian Office Action dated Aug. 1, 2013 in Canadian Patent Application No. 2,618,191, 4 pages. |
Canadian Office Action, dated May 16, 2012 for Canadian Patent Application No. 2,515,375, with international preliminary report, 2 pages. |
Ceramic Microstructures: Control at the Atomic Level, Recent Progress in Surface Activated Bonding, 1998, pp. 385-389. |
“Chemical Mechanical Polishing (CMP) Metrology with Advanced Surface Polisher,” Park Systems, 4 pages. |
Chung et al., “Room temperature GaAseu + Si and InPeu + Si wafer direct bonding by the surface activate bonding method,” Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, Jan. 2, 1997, vol. 121, Issues 1-4, pp. 203-206. |
Chung et al., “Wafer direct bonding of compound semiconductors and silicon at room temperature by the surface activated bonding method,” Applied Surface Science, Jun. 2, 1997, vols. 117-118, pp. 808- 812. |
D'Agostino, R., “Plasma etching of Si and SiO2 in SF6-O2 mixtures,” J. Appl. Phys., Jan. 1981, vol. 52, No. 1, pp. 162-167. |
Decision—Request for Trail Granted, Inter Partes Review, U.S. Pat. No. 7,485,968, Case IPR2013-00381, dated Dec. 18, 2013, in 27 pages. |
Declaration of Richard A. Blanchard in Support of Petition for inter partes review of U.S. Pat. No. 7,485,968, dated Jun. 13, 2013, pp. 1-18. |
Dysard, Jeffrey M. et al., “CMP solutions for the integration of high-k metal gate technologies,” ECS Transactions, 2010, vol. 33, Issue 10, pp. 77-89. |
Fan et al., “Copper water bonding,” Electrochem. Solid-State Lett., U.S.A., The Electrochemical Society, Aug. 6, 1999, vol. 2, No. 10, pp. 534-536. |
Fang, S.J. et al., “Advanced process control in dielectric chemical mechanical polishing (CMP),” Texas Instruments, Silicon Technology Development, 8 pages. |
Farrens et al., “Chemical free room temperature wafer to wafer direct bonding,” J. Electrochem. Soc., The Electrochemical Society, Inc., Nov. 1995, vol. 142, No. 11. pp. 3949-3955. |
Farrens et al., “Chemical free wafer bonding of silicon to glass and sapphire,” Electrochemical Society Proceedings vol. 95-97, 1995, pp. 72-77. |
Final Written Decision, Inter PartesReview, U.S. Pat. No. 7,485,968, Case IPR2013-00381, dated Feb. 27, 2014, in 3 pages. |
Gösele et al., “Semiconductor Wafer Bonding: A flexible approach to materials combinations in microelectronics; micromechanics and optoelectronics,” IEEE, 1997, pp. 23-32. |
Gösele et al., “Silicon layer transfer by wafer bonding,” Proceedings of the Second International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, The Electrochemical Society Proceedings, vol. 93-29 (1993), pp. 395-409. |
Handbook of Thin Film Technology, Maissel and Glang, 1983 Reissue, pp. 12-24. |
Harendt, C. et al., “Vertical polysilicon interconnects by aligned wafer bonding,” Electrochemical Society Proceedings, 1998, vol. 97-36, pp. 501-508. |
Hayashi, Y. et al., “Fabrication of three-dimensional Ic using cumulatively bonded IC (CUBIC) technology,” VSLI Tech. Dog., 1990, pp. 95-96. |
Hizukuri, M. et al., “Dynamic strain and chip damage during ultrasonic flip chip bonding,” Jpn. J. Appl. Phys. 40, 2001, pp. 3044-3048. |
Hosoda et al., “Effect of the surface treatment on the room-temperature bonding of Al to Si and SiO2,” Journal of Materials Science, Jan. 1, 1998, vol. 33, Issue 1, pp. 253-258. |
Hosoda et al., “Room temperature GaAs—Si and InP—Si wafer direct bonding by the surface activated bonding method,” Nuclear Inst. and Methods in Physics Research B, 1997, vol. 121, Nos. 1-4, pp. 203-206. |
Howlader et al., “A novel method for bonding of ionic wafers,” Electronics Components and Technology Conference, 2006, IEEE, pp. 7. |
Howlader et al., “Bonding of p-Si/n-InP wafers through surface activated bonding method at room temperature,” Indium Phosphide and Related Materials, 2001, IEEE International Conference On, pp. 272-275. |
Howlader et al., “Characterization of the bonding strength and interface current of p-Si/ n-InP wafers bonded by surface activated bonding method at room temperature,” Journal of Applied Physics, Mar. 1, 2002, vol. 91, No. 5, pp. 3062-3066. |
Howlader et al., “Investigation of the bonding strength and interface current of p-SionGaAs wafers bonded by surface activated bonding at room temperature,” J. Vac. Sci. Technol. B 19, Nov./Dec. 2001, pp. 2114-2118. |
“Hybrid Bonding—Patent Landscape Analysis,” from Technologies to IP Business Intelligence, KnowMade Patent & Technology Intelligence, www.kmowmade.com, Nov. 2019, 81 pages. |
Hymes, S. et al., “Determination of the planarization distance for copper CMP process,” 6 pages. |
Iida, A. et al., “The study of initial mechanism for Al—Au solid phase diffusion flip-chip bonding,” Jpn. J. Appl. Phys. 40, 1997, pp. 3044-3661. |
International Search Report and Written Opinion dated Apr. 22, 2019 in International Application No. PCT/US2018/064982, 13 pages. |
International Search Report and Written Opinion dated Mar. 7, 2019, in International Application No. PCT/US2018/060044, 14 pages. |
International Search Report and Written Opinion, dated Jan. 10, 2019, for PCT Application No. PCT/US2018/051537, 3 pages. |
International Search Report and Written Opinion dated Oct. 8, 2019, in International Application No. PCT/US2019/037072, 13 pages. |
International Search Report and Written Opinion dated Dec. 6, 2019, in International Application No. PCT/US2019/047513, 12 pages. |
Itoh et al., “Characteristics of fritting contacts utilized for micromachined wafer probe cards,” 2000 American Institute of Physics, AIP Review of Scientific Instruments, vol. 71, 2000, pp. 2224. |
Itoh et al., “Characteristics of low force contact process for MEMS probe cards,” Sensors and Actuators A: Physical, Apr. 1, 2002, vols. 97-98, pp. 462-467. |
Itoh et al., “Development of MEMS IC probe card utilizing fritting contact,” Initiatives of Precision Engineering at the Beginning of a Millennium: 10th International Conference on Precision Engineering (ICPE) Jul. 18-20, 2001, Yokohama, Japan, 2002, Book Part 1, pp. 314-318. |
Itoh et al., “Room temperature vacuum sealing using surface activated bonding method,” The 12th International Conference on Solid State Sensors, Actuators and Microsystems, Boston, Jun. 8-12, 2003, 2003 IEEE, pp. 1828-1831. |
Juang, Jing-Ye et al., “Copper-to-copper direct bonding on highly (111)-oriented nanotwinned copper in no-vacuum ambient,” Scientific Reports, Sep. 17, 2018, vol. 8, 11 pages. |
Kim et al., “Low temperature direct Cu—Cu bonding with low energy ion activation method,” Electronic Materials and Packaging, 2001, IEEE, pp. 193-195. |
Kim et al., “Room temperature Cu—Cu direct bonding using surface activated bonding method,” J. Vac. Sci. Technol., 2003 American Vacuum Society, Mar./Apr. 2003, vol. 21, No. 2, pp. 449-453. |
Kim et al., “Wafer-scale activated bonding of Cu—Cu, Cu—Si, and Cu—SiO2 at low temperature,” Proceedings—Electrochemical Society, 2003, vol. 19, pp. 239-247. |
Kissinger, G. et al., “Void-free silicon-wafer-bond stregthening in the 200-400 C range,” Sensors and Actuators A, 1993, vol. 36, pp. 149-156. |
Krauter, G. et al., “Low temperature silicon direct bonding for application in micromechanics: bonding energies for different combinations of oxides,” Sensors and Actuators A, 1998, vol. 70, pp. 271-275. |
Kunio, Takemitsu, “Three dimensional IC technology, using cubic method,” Journal of the JWS, Japan Welding Society, Apr. 5, 1994, vol. 63, No. 3, pp. 185-189. |
Lee, D. et al., “Slurry components in metal chemical mechanical planarization (CMP) process: A review,” International Journal of Precision Engineering and Manufacturing, Dec. 2016, vol. 17, No. 12, pp. 1751-1762. |
Li, Yuzhuo, “Key factors that influence step height reduction efficiency and defectivity during metal CMP,” Clarkson University, Levitronix CMP Users' Conference 2006, 2006, 32 pages. |
Li, Y.A. et al., “Low temperature copper to copper direct bonding,” Jpn. Appl. Phys. 37, 1998, pp. L1068-L1069. |
Li, Y.A. et al., “Systematic low temperature silicon bonding using pressure and temperature,” Jpn. J. Appl. Phys., vol. 37, 1998, pp. 737-741. |
Liu, Zi-Yu et al. “Detection and formation mechanism of micro-defects in ultrafine pitch Cu—Cu direct bonding,” Chin. Phys. B, 2016, vol. 25, No. 1, pp. 018103-1-018103-7. |
Liu, C. et al., “Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of nanotwinned Cu,” Scientific Reports, May 12, 2015, 5:09734, pp. 1-11. |
Lu, L. et al., “Grain growth and strain release in nanocrystalline copper,” Journal of Applied Physics, vol. 89, Issue 11, pp. 6408. |
Luo, Ying, “Slurry Chemistry Effects on Copper Chemical Mechanical Planarization,” University of Central Florida STARS, Electronic Theses and Disserations, 2004, Paper 36, 111 pages. |
Matsuzawa et al., “Room-temperature interconnection of electroplated Au microbump by means of surface activated bonding method,” Electornic Components and Technology Confererence, 2001, 51st Proceedings, IEEE, pp. 384-387. |
Monsma et al., “Development of the spin-valve transistor,” IEEE Tran. Magnet., vol. 33, No. 5, Sep. 1997, pp. 3495-3499. |
Mott, D. et al., “Synthesis of size-controlled and shaped copper nanoparticles,” Langmuir, 2007, vol. 23, No. 10, pp. 5740-5745. |
Onodera et al., “The effect of prebonding heat treatment on the separability of Au wire from Ag-plated Cu alloy substrate,” Electronics Packaging Manufacturing, IEEE Transactions, Jan. 2002, vol. 25, Issue 1, pp. 5-12. |
Ortleb, Thomas et al., “Controlling macro and micro surface topography for a 45nm copper CMP process using a high resolution profiler,” Proc. Of SPIE, 2008, vol. 6922, 11 pages. |
Paul, E. et al., “A model of copper CMP,” J. Electrochem. Soc., 2005, vol. 152, Issue 4, pp. G322-G328. |
Petition for Inter Partes Review of U.S. Pat. No. 7,485,968, IPR 2013-00381, filed Jun. 21, 2013, pp. 1-49. |
Reiche et al., “The effect of a plasma pretreatment on the Si/Si bonding behaviouir,” Electrochemical Society Proceedings, 1998, vol. 97-36, pp. 437-444. |
Rhoades, Robert L., “The Dark Art of CMP,” Future Fab International, Issue 24, 10 pages. |
Roberds et al., “Low temperature , in situ, plasma activated wafer bonding,” Electrochecmical Society Proceedings, 1997, vol. 97-36, pp. 598-606. |
Rosales-Yeomans, D. et al., “Evaluation of pad groove designs under reduced slurry flow rate conditions during copper CMP,” Journal of the Electrochemical Society, 2008, vol. 155, No. 10, pp. H812-H818. |
Schmidt, Martin A., Wafer-To-Wafer Bonding for Microstructure Formation, Proceedings of the IEEE, vol. 86, No. 8, 1998, pp. 1575-1586. |
Shigetou et al., “Cu—Cu direct bonding for bump-less interconnect,” Research Center for Advanced Science and Technolog., University of Tokyo, Optoelectronic Packaging and Solder Bumps, (2002), pp. 628-639. |
Shigetou et al., “Room temperature bonding of ultra-fine pitch and low-profiled Cu electrodes for bump-less interconnect,” 2003 Electronic Components and Technology Conference, pp. 848-852. |
Shigetou et al., “Room-temperature direct bonding of CMP-Cu film for bumpless interconnection,” Electronic Components and Technology Confererence, 51st Proceedings, 2001, IEEE, pp. 755-760. |
Shimatsu, T. et al., “Metal bonding during sputter film deposition,” J. Vac. Sci. Technol. A 16(4), 1998, pp. 2125-2131. |
Shingo et al., “Design and fabrication of an electrostatically actuated MEMS probe card,” Tranducers, Solid-State Sensors, Actuators and Microsystems, 12th International Conference, Jun. 8-12, 2003, vol. 2, pp. 1522-1525. |
Steinkirchner, J. et al., “Silicon wafer bonding via designed monolayers,” Advanced Materials, 1995, vol. 7, No. 7, 7 pages. |
Suga et al., “A new approach to Cu—Cu direct bump bonding,” IEMT/IMC Symposium, 1997, Joint International Electronic Manufacturing Symposium and the International Microelectronics Conference, Apr. 16-18, 1997, IEEE, pp. 146-151. |
Suga et al., “A new bumping process using lead-free solder paste,” Electronics Packaging Manufacturing, IEEE Transactions on (vol. 25, Issue 4), IEEE, Oct. 2002, pp. 253-256. |
Suga et al., “A new wafer-bonder of ultra-high precision using surface activated bonding (SAB) concept,” Electronic Components and Technology Conference, 2001, IEEE, pp. 1013-1018. |
Suga et al., “Bump-less interconnect for next generation system packaging,” Electronic Components and Technology Conference, 2001, IEEE, pp. 1003-1008. |
Suga et al., “Surface activated bonding—an approach to joining at room temperature,” Ceramic Transactions: Structural Ceramics Joining II, The American Ceramic Society, 1993, pp. 323-331. |
Suga et al., “Surface activated bonding for new flip chip and bumpless interconnect systems,” Electronic Components and Technology Conference, 2002, IEEE, pp. 105-111. |
Suga, “UHV room temperature joining by the surface activated bonding method,” Advances in science and technology, Techna, Faenza, Italie, 1999, pp. C1079-C1089. |
Suga, T., “Feasibility of surface activated bonding for ultra-fine pitch interconnection—A new concept of bump-less direct bonding for system level packaging,” The University of Tokyo, Research Center for Science and Technology, 2000 Electronic Components and Technology Conference, 2000 IEEE, pp. 702-705. |
Suga, T., “Room-temperature bonding on metals and ceramics,” Proceedings of the Second International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, The Electrochemical Society Proceedings, vol. 93-29 (1993), pp. 71-80. |
Takagi et al, “Wafer-scale room-temperature bonding between silicon and ceramic wafers by means of argon-beam surface activation,” Micro Electro Mechanical Systems, 2001, MEMS 2001, The 14th IEEE International Conference, Jan. 25, 2001, IEEE, pp. 60-63. |
Takagi et al., “Effect of surface roughness on room-temperature wafer bonding by Ar beam surface activation,” Japanese Journal of Applied Physics, 1998, vol. 37, Part 1, No. 1, pp. 4197. |
Takagi et al., “Low temperature direct bonding of silicon and silicon dioxide by the surface activation method,” Solid State Sensors and Actuators, 1997, Transducers '97 Chicago, 1997 International Conference, vol. 1, pp. 657-660. |
Takagi et al., “Room temperature silicon wafer direct bonding in vacuum by Ar beam irradiation,” Micro Electro Mehcanical Systems, MEMS '97 Proceedings, 1997, IEEE, pp. 191-196. |
Takagi et al., “Room-temperature bonding of lithium niobate and silicon wafers by argon-beam surface activation,” Appl. Phys. Lett., 1999. vol. 74, pp. 2387. |
Takagi et al., “Room-temperature wafer bonding of Si to LiNbO3, LiTaO3 and Gd3Ga5O12 by Ar-beam surface activation,” Journal of Micromechanics and Microengineering, 2001, vol. 11, No. 4, pp. 348. |
Takagi et al., “Room-temperature wafer bonding of silicon and lithium niobate by means of arbon-beam surface activation,” Integrated Ferroelectrics: An International Journal, 2002, vol. 50, Issue 1, pp. 53-59. |
Takagi et al., “Surface activated bonding silicon wafers at room temperature,” Appl. Phys. Lett. 68, 2222 (1996). |
Takagi et al., “Wafer-scale spontaneous bonding of silicon wafers by argon-beam surface activation at room temperature,” Sensors and Actuators A: Physical, Jun. 15, 2003, vol. 105, Issue 1, pp. 98-102. |
Tong et al., “Low temperature wafer direct bonding,” Journal of Microelectomechanical systems, Mar. 1994, vol. 3, No. 1, pp. 29-35. |
Tong et al., “Low temperature wafer direct bonding,” Journal of Microelectromechanical Systems, IEEE Service Center, Piscataway, NJ, vol. 3, No. 1, Mar. 1, 1994, pp. 29-35, XP-000885425, ISSN 1057-7157. |
Tong, Q.Y. et al., “Semiconductor wafer bonding,” Materials Chemistry and Physics, R25, 1999, 239 pages (exerpts). |
Tong, Q.Y. et al., “Semiconductor wafer bonding: recent developments,” Materials Chemistry and Physics, vol. 37, 1994, pp. 101-127. |
Tong, Q.Y. et al., “Semiconductor wafer bonding: science and technology,” 1999, 120 pages. |
Tong, Q.Y. et al., “Semiconductor wafer bonding: science and technology,” 1999, 159 pages. |
Tong, Q.Y. et al., “Wafer bonding and layer splitting for microsystems,” Advanced Materials, 1999, vol. 11, No. 17, pp. 1409-1425. |
Topol et al., “Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures,” 2004 Electronics Components and Technology Conference, 2004 IEEE, pp. 931-938. |
Tsau et al., “Fabrication process and plasticity of gold-gold thermocompression bonds,” Mater. Soc. Symp. Proc. 605, 171 (1999). |
Tsau, C.H. et al., “Characterization of low temperature wafer-level gold-gold thermocompression bonds,” Mater. Soc. Symp. Proc. 605, 1999, pp. 171-176. |
Vossen, J. et al., “Thin Film Processes II,” Academic Press, 1991, 62 pages. |
Vossen, J. et al., “Thin Film Processes,” Academic Press, 1978, 62 pages. |
Wang et al., “Reliability and microstructure of Au—Al and Au—Cu direct bonding fabricated by the Surface Activated Bonding,” Electronic Components and Technology Conference, 2002, IEEE, pp. 915-919. |
Wang et al., “Reliability of Au bump—Cu direct interconnections fabricated by means of surface activated bonding method,” Microelectronics Reliability, May 2003, vol. 43, Issue 5, pp. 751-756. |
Warner, K. et al., “Low-temperature oxide-bonded three-dimensional integrated circuits,” IEEE International Soi Conference, Oct. 2012, pp. 123-125. |
Weldon et al., “Physics and chemistry of silicon wafer bonding investigated by infrared absorption spectroscopy,” Journal of Vacuum Science & Technology B, Jul./Aug. 1996, vol. 14, No. 4, pp. 3095-3106. |
Wikipedia, “Chemical bond,” URL http://en.wikipedia.org/wiki/chemical_bond, accessed on Mar. 31, 2010, 10 pages. |
Wikipedia, “Van der Waals force,” URL https://en.wikipedia.org/wiki/Van_der_Waals_force, originally accessed on Mar. 31, 2010, 7 pages. |
Xu et al., “New Au—Al interconnect technology and its reliability by surface activated bonding,” Electronic Packaging Technology Proceedings, Oct. 28-30, 2003, Shanghai, China, pp. 479-483. |
Yablonovitch, E. et al., “Van der Waals bonding of GaAs on Pd leads to a permanent, solid-phase-topotaxial metallurgical bond,” Appl. Phys. Lett. 59, 1991, pp. 3159-3161. |
Image showing a partial cross-section of Sony IMX260 BSI image sensor from Samsung Galaxy S7; product believed to be released Mar. 2016. |
Image showing a partial cross-section of Omnivision OV16B10 16MP BSI image sensor from Huawei P20 Lite Phone; product believed to be released May 2018. |
Number | Date | Country | |
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20200126906 A1 | Apr 2020 | US |
Number | Date | Country | |
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62748653 | Oct 2018 | US | |
62902207 | Sep 2019 | US |