Patent Application
20140048799
Invisible/transparent nonvolatile memory devices are discussed herein. More particularly, memory devices that are transparent regardless of memory density are provided herein.
Electronic memory is the carrier for information storage, thus a key component in electronics. The realization of transparent memory may be desirable for integrated transparent electronics. While some individual memory bits/units can be invisible to the eye based upon their small size, as the bit/unit density increases, the visibility of the system becomes apparent because opaque silicon or opaque metal wiring are used throughout the structure.
If transparent materials are utilized for the entire design, then the entire memory would be transparent, regardless of the density. Transparent memory devices may allow the development of transparent electronics, such as, but not limited to, transparent displays with memory embedded in the display itself, touch screen displays, memory-containing visors, windscreens, and the like, including smart “heads-up” displays and “smart-windows”, with embedded memory or logic, memory arrays, transistors, microelectronics, nanoelectronics, and other electronic devices that utilize memory.
In one implementation, an optically transparent memory device comprises first and second electrodes, wherein the electrodes are formed from conductive and transparent material(s). The memory device also provides a resistive memory layer coupled to the first and second electrodes. The resistive memory layer is formed from a resistive memory material that is transparent. In some implementations, the memory device may be placed on a transparent substrate. In some implementations, the resistive memory layer may be positioned between the two electrodes to form a vertically stacked arrangement. In other implementations, the electrodes may be positioned on the resistive memory layer with a nanogap separation to form a horizontal arrangement.
Electrodes may be formed of any suitable conductive material, or a combination of conductive materials, that is also transparent. Non-limiting examples include graphene, indium tin oxide (ITO), transparent conducting oxides, fluorine doped tin oxide (FTO), doped zinc oxide, aluminum-doped zinc-oxide (AZO), indium-doped cadmium-oxide, transparent conducting polymers, polyacetylene, polyaniline, polypyrrole, polythiophenes, and/or nanocarbon coatings.
Resistive memory layers may be formed of any suitable resistive memory material, or a combination of resistive memory materials, that is also transparent. Non-limiting examples include SiOx, SiOxNy, SiOxCz, SiOxH, SiOxNyH, SiOxCzH or the like. In some implementations of SiOx, x is greater than or equal to 0.5 or less than or equal to 2. More preferably, in other implementations, x is greater than or equal to 1 or less than or equal to 2. In some implementations, y is greater than or equal to 0 or less than or equal to 1.33. In some implementations, z is greater than or equal to 0 or less than or equal to 1. In another implementation, each of x, y and z are equal or greater than 1 or equal or less than 2.
The foregoing has outlined rather broadly various features of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter.
For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions to be taken in conjunction with the accompanying drawings describing specific embodiments of the disclosure, wherein:
Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
Referring to the drawings in general, it will be understood that the illustrations are for the purpose of describing particular implementations of the disclosure and are not intended to be limiting thereto. While most of the terms used herein will be recognizable to those of ordinary skill in the art, it should be understood that when not explicitly defined, terms should be interpreted as adopting a meaning presently accepted by those of ordinary skill in the art.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the invention, as claimed. In this application, the use of the singular includes the plural, the word “a” or “an” means “at least one”, and the use of “or” means “and/or”, unless specifically stated otherwise. Furthermore, the use of the term “including”, as well as other forms, such as “includes” and “included”, is not limiting. Also, terms such as “element” or “component” encompass both elements or components comprising one unit and elements or components that comprise more than one unit unless specifically stated otherwise.
Transparent or invisible electronics may be desirable in the future generations of electronics. Electronic memory is the carrier for information storage, thus a key component in electronics. The realization of transparent memory is desirable for integrated transparent electronics. Though individual memory bits/units can be invisible to the eye based upon their small size, as the bit/unit density increases, the visibility of the system becomes apparent because opaque silicon and opaque metal wiring are used throughout the structure.
Potential technological advances from “invisible” or visibly transparent circuits have aroused extensive interest and motivated various studies in this direction. Progress has been made by using wide-bandgap semiconductors or nanowires to construct transparent transistors. For the realization of a fully integrated invisible circuit, high transparency is also desirable in one of the other indispensable circuitry elements: the memory unit. Although charge-based transparent memory can be constructed based on the transistor structure, it comes with the tradeoff in nonvolatility due to the limitations in achieving both high transparency and efficient charge trapping in the floating gate. This sacrifice can be eliminated by using resistive switching memory that can function on a non-charge based mechanism, provided that transparency is achieved both in the resistive memory material(s) and the electrodes.
While metal oxides or organic materials may potentially be suitable, a high-transparency memory device based on materials more suitable from the perspectives of processing and application is desirable. Using a transparent memory layer and transparent electrodes, a nonvolatile memory device featuring both high transparency and robust retention is provided. This transparent memory device may be optionally placed on transparent and/or flexible substrates.
For optical transparency without sacrificing the memory density or capacity, intrinsic transparency is desired in transparent memory systems. This may preclude many resistance-change materials with a bandgap <3.1 eV. The transparency can be further compromised by the top and bottom electrodes. For this reason, although transparent solid electrolytes can be involved in some metallic programmable cells, the use of a metal electrode as the filament-injection source limits the transparency in the device unit. Similarly, the requirement of a specific electrode-material interface in some resistive switching systems may restrict the choice of transparent electrode materials.
A non-limiting example of a resistive memory material providing resistive switching is SiOx. The intrinsic memory switching in SiOx enables the construction of completely metal-free transparent memory devices by using a transparent electrode material, such as graphene. For the fast progress in synthesis and abundance in the carbon sources, graphene has become a promising candidate for transparent electrode materials. The use of graphene and SiOx, another low-cost and industry-standard material, as materials for constructing memory devices provides advantages both in the material composition and processing.
Transparent resistive memory materials are capable of providing resistance changes and are also intrinsically transparent. For example, after initialization or electroforming, a resistive memory material may be capable of providing multiple conductivity states. A non-limiting example of a resistive memory material is SiOx. Because SiOx is intrinsically transparent and provides intrinsic memory effects, it may be a material suitable for use in transparent nonvolatile memory systems. The intrinsic memory effects in SiOx permit the use of transparent electrode materials, such as graphene, ITO, or the like, as TE to form TE/TML/TE memory units, where TML represents the transparent memory layer. The resulting memory unit features intrinsic transparency and simple structure in a two-terminal configuration, both of which may be desirable for a high-density transparent memory. Moreover, these transparent memories can be built upon a transparent substrate if used in conjunction with transparent wiring.
The x value in SiO, can be varied for desired performance. For example, in some embodiments, x is greater than or equal to 0.5 and less than or equal to 2. In other implementations, x is more preferably greater than equal to 1 or less than or equal to 2. An annealing process may be adopted to facilitate the initialization/electroforming process. Different etching methods (or recipes) may potentially lead to performance variations by introducing different defects at the vertical edges.
Note that since silicon filaments through direct Si—Si bond formation are likely to be responsible for the memory effect, other transparent materials with Si and O elements may be utilized as the transparent resistive memory material, such as SiOxNy, SiOxCz, SiOxH, SiOxNyH, SiOxCzH, or the like. In some embodiments, the y ratio of Ny to Si is in the range from 1.33 to 0. In some embodiments, the z ratio of Cz to Si is in the range from 1 to 0. In some embodiments, each of x, y and z are equal or greater than 1 or equal or less than 2.
A transparent memory layer contains at least one transparent resistive memory material. In some implementations, the transparent memory layer may contain multiple layers of transparent resistive memory materials, where the transparent resistive memory materials are the same or a combination of different resistive memory materials. The thickness of the transparent memory layer can be varied for desired performance.
Transparent resistive memory materials also allow the use of transparent electrode materials to form the conductive contacts. The transparent electrodes may be any suitable transparent conducting material, such as graphene, ITO, transparent conducting oxides, FTO, doped zinc oxide, AZO, indium-doped cadmium-oxide, transparent conducting polymers, polyacetylene, polyaniline, polypyrrole or polythiophenes, nanocarbon coatings, and the like. Transparent electrodes may be either symmetrical (same materials for both electrodes) or asymmetrical (different materials for the two electrodes).
The transparent resistive memory material may be coupled to transparent electrodes in any suitable arrangement, such as, but not limited to, a TE/TML/TE structure, where TE is a transparent electrode and TML is a transparent memory layer, or planar arrangement. Moreover, in some implementations, the transparent memory may be disposed on a transparent substrate. The transparent substrate may be any suitable insulating material that is transparent, such as glass, plastic, polymer(s), fluoropolymer(s), perfluoroalkoxy (PFA), poly(ethylene terephthalate), poly(methyl methacrylate) (PMMA), and/or the like. In some implementations, the materials of the transparent memory unit and/or the thickness of components may be selected to provide flexibility.
In some implementations, a single memory unit may be suitable for multi-bit storage. In some implementations, the memory is operated at certain level of vacuum or oxygen deficient environment. Non-limiting examples may include one or more inert gases, such as N2 and Ar. Standard industrial hermetic sealing techniques may be utilized to provide such an environment.
Optically transparent may include the range from 400 nm to about 800 nm in wavelength. Measurement of the optical transparency are provided at 550 nm, but similar levels of transparency are generally desired throughout the optical range. In some implementations, the memory has greater than 30% transparency at 550 nm. In some implementations, the memory has greater than 50% transparency at 550 nm. In some implementations, the memory has greater than 90% transparency at 550 nm. In some implementations, the first electrode or second electrode have greater than about 30% transparency at 550 nm. In some implementations, the first electrode or second electrode have greater than about 50% transparency at 550 nm. In some implementations, the first electrode or second electrode have greater than about 90% transparency at 550 nm.
Transparent memory systems and methods are suitable for use in electronic devices in which transparency is desired. Non-limiting examples of uses in electronic devices may include transparent displays with transparent memory embedded in the display itself; touch screen displays with transparent memory; transparent memory-containing visors, windscreens, and/or the like including smart “heads-up” displays or “smart-windows” with embedded memory and/or logic; transparent memory arrays; transparent memories integrated transistors; transparent memories integrated microelectronics; transparent memories integrated nanoelectronics; and/or various other electronic applications.
In some implementations, the memory units or memory arrays may be supported by a transparent substrate 40, such as glass, plastic, polymer(s), fluoropolymer(s), perfluoroalkoxy (PFA) polymers, poly(ethylene terephthalate), or the like. A voltage 50 may be applied to electrodes 30 to read or write transparent memory unit 10.
Once initialized/electroformed, the conductance of the TE/TML/TE unit can be modulated by voltage pulses of different magnitudes. For example, a moderate voltage pulse (e.g., 3-6 V) can set the unit into a low-resistance (ON) state while a higher voltage pulse (e.g., >7 V) can reset the unit to a high-resistance (OFF) state. It will be recognized by one of ordinary skill in the art that these resistance (or conductance) states can serve as the binary code 0 and 1 in digital information. Once programmed, the resistance states (both ON and OFF states) are nonvolatile. The memory reading operation occurs at a lower voltage (e.g., <3V) utilizing the same electrodes as write operations. Further, the memory state can be read nondestructively.
Bottom TE (e.g., graphene, ITO, or the like) deposition on a transparent substrate (e.g., glass, plastic, polymer, or the like).
Transparent memory layer (TML) is deposited on the bottom TE layer. As a non-limiting example, a SiO, (1≦x≦2) layer is deposited on the bottom TE in the fabrication shown.
Top TE deposition on the transparent memory layer.
Sacrificial mask definition by lithography, followed by etching process to define the memory units.
As a non-limiting example, transparent substrate 70 may be formed from SiOx, and transparent electrode 80 may be formed from graphene, ITO, and/or the like. Once initialized/electroformed, the conductance of the transparent memory unit 50 can be modulated by voltage pulses of different magnitudes, and can be read at low voltage.
Transparent memory systems may feature the following properties:
Intrinsic transparency: since the memory effect is intrinsic to the transparent memory materials, the memory is intrinsically transparent regardless of the density.
Nonvolatility and non-destructive reading: Once set or reset, the memory state remains when unbiased. The reading voltage used (e.g., +1 V or lower) does not affect the stored memory states.
Two-terminal configuration: The set, reset, and read operations may share the same electrodes, as opposed to a three-terminal configurations where reading and programming use different electrodes.
Non-charge based: No degradation was observed for the stored states after X-Ray exposure (dose ˜2 MGy). It shows the non-charge based nature and is potentially useful for radiation hardened electronics.
High ON/OFF ratio: experiments have shown that ON/OFF ratio as high as 1,000,000 can be achieved.
Promising scaling: The active filament involved in functioning is revealed to be at the size of ˜5 nm in diameter or smaller. This is promising for future device scaling to achieve high-density memory.
The use of SiOx in electronic devices is discussed further in U.S. patent application Ser. No. 12/240,673 filed Sep. 29, 2008; U.S. patent application Ser. No. 12/270,246 filed Nov. 13, 2008; PCT Application No. PCT/US11/27556 filed Mar. 8, 2011; and PCT Application No. PCT/US11/50812 filed Sep. 8, 2011.
The transparent nonvolatile memory can be used in transparent electronics as the transparent memory medium and/or logic medium. For example, displays with memory may utilize transparent memories embedded in the display itself; memory-containing visors and windscreens for smart “heads-up” displays may utilize the transparent memories; and any other electronics where it is desirable to have a transparent memory medium and/or logic medium may utilize transparent memories.
While other memory units, because of their small sizes, can be invisible to the eye at limited numbers, they inevitably become opaque when the density increases. These other memory units are not transparent because either the memory material itself is not transparent or these memory units require metal/silicon electrodes that are not transparent. In contrast, the transparent memory systems discussed herein utilize transparent memory material(s) providing intrinsic memory effects. Therefore, transparent memory material(s) can be combined with any other transparent (conducting) materials to form fully transparent memory units as described above. This transparency is maintained regardless of the memory density.
The following experimental examples are included to demonstrate particular aspects of the present disclosure. It should be appreciated by those of ordinary skill in the art that the methods described in the examples that follow merely represent illustrative embodiments of the disclosure. Those of ordinary skill in the art should, in light of the present disclosure, appreciate that many changes can be made in the specific embodiments described and still obtain a like or similar result without departing from the spirit and scope of the present disclosure.
The graphene films were synthesized directly on 25-μm-thick copper foils via the chemical vapor deposition (CVD) method. The process began with the thermal annealing of the copper foil at 1035° C. under H2 flow (500 sccm) for 20 min for grain coarsening. Then at the stabilized temperature of 1035° C. and pressure of 10 Torr, CH4 precursor gas (4 sccm) was introduced into the growth tube for graphene growth (40 min). The CH4 flow was turned off and the furnace was permitted to cool to room temperature. Protected with PMMA (poly(methyl methacrylate)), the graphene-coated copper film was then etched in a Fe(NO3)3 solution (0.5 M), followed by thoroughly cleaning in a 5% HNO3 solution and DI water. Then large monolayer graphene film was transferred to a highly doped (<0.005 Ω·cm) silicon substrate with a 300 nm thermal-grown SiO2 layer. After that, the graphene field effect transistors were fabricated by photolithography.
In order to ensure the graphene quality, the spectra and device behavior from the graphene was tested.
For ease of fabrication, the G/SiOx/G crossbar structure was fabricated on a silicon substrate (>5000 Ω·cm). The bottom bilayer graphene was first transferred on to the silicon substrate. Photolithography was used to define the resist mask, and then oxygen plasma was employed to etch and define the bottom graphene lines. Metal electrodes (Au/Ti=20 nm/2 nm, 100×100 μm2) were patterned at the end of each graphene line by photolithography, electron-beam evaporation and lift-off processes, serving as the bottom electrical contact for the probe tip. A layer of SiOx film (˜70 nm) was then deposited by electron-beam evaporation. The top bilayer graphene film was then transferred on to the SiOx layer. Photolithography was used to define the sacrificial layer for the top graphene lines, followed by the two-step SiOx etching method described before. Finally, top-metal electrode (Au/Ti=30 nm/5 nm, 100×100 μm2) was also patterned at the end of each top graphene line to form electrical contact for the upper probe tip.
As one of the backbones of the semiconductor industry, SiOx comes with the advantages in both its material composition and facile processing. With a large bandgap (˜9 eV), it also features high transparency. Instead of merely serving as a passive solid electrolyte in metallic programmable cells, an active role of SiOx in constructing resistive switching memory was recently revealed: SiOx itself can serve as the source of the formation of metallic-phase silicon filaments as well as the surrounding supportive matrix. The result is a memory effect that is intrinsic to SiOx and largely electrode-independent. This intrinsic memory effect in SiOx relaxes the restriction on the choice of electrode materials, making high-transparency or invisible memory devices feasible.
Non-limiting examples of transparent conductive materials, such as graphene and ITO, make them suitable for use as transparent electrodes. The combination of the two electrode materials in a single device demonstrates the versatility of the SiOx-based memory with respect to the choice of transparent electrode materials.
Vertical sandwiched pillar structures of G/SiOx/ITO (here G denotes graphene) were defined on a glass substrate. Specifically, the SiOx layer (˜70 nm thick) was prepared by physical vapor deposition (PVD) on a glass substrate coated with a layer of ITO (˜120 nm thick), with the top electrode consisting of bilayer graphene prepared by the chemical vapor deposition method and transfer process. Photolithography and reactive ion etching were then used to define the circular G/SiOx/ITO memory units at a diameter of ˜100 μm for an easy probe-tip landing. The electrical characterizations were performed in vacuum (10−5 Torr) at room temperature in a probe station connected to an Agilent 4155C semiconductor parameter analyzer.
After testing more than 20 devices, a device yield of ˜70% was achieved for the tested memory units, discounting the possibility of contamination-related memory effect; the 30% of non-working devices were short circuited. However, this depressed yield compared to that achieved in devices with polysilicon electrodes is likely caused by the atomically-thin nature of the graphene electrode, as structural damage in the graphene layer might result during the processing and/or the probe-tip landing processes (
As shown in
While graphene and graphene oxide have been used in some resistive switching systems, metal electrodes prevent the transparency of the memory devices. Because of the low optical absorbance in graphene, uniform transmittance as high as ˜90% over the visible range is achieved in the G/SiOx/G devices (
While the vertical pillar structures adopted above are frequently used for single-device testing purpose, other memory device may rely on the construction of memory arrays, such as a crossbar array. We further demonstrate the transparent SiOx crossbar memory arrays with graphene serving as both the electrode and interconnect material, in this case constructed atop a silicon/silicon oxide substrate.
The versatile transfer process of graphene to various substrates also enables the fabrication of the memory devices on plastic transparent substrates. Layered structures of G/SiOx/G were first deposited on a plastic (fluoropolymer, such as Perfluoroalkoxy (PFA)) substrate by transfer processes and SiOx PVD. Photolithography and etching processes were then used to define the vertical pillar structures. Here, a fluoropolymer was chosen as the plastic substrate for its comparatively high melting point (>280° C.) in order to sustain the current local heating involved during the initial electroforming process in the G/SiOx/G devices. The electroformed devices showed the same memory switching characteristics (
In summary, we have demonstrated transparent nonvolatile memory devices featuring high transparency, long retention and low programming currents. For the unique place of SiOx in the semiconductor industry and the promising future of graphene as an electrode material, the SiOx-graphene memory system features its advantages in both materials composition and processing.
Implementations described herein are included to demonstrate particular aspects of the present disclosure. It should be appreciated by those of skill in the art that the implementations described herein merely represent exemplary implementation of the disclosure. Those of ordinary skill in the art should, in light of the present disclosure, appreciate that many changes can be made in the specific implementations described and still obtain a like or similar result without departing from the spirit and scope of the present disclosure. From the foregoing description, one of ordinary skill in the art can easily ascertain the essential characteristics of this disclosure, and without departing from the spirit and scope thereof, can make various changes and modifications to adapt the disclosure to various usages and conditions. The implementations described hereinabove are meant to be illustrative only and should not be taken as limiting of the scope of the disclosure.
This application claims the benefit of U.S. Provisional Patent Application No. 61/443,420, filed on Feb. 16, 2011. The entirety of the above-referenced application is incorporated herein by reference.
This invention was made with government support under United States Army Grant No. W911NF-08-C-0133, awarded by the U.S. Department of Defense; United States Air Force Grant No. FA9550-10-C-0098, awarded by the U.S. Department of Defense; and United States Navy Grant No. N00039-10-0056, also awarded by the U.S. Department of Defense. The government has certain rights in the invention.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/US12/25435 | 2/16/2012 | WO | 00 | 11/4/2013 |
| Number | Date | Country | |
|---|---|---|---|
| 61443420 | Feb 2011 | US |
