Patent Grant
11227759
The present disclosure relates generally to charge detection mass spectrometry instruments, and more specifically to performing mass and charge measurements with such instruments.
Mass Spectrometry provides for the identification of chemical components of a substance by separating gaseous ions of the substance according to ion mass and charge. Various instruments and techniques have been developed for determining the masses of such separated ions, and one such technique is known as charge detection mass spectrometry (CDMS). In CDMS, ion mass is determined as a function of measured ion mass-to-charge ratio, typically referred to as “m/z,” and measured ion charge.
High levels of uncertainty in m/z and charge measurements with early CDMS detectors has led to the development of an electrostatic linear ion trap (ELIT) detector in which ions are made to oscillate back and forth through a charge detection cylinder. Multiple passes of ions through such a charge detection cylinder provides for multiple measurements for each ion, and it has been shown that the uncertainty in charge measurements decreases with n1/2, where n is the number of charge measurements. However, such multiple charge measurements necessarily limit the speed at which ion m/z and charge measurements can be obtained using current ELIT designs. Accordingly, it is desirable to seek improvements in ELIT design and/or operation which increase the rate of ion m/z and charge measurements over those obtainable using current ELIT designs.
The present disclosure may comprise one or more of the features recited in the attached claims, and/or one or more of the following features and combinations thereof. In a first aspect, an electrostatic linear ion trap (ELIT) array may comprise a plurality of elongated charge detection cylinders arranged end-to-end and each defining an axial passageway extending centrally therethrough, a plurality of ion mirror structures each defining a pair of axially aligned cavities and each defining an axial passageway therethrough extending centrally through both cavities, wherein a different one of the plurality of ion mirror structures is disposed between opposing ends of each arranged pair of the elongated detection cylinders, and front and rear ion mirrors each defining at least one cavity and an axial passageway extending centrally therethrough, the front ion mirror positioned at one end of the plurality of charge detection cylinders and the rear ion mirror positioned at an opposite end of the plurality of charge detection cylinders, wherein the axial passageways of the plurality of charge detection cylinders, the plurality of ion mirror structures, the front ion mirror and the rear ion mirror are axially aligned with one another to define a longitudinal axis passing centrally through the ELIT array.
In second aspect, a system for separating ions may comprise an ion source configured to generate ions from a sample, at least one ion separation instrument configured to separate the generated ions as a function of at least one molecular characteristic, and the ELIT described above in the first aspect, wherein ions exiting the at least one ion separation instrument pass into the ELIT array via the front ion mirror.
In a third aspect, a system for separating ions may comprise an ion source configured to generate ions from a sample, a first mass spectrometer configured to separate the generated ions as a function of mass-to-charge ratio, an ion dissociation stage positioned to receive ions exiting the first mass spectrometer and configured to dissociate ions exiting the first mass spectrometer, a second mass spectrometer configured to separate dissociated ions exiting the ion dissociation stage as a function of mass-to-charge ratio, and a charge detection mass spectrometer (CDMS), including the ELIT array described above in the first aspect, coupled in parallel with and to the ion dissociation stage such that the CDMS can receive ions exiting either of the first mass spectrometer and the ion dissociation stage, wherein masses of precursor ions exiting the first mass spectrometer are measured using CDMS, mass-to-charge ratios of dissociated ions of precursor ions having mass values below a threshold mass are measured using the second mass spectrometer, and mass-to-charge ratios and charge values of dissociated ions of precursor ions having mass values at or above the threshold mass are measured using the CDMS.
In a fourth aspect, a charge detection mass spectrometer (CDMS) may comprise a source of ions configured to generate and supply ions, an electrostatic linear ion trap (ELIT) array including a plurality of ion mirrors each defining a respective axial passageway therethrough, and a plurality of charge detection cylinders each defining a respective axial passageway therethrough, the plurality of ion mirrors and charge detection cylinders arranged to define a plurality of ELIT regions each including a different one of the plurality of charge detection cylinders positioned between a different respective pair of the plurality of ion mirrors with the axial passageway of each of the plurality of charge detection cylinders aligned with the axial passageways of the respective pair of the plurality of ion mirrors, the ELIT array configured to receive at least some of the ions supplied by the source of ions, and means for controlling each of the plurality of ion mirrors to trap a different one of the ions supplied by the source of ions in each of the plurality of ELIT regions and to cause the ion trapped in each of the plurality of ELIT regions to oscillate back and forth between the respective pair of the plurality of ion mirrors each time passing through a respective one of the plurality of charge detection cylinders.
In a fifth aspect, a method is provided for measuring ions supplied to an ion inlet of an electrostatic linear ion trap (ELIT) array having a plurality of ion mirrors and a plurality of elongated charge detection cylinders each defining a respective axial passageway therethrough, wherein the plurality of charge detection cylinders are arranged end-to-end in cascaded relationship with a different one of the plurality of ion mirrors positioned between each and with first and last ones of the plurality of ion mirrors positioned at respective opposite ends of the cascaded arrangement, wherein the first and last ion mirrors define the ion inlet and an ion exit of the ELIT array respectively, and wherein the axial passageways of each of the plurality of ion mirrors and charge detection cylinders are collinear with one another and define a longitudinal axis centrally therethrough to form a sequence of axially aligned ELIT array regions each defined by a combination of one of the plurality of charge detection cylinders and a respective pair of the plurality of ion mirrors at each end thereof. The method may comprise controlling at least one voltage source to apply voltages to each of the plurality of ion mirrors to establish an ion transmission electric field therein to pass the ions entering the ion inlet of the ELIT through each of the plurality of ion mirrors and charge detection cylinders and the ion exit of the ELIT array, wherein each ion transmission field is configured to focus ions passing therethrough toward the longitudinal axis, and controlling the at least one voltage source to sequentially modify the voltages applied to each the plurality of ion mirrors while maintaining previously applied voltages to remaining ones of the plurality of ion mirrors, beginning with the last ion mirror and ending with the first ion mirror, to sequentially establish an ion reflection electric field in each of the plurality of ion mirrors in a manner that sequentially traps a different ion in each of the ELIT regions, wherein each ion reflection electric field is configured to cause an ion entering a respective ion mirror from an adjacent one of the plurality of charge detection cylinders to stop and accelerate in an opposite direction back through the respective one of the plurality of charge detection cylinders, wherein the ion trapped in each of ELIT region oscillates back and forth between the respective ones of the plurality of ion mirrors, under the influence of the ion reflection electric fields established therein, each time passing through a respective one of the plurality of charge detection cylinders and inducing a corresponding charge thereon.
For the purposes of promoting an understanding of the principles of this disclosure, reference will now be made to a number of illustrative embodiments shown in the attached drawings and specific language will be used to describe the same.
This disclosure relates to an electrostatic linear ion trap (ELIT) array including two or more ELITs or ELIT regions and means for controlling them such that at least two of the ELITs or ELIT regions simultaneously operate to measure a mass-to-charge ratio and a charge of an ion trapped therein. In this manner, the rate of ion measurement is increased by at a factor of two or more as compared with conventional single ELIT systems, and a corresponding reduction in total ion measurement time is realized. In some embodiments, an example of which will be described in detail below with respect to
Referring to
In the embodiment illustrated in
In the illustrated embodiment, the region or cavity R2 of the first ion mirror M1, the charge detector CD1, the region or cavity R1 of the second ion mirror M2 and the spaces between CD1 and the ion mirrors M1, M2 together define a first ELIT or ELIT region E1 of the ELIT array 14, the region or cavity R2 of the second ion mirror M2, the charge detector CD2, the region or cavity R1 of the third ion mirror M3 and the spaces between CD2 and the ion mirrors M2, M3 together define a second ELIT or ELIT region E2 of the ELIT array 14, and the region or cavity R2 of the third ion mirror M3, the charge detector CD3, the region or cavity R1 of the ion mirror M4 and the spaces between CD3 and the mirror electrodes M3, M4 together define a third ELIT or ELIT region E3 of the ELIT array 14. It will be understood that in some alternate embodiments, the ELIT array 14 may include fewer cascaded ELITs or ELIT regions, e.g., two cascaded ELITs or ELIT regions, and that in other alternate embodiments the ELIT array 14 may include more cascaded ELITs or ELIT regions, e.g., four or more cascaded ELITs or ELIT regions. The construction and operation of any such alternate ELIT array 14 will generally follow that of the embodiment illustrated in
In the illustrated embodiment, four corresponding voltage sources V1-V4 are electrically connected to the ion mirrors M1-M4 respectively. Each voltage source V1-V4 illustratively includes one or more switchable DC voltage sources which may be controlled or programmed to selectively produce a number, N, of programmable or controllable voltages, wherein N may be any positive integer. Illustrative examples of such voltages will be described below with respect to
The voltage sources V1-V4 are illustratively shown electrically connected by a number, P, of signal paths to a conventional processor 16 including a memory 18 having instructions stored therein which, when executed by the processor 16, cause the processor 16 to control the voltage sources V1-V4 to produce desired DC output voltages for selectively establishing electric fields within the ion mirror regions or cavities R1, R2 of the respective ion mirrors M1-M4. P may be any positive integer. In some alternative embodiments, one or more of the voltage sources V1-V4 may be programmable to selectively produce one or more constant output voltages. In other alternative embodiments, one or more of the voltage sources V1-V4 may be configured to produce one or more time-varying output voltages of any desired shape. It will be understood that more or fewer voltage sources may be electrically connected to the mirror electrodes M1-M4 in alternate embodiments.
Each charge detector CD1-CD3 is electrically connected to a signal input of a corresponding one of three charge sensitive preamplifiers CP1-CP3, and the signal outputs of each charge preamplifier CP1-CP3 is electrically connected to the processor 16. The charge preamplifiers CP1-CP3 are each illustratively operable in a conventional manner to receive detection signals detected by a respective one of the charge detectors CD1-CD3, to produce charge detection signals corresponding thereto and to supply the charge detection signals to the processor 16. The processor 16 is, in turn, illustratively operable to receive and digitize the charge detection signals produced by each of the charge preamplifiers CP1-CP3, and to store the digitized charge detection signals in the memory 18. The processor 16 is further illustratively coupled to one or more peripheral devices 20 (PD) for providing signal input(s) to the processor 16 and/or to which the processor 16 provides signal output(s). In some embodiments, the peripheral devices 20 include at least one of a conventional display monitor, a printer and/or other output device, and in such embodiments the memory 18 has instructions stored therein which, when executed by the processor 16, cause the processor 16 to control one or more such output peripheral devices 20 to display and/or record analyses of the stored, digitized charge detection signals. In some embodiments, a conventional microchannel plate (MP) detector 22 may be disposed at the ion outlet of the ELIT array 14, i.e., at the ion outlet of the ion mirror M4, and electrically connected to the processor 16. In such embodiments, the microchannel plate detector 22 is operable to supply detection signals to the processor 16 corresponding to detected ions and/or neutrals.
As will be described in greater detail below, the voltage sources V1-V4 are illustratively controlled in a manner which selectively and successively guides ions entering the ELIT array 14 from the ion source 12 into each of the three separate ELITs or ELIT regions E1-E3 such that a different ion is trapped in each of the three regions E1-E3 and oscillates therein between respective ones of the ion mirrors M1-M4 each time passing through a respective one of the charge detectors CD1-CD3. A plurality of charge and oscillation period values are measured at each charge detector CD1-CD3, and the recorded results are processed to determine charge, mass-to-charge ratio and mass values of the ions in each of the three ELITs or ELIT regions E1-E3. Depending upon a number of factors including, but not limited to, the dimensions of the three ELITs or ELIT regions E1-E3, the ion oscillation frequency and the resident times of the ions within each of the three ELITs or ELIT regions E1-E3, the trapped ions oscillate simultaneously within at least two of the three ELITs or ELIT regions E1-E3, and in typical implementations within each of the three of the ELITs or ELIT regions E1-E3, such that ion charge and mass-to-charge ratio measurements can be collected simultaneously from at least two of the three ELITs or ELIT regions E1-E3.
Referring now to
A second mirror electrode 302 of the ion mirror MX is spaced apart from the first mirror electrode 301 and defines a passageway therethrough of diameter P2. A third mirror electrode 303 is spaced apart from the second mirror electrode 302 and likewise defines a passageway therethrough of diameter P2. The second and third mirror electrodes 302, 303 illustratively have equal thickness of D2≥D1. A fourth mirror electrode 304 is spaced apart from the third mirror electrode 303. The fourth mirror electrode 304 defines a passageway therethrough of diameter P2 and illustratively has a thickness D3 of between approximately 2D2 and 3D2. A plate, ring or grid 30A is illustratively positioned centrally within the passageway of the fourth mirror electrode 304 and defines a central aperture CA therethrough having a diameter P3. In the illustrated embodiment, P3<P1 although in other embodiments P3 may be greater than or equal to P1. A fifth mirror electrode 305 is spaced apart from the fourth mirror electrode 304, and a sixth mirror electrode 306 is spaced apart from the fifth mirror electrode 305. Illustratively, the fifth and sixth mirror electrodes 305, 306 are identical to the third and second mirror electrodes 303, 302 respectively.
For each of the ion mirrors M1-M3, a seventh mirror electrode 307 is formed by the ground cylinder, GCX, disposed about a respective one of the charge detectors CDX. The seventh electrode 307 of the ion mirror M4, on the other hand, may be a stand-alone electrode since the ion mirror M4 is the last in the sequence. In either case, the seventh mirror electrode 307 defines an aperture A2 centrally therethrough which serves as an ion entrance and/or exit to and/or from the ion mirror MX. The aperture A2 is illustratively the mirror image of the aperture A1, and is of a conical shape which decreases linearly between the external and internal faces of GCX from expanded diameter P2 defined at the external face of GCX to the reduced diameter P1 at the internal face of GCX. The seventh mirror electrode 307 illustratively has a thickness of D1. In some embodiments, as illustrated by example in
The mirror electrodes 301-307 are illustratively equally spaced apart from one another by a space S1. Such spaces S1 between the mirror electrodes 301-307 may be voids in some embodiments, i.e., vacuum gaps, and in other embodiments such spaces S1 may be filled with one or more electrically non-conductive, e.g., dielectric, materials. The mirror electrodes 301-307 are axially aligned, i.e., collinear, such that a longitudinal axis 24 passes centrally through each aligned passageway and also centrally through the apertures A1, A2 and CA. In embodiments in which the spaces S1 include one or more electrically non-conductive materials, such materials will likewise define respective passageways therethrough which are axially aligned, i.e., collinear, with the passageways defined through the mirror electrodes 301-307 and which have diameters of P2 or greater.
In each of the ion mirrors M1-M4, the region R1 is defined between the aperture A1 of the mirror electrode 301 and the central aperture CA defined through the plate or grid 30A. In each of the ion mirrors M1-M3, the adjacent region R2 is defined between the central aperture CA defined through the plate or grid 30A and the aperture A2 of the mirror electrode 307. In the illustrated embodiment, the ion mirrors M1-M3 are each shown in the form of a single mirror structure defining two adjacent and opposed, i.e., back-to-back, and axially aligned ion mirror regions R1, R2 separated by a plate 30A defining an aperture CA centrally therethrough. In some alternate embodiments, one or more of the ion mirrors M1-M3 (and/or M4 in embodiments in which M4 is configured identically to M1-M3), may instead be implemented as separate, axially aligned ion mirror structures arranged back-to-back relative to one another and spaced apart from one another by a conventional, electrically non-conductive spacer, e.g., an electrically insulating plate or ring. In some such embodiments, the separate, back-to-back ion mirror structures may be coupled together, i.e., affixed or mounted to one another, and in other embodiments such structures may be spaced apart from one another but not physically coupled together. In one illustrative example of this alternate embodiment using selected parts of the ion mirror structures illustrated in
Within each ELIT or ELIT region E1-E3, a respective charge detector CD1-CD3, each in the form of an elongated, electrically conductive cylinder, is positioned and spaced apart between corresponding ones of the ion mirrors M1-M4 by a space S2. Illustratively, S2>S1, although in alternate embodiments S2 may be less than or equal to S2. In any case, each charge detection cylinder CD1-CD3 illustratively defines a passageway axially therethrough of diameter P4, and each charge detection cylinder CD1-CD3 is oriented relative to the ion mirrors M1-M4 such that the longitudinal axis 24 extends centrally through the passageway thereof. In the illustrated embodiment, P1<P4<P2, although in other embodiments the diameter of P4 may be less than or equal to P1, or greater than or equal to P2. Each charge detection cylinder CD1-CD3 is illustratively disposed within a field-free region of a respective one of the ground cylinders GC1-GC3, and each ground cylinder GC1-GC3 is positioned between and forms part of respective ones of the ion mirrors M1-M4 as described above. In operation, the ground cylinders GC1-G3 are illustratively controlled to ground potential such that the first and seventh electrodes 301, 307 are at ground potential at all times. In some alternate embodiments, either or both of first and seventh electrodes 301, 307 in one or more of the ion mirrors M1-M4 may be set to any desired DC reference potential, and in other alternate embodiments either or both of first and seventh electrodes 301, 307 in one or more of the ion mirrors M1-M4 may be electrically connected to a switchable DC or other time-varying voltage source.
As briefly described above, the voltage sources V1-V4 are illustratively controlled in a manner which causes ions entering into the ELIT array 14 from the ion source 12 to be selectively trapped within each of the ELITs or ELIT regions E1-E3. More specifically, the voltage sources V1-V4 are controlled in a manner which sequentially traps an ion in each ELIT or ELIT region illustratively beginning with E3 and ending with E1, and which causes each trapped ion to oscillate within a respective one of the ELITs or ELIT regions E1-E3 between respective ones of the ion mirrors M1-M4. Each such trapped, oscillating ion thus repeatedly passes through a respective one of the charge detectors CD1-CD3 in a respective one of the three ELITs or ELIT regions E1-E3, and charge and oscillation period values are measured and recorded at each charge detector CD1-CD3 each time a respective oscillating ion passes therethrough. The measurements are recorded and the recorded results are processed to determine charge, mass-to-charge ratio and mass values of each of the three ions.
Within each ELIT or ELIT region E1-E3 of the ELIT array 14, an ion is captured and made to oscillate between opposed regions of the respective ion mirrors M1-M4 by controlling the voltage sources V1-V4 to selectively establish ion transmission and ion reflection electric fields within the regions R1, R2 of the ion mirrors M1-M4. In this regard, each voltage source VX is illustratively configured in one embodiment to produce seven DC voltages DC1-DC7, and to supply each of the voltages DC1-DC7 to a respective one of the mirror electrodes 301-307 of the respective ion mirror MX. In some embodiments in which one or more of the mirror electrodes 301-307 is to be held at ground potential at all times, the one or more such mirror electrodes 301-307 may alternatively be electrically connected to the ground reference of the voltage supply VX and the corresponding one or more voltage outputs DC1-DC7 may be omitted. Alternatively or additionally, in embodiments in which any two or more of the mirror electrodes 301-307 are to be controlled to the same non-zero DC values, any such two or more mirror electrodes 301-307 may be electrically connected to a single one of the voltage outputs DC1-DC7 and superfluous ones of the output voltages DC1-DC7 may be omitted.
As illustrated by example in
In the ion reflection mode, the voltages DC1-DC7 are selected to establish an ion reflection electric field REF1 within the region R1 of the ion mirror MX and to establish another ion reflection electric field REF2 within the region R2 of the ion mirror MX. Example ion reflection electric field lines are depicted in each of the ion mirror regions R1 and R2 of the ion mirror illustrated in
Example sets of output voltages DC1-DC7 produced by the voltage sources V1-V4 respectively to control a corresponding one of the ion mirrors M1-M4 to the ion transmission and reflection modes described above are shown in TABLE I below. It will be understood that the following values of DC1-DC7 are provided only by way of example, and that other values of one or more of DC1-DC7 may alternatively be used.
In the examples illustrated in
Referring now to
With reference to
Following step 102, the process 100 advances to step 104 where the processor 16 is operable to pause and determine when to advance to step 106. In one embodiment of step 102, the ELIT array 14 is illustratively controlled in a “random trapping mode” in which the ion mirrors M1-M4 are held in their transmission modes for a selected time period during which one or more ions generated by the ion source 12 will be expected to enter and travel through the ELIT array 14. As one non-limiting example, the selected time period which the processor 16 spends at step 104 before moving on to step 106 when operating in the random trapping mode is on the order of 1-3 millisecond (ms) depending upon the axial length of the ELIT array 14 and of the velocity of ions entering the ELIT array 14, although it will be understood that such selected time period may, in other embodiments, be greater than 3 ms or less than 1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 104 and loops back to the beginning of step 104. After passage of the selected time period, the process 100 follows the YES branch of step 104 and advances to step 106. In some alternate embodiments of step 104, such as in embodiments which include the microchannel plate detector 22, the processor 16 may be configured to advance to step 106 only after one or more ions has been detected by the detector 22, with or without a further additional delay period, so as to ensure that ions are being moved through the ELIT array 14 before advancing to step 106. In other alternate embodiments, the ELIT array 14 may illustratively be controlled by the processor 16 in a “trigger trapping mode” in which the ion mirrors M1-M4 are held in their ion transmission modes until an ion is detected at the charge detector CD3. Until such detection, the process 100 follows the NO branch of step 104 and loops back to the beginning of step 104. Detection by the processor 16 of an ion at the charge detector CD3 is indicative of the ion passing through the charge detector CD3 toward the ion mirror M4 and serves as a trigger event which causes the processor 16 to follow the YES branch of step 104 and advance to step 106 of the process 100.
Following the YES branch of step 104 and with reference to
Following step 106, the process 100 advances to step 108 where the processor 16 is operable to pause and determine when to advance to step 110. In embodiments of step 108 in which the ELIT array 14 is controlled by the processor 16 in random trapping mode, the ion mirrors M1-M3 are held at step 108 in their transmission modes for a selected time period during which an ion may enter the ELIT or ELIT region E3. As one non-limiting example, the selected time period which the processor 16 spends at step 108 before moving on to step 110 when operating in the random trapping mode is on the order of 0.1 millisecond (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 0.1 ms or less than 0.1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 108 and loops back to the beginning of step 108. After passage of the selected time period, the process 100 follows the YES branch of step 108 and advances to step 110. In alternate embodiments of step 108 in which the ELIT array 14 is controlled by the processor 16 in trigger trapping mode, the ion mirrors M1-M3 are held in their ion transmission modes until an ion is detected at the charge detector CD3. Until such detection, the process 100 follows the NO branch of step 108 and loops back to the beginning of step 108. Detection by the processor 16 of an ion at the charge detector CD3 ensures that the ion is moving through the charge detector CD3 and serves as a trigger event which causes the processor 16 to follow the YES branch of step 108 and advance to step 110 of the process 100.
Following the YES branch of step 108 and with reference to
The ion reflection electric field R31 operates, as described above, to reflect an ion entering the region R1 of M3 back toward the ion mirror M2 (and through the charge detector CD2) as described above with respect to
Following steps 110 and 112, the process 100 advances to step 114 where the processor 16 is operable to pause and determine when to advance to step 116. In embodiments of step 114 in which the ELIT array 14 is controlled by the processor 16 in random trapping mode, the ion mirrors M1-M2 are held at step 114 in their transmission modes for a selected time period during which one or more ions may enter the ELIT or ELIT region E2. As one non-limiting example, the selected time period which the processor 16 spends at step 114 before moving on to step 116 when operating in the random trapping mode is on the order of 0.1 millisecond (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 0.1 ms or less than 0.1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 114 and loops back to the beginning of step 108. After passage of the selected time period, the process 100 follows the YES branch of step 114 and advances to step 116. In alternate embodiments of step 114 in which the ELIT array 14 is controlled by the processor 16 in trigger trapping mode, the ion mirrors M1-M2 are held in their ion transmission modes until an ion is detected at the charge detector CD2. Until such detection, the process 100 follows the NO branch of step 114 and loops back to the beginning of step 114. Detection by the processor 16 of an ion at the charge detector CD2 ensures that the ion is moving through the charge detector CD2 and serves as a trigger event which causes the processor 16 to follow the YES branch of step 114 and advance to step 116 of the process 100.
The ion reflection electric field R21 operates, as described above, to reflect an ion entering the region R1 of M2 back toward the ion mirror M1 (and through the charge detector CD1) as described above with respect to
Following the YES branch of step 114 and as the ion in the ELIT or ELIT region E3 continues to oscillate back and forth through the charge detection cylinder CD3 between the ion mirrors M3 and M4, the process 100 advances to step 116. With reference to
Following steps 116 and 118, the process 100 advances to step 120 where the processor 16 is operable to pause and determine when to advance to step 122. In embodiments of step 120 in which the ELIT array 14 is controlled by the processor 16 in random trapping mode, the ion mirror M1 is held at step 120 in its transmission mode of operation for a selected time period during which one or more ions may enter the ELIT or ELIT region E1. As one non-limiting example, the selected time period which the processor 16 spends at step 120 before moving on to step 122 when operating in the random trapping mode is on the order of 0.1 millisecond (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 0.1 ms or less than 0.1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 120 and loops back to the beginning of step 120. After passage of the selected time period, the process 100 follows the YES branch of step 120 and advances to step 122. In alternate embodiments of step 120 in which the ELIT array 14 is controlled by the processor 16 in trigger trapping mode, the ion mirror M1 is held in its ion transmission mode of operation until an ion is detected at the charge detector CD1. Until such detection, the process 100 follows the NO branch of step 120 and loops back to the beginning of step 120. Detection by the processor 16 of an ion at the charge detector CD1 ensures that an ion is moving through the charge detector CD1 and serves as a trigger event which causes the processor 16 to follow the YES branch of step 120 and advance to step 122 of the process 100.
Following the YES branch of step 120, and an ion in the ELIT or ELIT region E3 continues to oscillate back and forth through the charge detection cylinder CD3 between the ion mirrors M3 and M4 and also as another ion in the ELIT or ELIT region E2 simultaneously continues to oscillate back and forth through the charge detection cylinder CD2 between the ion mirrors M2 and M3 the process 100 advances to step 122. With reference to
Following steps 122 and 124, the process 100 advances to step 126 where the processor 16 is operable to pause and determine when to advance to step 128. In one embodiment, the processor 16 is configured, i.e. programmed, to allow the ions to oscillate back and forth simultaneously through each of the ELITs or ELIT regions E1-E3 for a selected time period, i.e., a total ion cycle measurement time, during which ion detection events, i.e., by each of the charge detectors CD1-CD3, are recorded by the processor 16. As one non-limiting example, the selected time period which the processor 16 spends at step 126 before moving on to step 128 is on the order of 100-300 millisecond (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 300 ms or less than 100 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 126 and loops back to the beginning of step 126. After passage of the selected time period, the process 100 follows the YES branch of step 126 and advances to steps 128 and 140. In some alternate embodiments of the process 100, the voltage sources V1-V4 may illustratively be controlled by the processor 16 at step 126 to allow the ions to oscillate back in forth through the charge detectors CD1-CD3 a selected number of times, i.e., a total number of measurement cycles, during which ion detection events, i.e., by each of the charge detectors CD1-CD3, are recorded by the processor 16. Until the processor counts the selected number ion detection events of one or more of the charge detectors CD1-CD3, the process 100 follows the NO branch of step 126 and loops back to the beginning of step 126. Detection by the processor 16 of the selected number of ion detection events serves as a trigger event which causes the processor 16 to follow the YES branch of step 126 and advance to steps 128 and 140 of the process 100.
Following the YES branch of step 126, the processor 16 is operable at step 128 to control the voltage sources V1-V4 to set the output voltages DC1-DC7 of each in a manner which changes or switches the operation of all of the ion mirrors M1-M4 from the ion reflection mode of operation to the ion transmission mode of operation in which the ion mirrors M1-M4 each operate to allow passage of ions therethrough. Illustratively, the voltage sources V1-V4 are illustratively controlled at step 128 of the process 100 to produce the voltages DC1-DC7 according to the all-pass transmission mode as illustrated in Table I above, which re-establishes the ion trajectory 50 illustrated in
Following step 128, the processor 16 is operable at step 130 to pause for a selected time period to allow the ions contained within the ELIT array 14 to travel out of the ELIT array 14. As one non-limiting example, the selected time period which the processor 12 spends at step 130 before looping back to step 102 to restart the process 100 is on the order of 1-3 milliseconds (ms), although it will be understood that such selected time period may, in other embodiments, be greater than 3 ms or less than 1 ms. Until the selected time period has elapsed, the process 100 follows the NO branch of step 130 and loops back to the beginning of step 130. After passage of the selected time period, the process 100 follows the YES branch of step 130 and loops back to step 102 to restart the process 100.
Also following the YES branch of step 126, the process 100 additionally advances to step 140 to analyze the data collected during steps 112, 118 and 124 of the process 100 just described. In the illustrated embodiment, the data analysis step 140 illustratively includes step 142 in which the processor 16 is operable to compute Fourier transforms of the recorded sets of stored charge detection signals provided by each of the charge preamplifiers CP1-CP3. The processor 16 is illustratively operable to execute step 142 using any conventional digital Fourier transform (DFT) technique such as for example, but not limited to, a conventional Fast Fourier Transform (FFT) algorithm. In any case, the processor 16 is operable at step 142 to compute three Fourier Transforms, FT1, FT2 and FT3, wherein FT1 is the Fourier Transform of the recorded set of charge detection signals provided by the first charge preamplifier CP1, thus corresponding to the charge detection events detected by the charge detection cylinder CD1 of the ELIT or ELIT region E1, FT2 is the Fourier Transform of the recorded set of charge detection signals provided by the first charge preamplifier CP2, thus corresponding to the charge detection events detected by the charge detection cylinder CD2 of the ELIT or ELIT region E2 and FT3 is the Fourier Transform of the recorded set of charge detection signals provided by the first charge preamplifier CP3, thus corresponding to the charge detection events detected by the charge detection cylinder CD3 of the ELIT or ELIT region E3.
Following step 142, the process 100 advances to step 144 where the processor 16 is operable to compute three sets of ion mass-to-charge ratio values (m/z1, m/z2 and m/z3), ion charge values (z1, z2 and z3) and ion mass values (m1, m2 and m3), each as a function of a respective one of the computed Fourier Transform values FT1, FT2, FT3). Thereafter at step 146 the processor 16 is operable to store the computed results in the memory 18 and/or to control one or more of the peripheral devices 20 to display the results for observation and/or further analysis.
It is generally understood that the mass-to-charge ratio (m/z) of ion(s) oscillating back and forth between opposing ion mirrors in any of the ELITs or ELIT regions E1-E3 is inversely proportional to the square of the fundamental frequency ff of the oscillating ion(s) according to the equation:
m/z=C/ff2,
where C is a constant that is a function of the ion energy and also a function of the dimensions of the respective ELIT or ELIT region, and the fundamental frequency ff is determined directly from the respective computed Fourier Transform. Thus, ff1 is the fundamental frequency of FT1, ff2 is the fundamental frequency of FT2 and ff3 is the fundamental frequency of FT3. Typically, C is determined using conventional ion trajectory simulations. In any case, the value of the ion charge, z, is proportional to the magnitude FTMAG of the fundamental frequency of the respective Fourier Transform FT, taking into account the number of ion oscillation cycles. In some cases, the magnitude(s) of one or more of the harmonic frequencies of the FFT may be added to the magnitude of the fundamental frequency for purposes of determining the ion charge values. In any case, ion mass, m, is then calculated as a product of m/z and z. Thus, with respect to the recorded set of charge detection signals provided by the first charge preamplifier CP1, the processor 16 is operable at step 144 to compute m/z1=C/ff12, z1=F(FTMAG1) and m1=(m/z1)(z1). With respect to the recorded set of charge detection signals provided by the second charge preamplifier CP2, the processor 16 is similarly operable at step 144 to compute m/z2=C/ff22, z2=F(FTMAG2) and m2=(m/z2)(z2), and with respect to the recorded set of charge detection signals provided by the third charge preamplifier CP3, the processor 16 is likewise operable at step 144 to compute m/z3=C/ff32, z3=F(FTMAG3) and m3=(m/z3)(z3).
Referring now to
Focusing on the ion source 12, it will be understood that the source 12 of ions entering the ELIT 10 may be or include, in the form of one or more of the ion source stages IS1-ISQ, any conventional source of ions as described above, and may further include one or more conventional instruments for separating ions according to one or more molecular characteristics (e.g., according to ion mass, ion mass-to-charge, ion mobility, ion retention time, or the like) and/or one or more conventional ion processing instruments for collecting and/or storing ions (e.g., one or more quadrupole, hexapole and/or other ion traps), for filtering ions (e.g., according to one or more molecular characteristics such as ion mass, ion mass-to-charge, ion mobility, ion retention time and the like), for fragmenting or otherwise dissociating ions, for normalizing ion charge states, and the like. It will be understood that the ion source 12 may include one or any combination, in any order, of any such conventional ion sources, ion separation instruments and/or ion processing instruments, and that some embodiments may include multiple adjacent or spaced-apart ones of any such conventional ion sources, ion separation instruments and/or ion processing instruments.
Turning now to the ion processing instrument 70, it will be understood that the instrument 70 may be or include, in the form of one or more of the ion processing stages OS1-OSR, one or more conventional instruments for separating ions according to one or more molecular characteristics (e.g., according to ion mass, ion mass-to-charge, ion mobility, ion retention time, or the like) and/or one or more conventional ion processing instruments for collecting and/or storing ions (e.g., one or more quadrupole, hexapole and/or other ion traps), for filtering ions (e.g., according to one or more molecular characteristics such as ion mass, ion mass-to-charge, ion mobility, ion retention time and the like), for fragmenting or otherwise dissociating ions, for normalizing ion charge states, and the like. It will be understood that the ion processing instrument 70 may include one or any combination, in any order, of any such conventional ion separation instruments and/or ion processing instruments, and that some embodiments may include multiple adjacent or spaced-apart ones of any such conventional ion separation instruments and/or ion processing instruments. In any implementation which includes one or more mass spectrometers, any one or more such mass spectrometers may be implemented in any of the forms described above with respect to
As one specific implementation of the ion separation instrument 60 illustrated in
As another specific implementation of the ion separation instrument 60 illustrated in
As yet another specific implementation of the ion separation instrument 60 illustrated in
As still another specific implementation of the ion separation instrument 60 illustrated in
Referring now to
MS/MS, e.g., using only the ion separation instrument 82, is a well-established approach where precursor ions of a particular molecular weight are selected by the first mass spectrometer 84 (MS1) based on their m/z value. The mass selected precursor ions are fragmented, e.g., by collision-induced dissociation, surface-induced dissociation, electron capture dissociation or photo-induced dissociation, in the ion dissociation stage 86. The fragment ions are then analyzed by the second mass spectrometer 86 (MS2). Only the m/z values of the precursor and fragment ions are measured in both MS1 and MS2. For high mass ions, the charge states are not resolved and so it is not possible to select precursor ions with a specific molecular weight based on the m/z value alone. However, by coupling the instrument 82 to the CDMS 10, 200, 300 illustrated and described herein, it is possible to select a narrow range of m/z values and then use the CDMS 10, 200, 300 to determine the masses of the m/z selected precursor ions. The mass spectrometers 84, 88 may be, for example, one or any combination of a magnetic sector mass spectrometer, time-of-flight mass spectrometer or quadrupole mass spectrometer, although in alternate embodiments other mass spectrometer types may be used. In any case, the m/z selected precursor ions with known masses exiting MS1 can be fragmented in the ion dissociation stage 86, and the resulting fragment ions can then be analyzed by MS2 (where only the m/z ratio is measured) and/or by the CDMS instrument 10, 200, 300 (where the m/z ratio and charge are measured simultaneously). Low mass fragments, i.e., dissociated ions of precursor ions having mass values below a threshold mass value, e.g., 10,000 Da (or other mass value), can thus be analyzed by conventional MS, using MS2, while high mass fragments (where the charge states are not resolved), i.e., dissociated ions of precursor ions having mass values at or above the threshold mass value, can be analyzed by the CDMS 10, 200, 300.
Referring now to
The ELIT 204 is illustratively identical to the ELIT 202 just described with ion mirrors M3, M4 corresponding to the ion mirrors M1, M2 of the ELIT 202, with the voltage sources V3, V4 corresponding to the voltage sources V1, V2 of the ELIT 202 and with inlet/outlet apertures AI2/AO2 defining a longitudinal axis 242 extending through the ELIT 204 and illustratively bisecting the apertures AI2, AO2. A charge amplifier CP2 is electrically coupled to the charge detection cylinder CD2 of the ELIT 204, and is illustratively identical in structure and function to the charge preamplifier CP2 illustrated in
The ELIT 206 is likewise illustratively identical to the ELIT 202 just described with ion mirrors M5, M6 corresponding to the ion mirrors M1, M2 of the ELIT 202, with the voltage sources V5, V6 corresponding to the voltage sources V1, V2 of the ELIT 202 and with inlet/outlet apertures AI3/AO3 defining a longitudinal axis 243 extending through the ELIT 206 and illustratively bisecting the apertures AI3, AO3. A charge amplifier CP3 is electrically coupled to the charge detection cylinder CD3 of the ELIT 206, and is illustratively identical in structure and function to the charge preamplifier CP3 illustrated in
The voltage sources V1-V6, as well as the charge preamplifier CP1-CP3, are operatively coupled to a processor 210 including a memory 212 as described with respect to
In the embodiment illustrated in
While the ELITs 202, 204 and 206 are illustrated in
In the illustrated embodiment, the ion steering array 208 illustratively includes 3 sets of four electrically conductive pads P1-P4, P5-P8 and P9-P12 arranged on each of two spaced-apart planar substrates such that each of the electrically conductive pads P1-P12 on one of the planar substrates is aligned with and faces a respective one of the electrically conductive pads on the other substrate. In the embodiment illustrated in
Referring now to
Referring specifically to
The opposed pad pairs P31, P32 and P41, P42 are upstream of the opposed pad pairs P11, P12 and P21, P22, and the opposed pad pairs P11, P12 and P21, P22 are conversely downstream of the opposed pad pairs P41, P42 and P31, P32. In this regard, the “unaltered direction of ion travel” through the channel 225, as this term is used herein, is “upstream,” and generally parallel with the direction A of ions exiting the ion source 12. Transverse edges 220C, 222C of the substrates 220, 222 are aligned, as are opposite transverse edges 220D, 222D, and the “altered direction of ion travel” through the channel 225, as this term is used herein, is from the aligned edges 220C, 222C toward the aligned edges 220D, 222D, and generally perpendicular to both such aligned edges 220C, 222C and 220D, 222D.
In the embodiment illustrated in
Referring now to
Referring now specifically to
Referring again to
With reference to
With reference to
With reference to
At the same time or following control of the ELIT 202 as just described, and with the ion oscillating within the ELIT 202 back and forth between the ion mirrors M1, M2, the processor 210 is operable to control VST to switch the voltages applied to pads P2 and P4 back to VREF, to switch the voltages applied to pads P5-P8 from −XV to VREF and to switch the voltages applied to pads P9-P12 from VREF to −XV, as also illustrated in
With reference now to
Following the operating state illustrated in
At the same time or following control of the ELIT 204 as just described with respect to
In any case, the processor 210 is operable at some point thereafter to control V6 to produce voltages which cause the ion mirror M6 to switch from the ion transmission mode of operation to the ion reflection mode of operation so as to reflect ions back toward M5. The timing of this switch of M6 illustratively depends on whether the operation of the ELIT 206 is being controlled by the processor 210 in random trapping mode or in trigger trapping mode as described with respect to
As also illustrated in
After the ions have oscillated back and forth within each of the ELITs 202, 204 and 206 for a total ion cycle measurement time or a total number of measurement cycles, e.g., as described above with respect to step 126 of the process 100 illustrated in
Depending upon a number of factors including, but not limited to, the dimensions of the ELITS 202, 204, 206, the frequency or frequencies of oscillation of ions through each ELIT 202, 204, 206 and the total number of measurement cycles/total ion cycle measurement time in each ELIT 202, 204, 206, ions may simultaneously oscillate back and forth within at least two of the ELITs 202, 204 and 206, and ion charge/timing measurements taken from respective ones of the charge preamplifiers CP1, CP2 and CP3 may therefore be simultaneously collected and stored by the processor 210. In the embodiment illustrated in
Referring now to
The CDMS 300 is identical in some respects to the CDMS 200 in that the CDMS 300 includes an ion source 12 operatively coupled to an ion steering array 208, the structures and operation of which are as described above. The instructions store in the memory 306 further illustratively include instructions which, when executed by the processor 304, cause the processor 304 to control the ion steering array voltage source VST as described below.
In the embodiment illustrated in
An ion trap voltage source VIT is operatively coupled between the processor 304 and each of the ion traps IT1-IT3. The voltage source VIT is illustratively configured to produce suitable DC and AC, e.g., RF, voltages for separately and individually controlling operation of each of the ion traps IT1-IT3 in a conventional manner.
The processor 304 is illustratively configured, e.g. programmed, to control the ion steering array voltage source VST to sequentially steer one or more ions exiting the ion aperture IA of the ion source 12, as described with respect to
As the ion traps IT1-IT3 are being filled with ions, the processor 304 is configured, i.e., programmed, to control V1 and V2 to produce suitable DC voltages which control the ion mirrors M1 and M2 of the ELIT E1-E2 to operate in their ion transmission operating modes so that any ions moving therein exit via the ion outlet apertures AO1-AO3 respectively. When, via control of the ion steering array 208 and the ion traps IT1-IT3 as just described, at least one ion is trapped within each of the ion traps IT1-IT3, the processor 304 is configured, i.e., programmed, to control V2 to produce suitable DC voltages which control the ion mirrors M2 of the ELITs E1-E3 to operate in their ion reflection operating modes. Thereafter, the processor 304 is configured to control the ion trap voltage source VIT to produce suitable voltages which cause the ion outlets TO1-TO3 of the respective ion traps IT1-IT3 to simultaneously open to direct an ion trapped therein into a respective one of the ELITs E1-E3 via a respective ion inlet aperture AI1-AI3 of a respective ion mirror M1. When the processor 304 determines that an ion has entered each ELIT E1-E3, e.g., after passage of some time period following simultaneous opening of the ion traps IT1-IT3 or following charge detection by each of the charge preamplifiers CP1-CP3, the processor 304 is operable to control the voltage source V1 to produce suitable DC voltages which control the ion mirrors M1 of the ELTs E1-E3 to operate in their ion reflection operating modes, thereby trapping an ion within each of the ELITs E1-E3.
With the ion mirrors M1 and M2 of each ELIT E1-E3 operating in the ion reflection operating mode, the ion in each ELIT E1-E3 simultaneously oscillates back and forth between M1 and M2, each time passing through a respective one of the charge detection cylinders CD1-CD3. Corresponding charges induced on the charge detection cylinders CD1-CD3 are detected by the respective charge preamplifiers CP1-CP3, and the charge detection signals produced by the charge preamplifiers CP1-CP3 are stored by the processor 304 in the memory 306 and subsequently processed by the processor 304, e.g., as described with respect step 140 of the process 100 illustrated in
Although the embodiments of the CDMS 200 and 300 are illustrated in
It will be understood that the dimensions of the various components of any of the ELIT arrays 14, 205, 302 and the magnitudes of the electric fields established therein in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described above may illustratively be selected to establish a desired duty cycle of ion oscillation within one or more of the ELITs or ELIT regions E1-E3, corresponding to a ratio of time spent by an ion in the respective charge detection cylinder CD1-CD3 and a total time spent by the ion traversing the combination of the corresponding ion mirrors and the respective charge detection cylinder CD1-CD3 during one complete oscillation cycle. For example, a duty cycle of approximately 50% may be desirable in one or more of the ELITs or ELIT regions for the purpose of reducing noise in fundamental frequency magnitude determinations resulting from harmonic frequency components of the measure signals. Details relating to such dimensional and operational considerations for achieving a desired duty cycle, e.g., such as 50%, are illustrated and described in U.S. Patent Application Ser. No. 62/616,860, filed Jan. 12, 2018, U.S. Patent Application Ser. No. 62/680,343, filed Jun. 4, 2018 and co-pending International Patent Application No. PCT/US2019/013251, filed Jan. 11, 2019, all entitled ELECTROSTATIC LINEAR ION TRAP DESIGN FOR CHARGE DETECTION MASS SPECTROMETRY, the disclosures of which are all expressly incorporated herein by reference in their entireties.
It will be further understood that one or more charge calibration or resetting apparatuses may be used with the charge detection cylinder(s) of any one or more of the ELIT arrays 14, 205, 302 and/or in any one or more of the regions E1-E3 of the ELIT array 14 in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein. An example of one such charge calibration or resetting apparatus is illustrated and described in U.S. Patent Application Ser. No. 62/680,272, filed Jun. 4, 2018 and in International Patent Application No. PCT/US2019/013284, filed Jan. 11, 2019, both entitled APPARATUS AND METHOD FOR CALIBRATING OR RESETTING A CHARGE DETECTOR, the disclosures of which are both expressly incorporated herein by reference in their entireties.
It will be further understood that one or more charge detection optimization techniques may be used with any one or more of the ELIT arrays 14, 205, 302 and/or with one or more regions E1-E3 of the ELIT array 14 in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein, e.g., for trigger trapping or other charge detection events. Examples of some such charge detection optimization techniques are illustrated and described in U.S. Patent Application Ser. No. 62/680,296, filed Jun. 4, 2018 and in co-pending International Patent Application No. PCT/US2019/13280, filed Jan. 11, 2019, both entitled APPARATUS AND METHOD FOR CAPTURING IONS IN AN ELECTROSTATIC LINEAR ION TRAP, the disclosures of which are both expressly incorporated herein by reference in their entireties.
It will be further still understood that one or more ion source optimization apparatuses and/or techniques may be used with one or more embodiments of the ion source 12 in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein, some examples of which are illustrated and described in U.S. Patent Application Ser. No. 62/680,223, filed Jun. 4, 2018 and entitled HYBRID ION FUNNEL-ION CARPET (FUNPET) ATMOSPHERIC PRESSURE INTERFACE FOR CHARGE DETECTION MASS SPECTROMETRY, and in International Patent Application No. PCT/US2019/013274, filed Jan. 11, 2019 and entitled INTERFACE FOR TRANSPORTING IONS FROM AN ATMOSPHERIC PRESSURE ENVIRONMENT TO A LOW PRESSURE ENVIRONMENT, the disclosures of which are both expressly incorporated herein by reference in their entireties.
It will be still further understood that any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein may be implemented in accordance with real-time analysis and/or real-time control techniques, some examples of which are illustrated and described in U.S. Patent Application Ser. No. 62/680,245, filed Jun. 4, 2018 and International Patent Application No. PCT/US2019/013277, filed Jan. 11, 2019, both entitled CHARGE DETECTION MASS SPECTROMETRY WITH REAL TIME ANALYSIS AND SIGNAL OPTIMIZATION, the disclosures of which are both expressly incorporated herein by reference in their entireties.
It will be yet further understood that in any of the systems 10, 60, 80, 200, 300 illustrated in the attached figures and described herein, one or more ion inlet trajectory control apparatuses and/or techniques may be implemented to provide for simultaneous measurements of multiple individual ions within one or more of the ELITs or ELIT regions of any of the ELIT arrays illustrated in the attached figures and described herein. Examples of some such ion inlet trajectory control apparatuses and/or techniques are illustrated and described in U.S. Patent Application Ser. No. 62/774,703, filed Dec. 3, 2018 and in International Patent Application No. PCT/US2019/013285, filed Jan. 11, 2019, both entitled APPARATUS AND METHOD FOR SIMULTANEOUSLY ANALYZING MULTIPLE IONS WITH AN ELECTROSTATIC LINEAR ION TRAP, the disclosures of which are both expressly incorporated herein by reference in their entireties.
While this disclosure has been illustrated and described in detail in the foregoing drawings and description, the same is to be considered as illustrative and not restrictive in character, it being understood that only illustrative embodiments thereof have been shown and described and that all changes and modifications that come within the spirit of this disclosure are desired to be protected.
This application is a U.S. national stage entry of PCT Application No. PCT/US2019/013283, filed Jan. 11, 2019, which claims the benefit of and priority to U.S. Provisional Patent Application Ser. No. 62/680,315, filed Jun. 4, 2018, the disclosures of which are incorporated herein by reference in their entireties.
This invention was made with government support under CHE1531823 awarded by the National Science Foundation. The United States Government has certain rights in the invention.
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| Number | Date | Country | |
|---|---|---|---|
| 20210217606 A1 | Jul 2021 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62680315 | Jun 2018 | US |
