Patent Application
20240355905
The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Thus far the demand has been met in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.
Multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. Another multi-gate device, introduced in part to address performance challenges associated with FinFETs, is the gate-all-around (GAA) transistor. GAA devices get their name from the gate structure which extends completely around the channel, providing better electrostatic control than FinFETs. FinFET devices and GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes. Further, the three-dimensional structure of such devices allows them to be aggressively scaled while maintaining gate control and mitigating SCEs.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “over”, “overlying”, “above”, “upper”, “top”, “under”, “underlying”, “beneath”, “below”, “lower”, “bottom”, “side”, and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In certain embodiments herein, a “material layer” is a layer that includes at least 50 wt. % of the identified material, for example at least 60 wt. % of the identified material, at least 75 wt. % of the identified material, or at least 90 wt. % of the identified material, or substantially 100 wt. % of the identified material; and a layer that is a “material” includes at least 50 wt. % of the identified material, for example at least 60 wt. % of the identified material, at least 75 wt. % of the identified material, or at least 90 wt. % of the identified material, or substantially 100 wt. % of the identified material. For example, certain embodiments, each of a titanium nitride layer and a layer that is titanium nitride is a layer that is at least 50 wt. %, at least 60 wt. %, at least 75 wt. %, titanium nitride, or at least 90 wt. %, or substantially 100 wt. %, titanium nitride.
For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication of semiconductor devices are well-known and so, in the interest of brevity, many conventional processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. As will be readily apparent to those skilled in the art upon a complete reading of the disclosure, the structures disclosed herein may be employed with a variety of technologies, and may be incorporated into a variety of semiconductor devices and products. Further, it is noted that semiconductor device structures include a varying number of components and that single components shown in the illustrations may be representative of multiple components.
It is also noted that this disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of a channel region. These multi-gate devices may include a P-type metal-oxide-semiconductor device or an N-type metal-oxide-semiconductor multi-gate device. Specific examples may be presented and referred to herein as FinFET devices, on account of their fin-like structure. Also presented herein are embodiments of a type of multi-gate transistor referred to as a gate-all-around (GAA) device. A GAA device includes any device that has its gate structure, or portion thereof, formed on four sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in nanosheet channel(s), nanowire channel(s), bar-shaped channel(s), and/or other suitable channel configurations. Herein, the term “nanosheet channel” is intended to include nanowire channel and bar-shaped channel configurations.
Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanosheets) associated with a single, contiguous gate structure. However, one of ordinary skill would recognize that the teaching can apply to a single channel (e.g., single nanosheet) or any number of channels. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.
As described herein, processes are performed to isolate adjacent devices. For example, vertically-extending isolation structures are formed between adjacent devices and have a relatively shallow depth to provide for reduced parasitic capacitance, as compared to vertically-extending isolation structures extending to a deeper depth. Further, laterally-extending isolation layers are formed between source/drain regions and the underlying semiconductor material. Such laterally-extending isolation layers reduce leakage current passing under the shallow vertically-extending isolation structures. As used herein, “source/drain region(s)” may refer to a source region or a drain region, individually or collectively depending on the context.
In certain embodiments, a continuous poly on diffusion edge (CPODE) process is used to provide isolation structures between adjacent devices. For purposes of this disclosure, a “diffusion edge” may be equivalently referred to as an active edge, where for example an active edge abuts adjacent active regions. Further, an active region includes a region where transistor structures are formed (e.g., including source, drain, and gate/channel structures). In some examples, active regions may be disposed between insulating regions. The CPODE process may provide an isolation structure between neighboring active regions, and thus neighboring transistors, by performing a dry etching process along an active edge (e.g., at a boundary of adjacent active regions) to form a cut region, and by filling the cut region with a dielectric, such as silicon nitride (SiN).
Before the CPODE process, the active edge may include a GAA dummy structure having a gate stack and a plurality of channels (e.g., nanosheet channels). The plurality of channels may each include a chemical oxide layer formed thereon, and high-K dielectric/metal gate layers may be formed over the chemical oxide layer and between adjacent channels of the plurality of channels. In addition, inner spacers may be disposed between adjacent channels at lateral ends of the plurality of channels. In various examples, source/drain epitaxial (epi) layers of adjacent active regions are disposed on either side of the GAA dummy structure (formed at the active edge), such that the adjacent source/drain epi layers are in contact with the inner spacers and plurality of channels of the GAA dummy structure.
In exemplary embodiments, an isolation layer is formed before the source/drain epitaxial (epi) layers are formed. As a result, each source/drain epi region is isolated from the underlying semiconductor material by respective portions of the isolation layer. With the isolation provided by the isolation layer, a vertically-extending isolation structure may be provided with a shallower depth to reduce parasitic capacitance while sufficiently reducing leakage current through the semiconductor material under the isolation structure.
Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, embodiments discussed herein include structures and related methods for performing a CPODE process.
In various embodiments, a GAA dummy structure may be formed at an active edge (e.g., at a boundary of adjacent active regions), as described above, with isolation layers and overlying source/drain epi layers of adjacent active regions disposed on either side of the GAA dummy structure.
For purposes of the discussion that follows,
As further shown in
Referring to
Method 1000 is described below with reference to
Further, the semiconductor device 200 may include various other devices and features, such as other types of devices such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random-access memory (SRAM) and/or other logic circuits, etc., but is simplified for a better understanding of the concepts of the present disclosure. In some embodiments, the semiconductor device 200 includes a plurality of semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., which may be interconnected. Moreover, it is noted that the process steps of method 1000, including any descriptions given with reference to the figures are merely exemplary and are not intended to be limiting beyond what is specifically recited in the claims that follow.
At operation S1010, the method 1000 provides a substrate 202, as shown in
As shown in
In some embodiments, the epitaxial layer 214 has a thickness ranging from about 5 nm to about 15 nm. The epitaxial layers 214 may be substantially uniform in thickness. In some embodiments, the epitaxial layer 216 has a thickness ranging from about 5 nm to about 15 nm. In some embodiments, the epitaxial layers 216 of the stack are substantially uniform in thickness. As described in more detail below, the epitaxial layer 216 may serve as channel region(s) for a subsequently formed multi-gate device and has a thickness chosen based on device performance considerations. The epitaxial layer 214 may serve to define a gap between adjacent channel region(s) for a subsequently formed multi-gate device and has a thickness chosen based on device performance considerations.
By way of example, epitaxial growth of the epitaxial stack 212 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers such as, the epitaxial layers 216 include the same material as the substrate 202. In some embodiments, the epitaxially grown layers 214 and 216 include a different material than the substrate 202. As stated above, in at least some examples, the epitaxial layer 214 includes an epitaxially grown Si1-xGex layer (wherein x is from about 10 to about 55%) and the epitaxial layer 216 includes an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the epitaxial layers 214 and 216 may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxial layers 214 and 216 may be chosen based on providing differing oxidation, etch selectivity properties. In various embodiments, the epitaxial layers 214 and 216 are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3 to about 1×1017 cm−3), where for example, no intentional doping is performed during the epitaxial growth process. In some embodiments, the bottom layer and the top layer of the epitaxial stack 212 are SiGe layers (not shown). In alternative embodiments, the bottom layer of the epitaxial stack 212 is a Si layer and the top layer of the epitaxial stack 212 is a SiGe layer (not shown).
As shown in
In various embodiments, each fin 220 includes an upper portion of the interleaved epitaxial layers 214 and 216, and a bottom portion that is formed from the etched substrate 202. Each fin 220 protrudes upwardly in the z-direction from the substrate 202 and extends lengthwise in the y-direction. Sidewalls of each fin 220 may be straight or inclined (not shown). In
As shown in
As shown in
The sacrificial gate structures 222 are formed by first blanket depositing a sacrificial gate dielectric layer over the fin(s) 220. A sacrificial gate electrode layer is then blanket deposited on the sacrificial gate dielectric layer and over the fin(s) 220. The sacrificial gate dielectric layer includes silicon oxide, silicon nitride, or a combination thereof. The thickness of the sacrificial gate electrode layer is in a range from about 100 nm to about 200 nm in some embodiments. The sacrificial gate electrode layer 224 includes silicon such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate dielectric layer is in a range from about 1 nm to about 5 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable process. A mask layer 225 is formed over the sacrificial gate electrode layer. The mask layer 225 may include a mask layer 226 such as silicon oxide and a mask layer 227 such as silicon nitride. Subsequently, a patterning operation is performed on the mask layer 225, the sacrificial gate electrode layers and the sacrificial gate dielectric layer are patterned into the sacrificial gate structures 222, including sacrificial gate dielectric layer 223 and sacrificial gate electrode 224.
As shown, the fin 220 is partially exposed between and on opposite sides of the sacrificial gate structures 222, thereby defining source/drain (S/D) regions. In this disclosure, a source and a drain are interchangeably used and the structures thereof are substantially the same.
Still referring to
By way of example, the spacers 230 may be formed by depositing spacer material including a liner material layer and a dielectric material layer over the sacrificial gate structure 222 using processes such as a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process respectively.
As shown in
Cross-referencing
As shown most clearly in
As further shown in
As shown in
Referring to
As shown, the isolation layer 300 may completely cover the bottom gap surface 233 such that no portion of the semiconductor substrate 202 between the bottom inner spacers 2162 is uncovered. Thus, each portion of the isolation layer 300 extends from one gate structure 222 to an adjacent gate structure 222.
In exemplary embodiments, the isolation layer 300 is a dielectric material with a large band gap. For example, the isolation layer 300 may be formed from a material with a band gap of at least 4 eV, such as at least 4.5 eV, at least 5 eV, at least 5.5 eV, at least 6 eV, at least 6.5 eV, at least 7 eV, at least 7.5 eV, at least 8 eV, at least 8.5 eV, or at least 8.9 eV.
In certain embodiments, the isolation layer 300 is formed from silicon nitride (SiN) and has a band gap of about 5 eV. In certain embodiments, the isolation layer 300 is formed from silicon oxide (SiO) and has a band gap of about 8.9 eV. In exemplary embodiments, the isolation layer 300 is formed from silicon oxide, silicon nitride, or a combination thereof.
In exemplary embodiments, the isolation layer includes a plurality of sublayers, such that the isolation layer is a multi-film structure. Such sublayers may be separately deposited. The thickness and order of sublayers within the multi-film structure may be designed to provide a desired band gap, a desired dielectrics constant, and to facilitate epitaxial growth of material for forming source/drain regions over the isolation layer as described below.
In exemplary embodiments, the isolation layer 300 has a small dielectrics constant (or relative permittivity). In exemplary embodiments, the isolation layer has a dielectric constant of less than 10, such as less than 7.5, less than 5, or less than 4.
In exemplary embodiments, the upper surface 301 of the isolation layer 300 is located at a height H1 over the trough or lowest point of the bottom surface 233 of the semiconductor substrate 202. In certain embodiments, the isolation layer 300 may have a vertical thickness, in the z-direction, equal to the height H1.
In exemplary embodiments, height H1 is less than 10 nanometers, such as less than 9 nm, less than 8 nm, less than 7 nm, less than 6 nm, less than 5 nm, or less than 4 nm. Height H1 may be at least 3 nm, such as at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, or at least 9 nm.
As shown, the lowest or bottom epitaxial layer 2141 of the first composition has an uppermost or top surface 302 located at a height H2 over the trough or lowest point of the bottom surface 233 of the semiconductor substrate 202. In exemplary embodiments, the height H1 of the top surface 301 of the isolation layer 300 is less than the height H2 of the top surface 302 of the bottom epitaxial layer 2141.
While
Similar to the embodiment of
Whether forming the inner spacers 2162 and isolation layer 300 with two different deposition processes or simultaneously, the method may continue, at operation S1110, with forming source/drain regions 400, as shown in
The epitaxial material may include one or more layers of Si, SiP, SiC and SiCP for an n-channel FET or Si, SiGe, Ge for a p-channel FET. For the P-channel FET, boron (B) may also be contained in the source/drain. The source/drain epitaxial layers may be formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE).
In
As further shown in
As shown in
In
In
In exemplary embodiments, the replacement metal gate process includes forming a gate dielectric layer 540 in the gate cavities 499 and in the gaps 2169, and forming a gate electrode material 550 over the gate dielectric layer 540 to fill the gate cavities 499 and fill the gaps 2169.
An exemplary gate dielectric layer(s) 540 is deposited conformally in the gate cavities 499 and gaps 2169. The gate dielectric 540 may be formed on the semiconductor nanosheets 560, and the gate electrode material 550 may be formed on the gate dielectric layer(s) 540. Thus, each semiconductor nanosheet 560 is wrapped in gate dielectric 540 and surrounded by gate electrode material 550.
In accordance with some embodiments, the gate dielectric layer(s) 540 comprises silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectric layer(s) 540 is a high-k dielectric material, and in these embodiments, the gate dielectric layer(s) 540 may have a k value greater than about 7.0, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation methods of the gate dielectric layer(s) 540 may include Molecular-Beam Deposition (MBD), ALD, PECVD, and the like.
The gate electrode material 550 is deposited over the gate dielectric layer(s) 540 and fills the remaining portion of the gate cavity. The gate electrode material 550 may be a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multi-layers thereof. For example, although a single gate electrode material is illustrated, any number of work function tuning layers may be deposited.
As shown, the
After completing the replacement metal gate process, method 1000 may continue with forming an isolation structure to isolate adjacent devices.
For example, in
Thereafter, method 1000 includes, at operation S1180, performing a selective etch process to remove the selected gate structure 502, as shown in
The etching process may include an initial selective deposition of a liner (not shown) over the hard mask 600. For example, a CH4 deposition process may be performed to selectively deposit the liner on the hard mask 600.
An exemplary etching process may be performed by any highly directional etch processes that selectively etch silicon over silicon oxide or silicon nitride.
The exemplary etching process includes Si etch steps with highly selective etchants, such as HBr based plasma, which can efficiently remove Si with minor damage to the inner spacer, which may be consist of silicon, carbon, nitrogen, and oxygen. The etch rates and selectivity can be tuned by adding O2 or CO2 into the HBr plasma. During the etching processes, sidewall passivation steps may be used to preserve the CD of trenches without being broadening by the Si etch steps. For example, sidewall passivation steps utilizing SiCl4, HBr, and O2 precursors may be used to form sidewall oxide for this purpose. Furthermore, to avoid having the etch stopped by etch by-product or oxide passivation layers, break-through steps utilizing low selective etchants, such as CF4, may be used to remove them.
As shown in
In exemplary embodiments, a refill process is used to form an isolation material 800 over the structure 200. An exemplary material 800 is silicon nitride. The material 800 fills the previously formed trenches 700 and electrically isolates the now adjacent gate structures 501 and 503 from one another. In some embodiments, the material 800 includes SiN. Alternatively, in some cases, the material 800 may include SiO2, silicon oxynitride, FSG, a low-k dielectric, combinations thereof, and/or other suitable materials known in the art. In various examples, the material 800 may be deposited by a CVD process, an SACVD process, a flowable CVD process, an ALD process, a PVD process, and/or other suitable process. In some cases, after depositing the material 800, a chemical mechanical polishing (CMP) process may be performed to remove excess material 810 and planarize a top surface of the device 200.
Method 1000 may continue at operation S1200 where further processing may be performed. Generally, the further processing may form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) over the substrate 202, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after method 1000, and some process steps described above may be replaced or eliminated in accordance with various embodiments of method 1000.
As shown, the gate structure 503 is formed with three semiconductor nanosheets 560, a bottom or lowest nanosheet 561, a middle nanosheet 562, and a top or uppermost nanosheet 563. Accordingly, the gate structure 503 includes gate portions 570 that lie under the nanosheets 561, 562, and 563, respectively, where the removed layers 214 (
As shown, the lowest gate portion 571 has an upper surface 581 located at a vertical height H3 over the uppermost surface 201 of the semiconductor substrate 202. Further, the upper surface 581 of the lowest gate portion 571 is located at a height H2 over the bottom surface 233 of the isolation layer 300. Further, the isolation layer 300 has a top surface 301 at a height H1 over the bottom surface 233. As shown height H1 is less than the vertical height H2 of the upper surface 581 of the lowest gate portion 571. Providing the upper surface 581 of the lowest gate portion 571 at a greater height than the top surface 301 of the isolation layer 300 avoids impacting the electrical conductance of the epi.
As shown, the uppermost nanosheet 563 has an upper surface 583 defining a plane 590 and located at a vertical height H4 over the uppermost surface 201 of the semiconductor substrate 202. In exemplary embodiments, the vertical height H4 is from 42 nm to 46 nm, such as from 43.4 nm to 44.9 nm, with an average of 44.2 nm.
As shown, the upper surface 583 of the uppermost nanosheet 563 and plane 590 is located at a vertical height H5 over the upper surface 301 of the isolation layer 300. In exemplary embodiments, the vertical height H5 is from 38 nm to 43 nm, such as from 39.3 nm to 41.3 nm, with an average of 40.3 nm.
In
In exemplary embodiments, vertical height H4 is greater than vertical height H6. For example, vertical height H6 may be less than 95% of vertical height H4, such as less than 90% of vertical height H4, less than 85% of vertical height H4, less than 80% of vertical height H4, less than 75% of vertical height H4, less than 70% of vertical height H4, less than 65% of vertical height H4, less than 60% of vertical height H4, less than 55% of vertical height H4, or less than 50% of vertical height H4.
Further, the upper surface 583 of the uppermost nanosheet 563 is located at a vertical height H7 over the nadir 820. The vertical height H7 may be considered to be the depth of the trench 700 as measured from the upper surface 583 of the uppermost nanosheet 563.
In exemplary embodiments, the vertical height H7 may be at least 60 nanometers (nm), such as at least 62 nm, at least 64 nm, at least 66 nm, at least 68 nm, at least 70 nm, at least 71 nm, at least 72 nm, at least 74 nm, at least 76 nm, at least 78 nm, at least 80 nm, at least 82 nm, at least 84 nm, or at least 86 nm.
In exemplary embodiments, the vertical height H7 may be no more than 120 nanometers (nm), such as no more than 110 nm, no more than 100 nm, no more than 90 nm, such as no more than 88 nm, no more than 86 nm, no more than 84 nm, no more than 82 nm, no more than 80 nm, no more than 78 nm, no more than 76 nm, no more than 74 nm, no more than 72 nm, or no more than 70 nm.
As shown in
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As shown in
Cross-referencing
In certain embodiments, the ratio of H4:GW may be at least 2:1, at least 2.1:1, at least 2.2:1, at least 2.3:1, at least 2.4:1, at least 2.5:1, at least 2.6:1, at least 2.7:1, at least 2.8:1, at least 2.9:1, at least 3.1:1, at least 3.2:1, at least 3.3:1, at least 3.4:1, at least 3.5:1, at least 3.6:1, at least 3.7:1, at least 3.8:1, at least 3.9:1, or at least 4:1. In certain embodiments, the ratio of H4:GW may be at most 2:1, at most 2.1:1, at most 2.2:1, at most 2.3:1, at most 2.4:1, at most 2.5:1, at most 2.6:1, at most 2.7:1, at most 2.8:1, at most 2.9:1, at most 3.1:1, at most 3.2:1, at most 3.3:1, at most 3.4:1, at most 3.5:1, at most 3.6:1, at most 3.7:1, at most 3.8:1, at most 3.9:1, or at most 4:1.
Referring back to
Also, the trench 700 and isolation structure 800 are formed with a lateral width W6 in the Y-direction at a plane defined by the middle nanosheet 562. In exemplary embodiments, the lateral width W6 is from 16 nm to 19 nm, such as from 16.6 nm to 18.3 nm, with an average of 17.5 nm.
Moreover, the trench 700 and isolation structure 800 are formed with a lateral width W7 in the Y-direction at a plane defined by the uppermost nanosheet 563. In exemplary embodiments, the lateral width W7 is from 19 nm to 22 nm, such as from 19.1 nm to 21.5 nm, with an average of 20.2 nm.
Cross-referencing
As shown in
As shown in
In exemplary embodiments, the width W8 of the isolation structure 800 at the uppermost surface 201 of the semiconductor substrate 202 is less than the length L2.
Referring to
Parasitic capacitance C is calculated with the equation C=εεoA/d, where ε is the relative permittivity of the material, εo is the relative permittivity of a vacuum or free space, A is the area of the layer of material, and d is the thickness of the layer of material. Thus, given a same area A, reducing ε and increasing d will result in a reduced parasitic capacitance. As may be understood, selecting thicknesses and materials of certain relative permittivity may allow for tuning the parasitic capacitance of each sublayer, and of the isolation layer 300 as a whole.
While
For example, referring to
As shown in
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As shown in
In
In exemplary embodiments, height H9 is less than 10 nanometers, such as less than 9 nm, less than 8 nm, less than 7 nm, less than 6 nm, less than 5 nm, or less than 4 nm. Height H9 may be at least 3 nm, such as at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, or at least 9 nm.
As shown, the lowest or bottom epitaxial layer 2141 of the first composition has an uppermost or top surface 302 located at a height H10 over the epitaxial material 401. In exemplary embodiments, the height H9 of the top surface 301 of the isolation layer 300 is less than the height H10 of the top surface 302 of the bottom epitaxial layer 2141.
Processing of the structure of
Through the combination of the laterally-extending (in the Y-direction) isolation layer 300 and the vertically-extending (in the Z-direction) isolation structure 800, devices 200 are provided with reduced parasitic capacitance while still preventing or reducing leakage current under the isolation structure 800 between adjacent active areas. Specifically, the isolation structure 800 may be formed in a shallower trench, resulting in a small parasitic capacitance, and the isolation layer 300 may prevent or reduce leakage current between source/drain regions.
By employing the disclosed process, a process window may be enlarged and device performance and reliability of transistors formed in the adjacent active regions will be enhanced. Those of skill in the art will readily appreciate that the methods and structures described herein may be applied to a variety of other semiconductor devices to advantageously achieve similar benefits from such other devices without departing from the scope of the present disclosure.
Thus, one of the embodiments of the present disclosure describes a method including forming an isolation layer over a semiconductor material; forming source/drain regions over the isolation layer; removing a selected gate structure, wherein removing the selected gate structure forms a trench in the semiconductor material; and forming an isolation structure in the trench.
In certain embodiments of the method, after removing the selected gate structure, a non-selected gate structure remains over the semiconductor material; the non-selected gate structure comprises a stack of vertically spaced-apart nanosheets including a bottom nanosheet having a top surface at a first height over the semiconductor material; the isolation layer has a top surface at a second height over the semiconductor material; and the first height is greater than the second height.
In certain embodiments of the method, after removing the selected gate structure, a non-selected gate structure remains over the semiconductor material; the non-selected gate structure comprises a stack of vertically spaced-apart nanosheets including a top nanosheet having a top surface; the trench has a nadir; the top surface is distanced from the nadir by a vertical distance H; the trench has a width W; and the ratio of H to W is at least 2:1 and at most 5:1.
In certain embodiments of the method, the isolation layer comprises silicon oxide, silicon nitride, or a combination thereof.
In certain embodiments of the method, the isolation layer comprises a plurality of sublayers.
In certain embodiments of the method, the isolation layer has a vertical thickness of less than 6 nanometers (nm).
In certain embodiments of the method, the isolation layer has a band gap of at least 4 eV.
In certain embodiments of the method, the isolation layer has a dielectric constant of less than 7.5.
In certain embodiments of the method, the isolation structure is laterally distanced from a nearest adjacent gate structure by a distance of from 22 to 34 nanometers (nm).
In another embodiment, a semiconductor device is provided and includes a multi-gate structure over a semiconductor substrate; an isolation structure laterally distanced from the multi-gate structure, wherein the isolation structure is located in a trench in the semiconductor substrate; and an isolation layer overlying the semiconductor substrate and extending from the multi-gate structure to the isolation structure.
In exemplary embodiments of the semiconductor device, the multi-gate structure comprises a stack of spaced-apart nanosheets including a bottom nanosheet; the bottom nanosheet has a top surface at a first height over the semiconductor material; the isolation layer has a top surface at a second height over the semiconductor material; and the first height is greater than the second height.
In exemplary embodiments of the semiconductor device, the multi-gate structure comprises a stack of spaced-apart nanosheets including a top nanosheet; the top nanosheet has a top surface at a first height over the semiconductor material; the trench has a nadir; and a vertical distance from the top surface to the nadir is less than 120 nanometers (nm).
In exemplary embodiments of the semiconductor device, the multi-gate structure comprises a stack of spaced-apart nanosheets including a top nanosheet; the top nanosheet has a top surface at a first vertical distance from an upper surface of the semiconductor material; the trench has a nadir, wherein the upper surface of the semiconductor material is located at a second vertical distance from the nadir; the first vertical distance is greater than the second vertical distance.
In exemplary embodiments of the semiconductor device, the semiconductor device includes a source/drain region overlying the isolation layer, the trench has a nadir; the top surface is located at a first vertical distance from the nadir; the source/drain region has a bottom-most surface and an uppermost surface, wherein the uppermost surface is located at a second vertical distance from the bottom-most surface; and the first vertical distance is less than the second vertical distance.
In exemplary embodiments of the semiconductor device, the isolation layer has a vertical thickness of less than 6 nanometers (nm), and the isolation structure is laterally distanced from the multi-gate structure by a distance of from 22 to 34 nanometers (nm).
In another embodiment, a semiconductor device includes a first gate structure and a second gate structure located over a semiconductor material; an isolation structure located between the first gate structure and the second gate structure; a first source/drain region located between the first gate structure and the isolation structure, wherein the first source/drain region is separated from the semiconductor material by a first isolation layer; and a second source/drain region located between the second gate structure and the isolation structure, wherein the second source/drain region is separated from the semiconductor material by a second isolation layer.
In exemplary embodiments of the semiconductor device, the first isolation layer and the second isolation layer comprise a plurality of sublayers, and the first isolation layer and the second isolation layer comprise silicon oxide, silicon nitride, or a combination thereof.
In exemplary embodiments of the semiconductor device, the first isolation layer and the second isolation layer each has a vertical thickness of less than 6 nanometers (nm).
In exemplary embodiments of the semiconductor device, each gate structure contacts the semiconductor material along an interface plane; each gate structure has an uppermost surface located at a first vertical distance over the interface plane; the isolation structure has a nadir; the interface plane is located at a second vertical distance over the nadir; and the first vertical distance is greater than the second vertical distance.
In exemplary embodiments of the semiconductor device, each gate structure contacts the semiconductor material along an interface plane; at the interface plane, each gate structure is distanced from the isolation structure by a lateral distance; at the interface plane, the isolation structure has a lateral width; and the lateral distance is greater than the lateral width.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present.
