This application claims the priority to Chinese patent application No. CN 202111010037.9, filed on Aug. 31, 2021, and entitled “ISOLATION TRENCH STRUCTURE OF BACKSIDE ILLUMINATED CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME”, the disclosure of which is incorporated herein by reference in entirety.
The present application relates to the field of semiconductor integrated circuit manufacturing, in particular, to an isolation trench structure of a backside illuminated (BSI) CMOS image sensor (CIS). The present application also relates to a method for manufacturing an isolation trench structure of the backside illuminated CMOS image sensor.
The existing CMOS image sensor includes a pixel cell circuit and a CMOS circuit. The pixel cell circuit is located in a pixel area, and the CMOS circuit is a logic circuit located in a logic circuit area. Compared with the CCD image sensor, the CMOS image sensor may have a higher integration degree from the CMOS standard manufacturing process, can be integrated with other digital-analog operation and control circuits on the same chip, and thus is more applicable to many applications.
According to the number of transistors included in the pixel cell circuit of the existing CMOS image sensor, the existing CMOS image sensors are mainly classified into 3T-type structures and 4T-type structures.
An N-type area of the photodiode D1 is connected to the source of the reset transistor M1.
The gate of the reset transistor M1 is connected to a reset signal Reset, and the reset signal Reset is a voltage pulse. When the reset signal Reset is at a high level, the reset transistor M1 is turned on and absorbs electrons of the photodiode D1 into the power supply Vdd of the readout circuit, so as to achieve reset. When irradiated by light, the photodiode D1 generates photo-generated electrons, the voltage increases, and an electrical signal is transmitted via an amplification circuit M2. The gate of the selection transistor M3 is connected to a row selection signal Rs, so as to select an amplified electrical signal for outputting, i.e., an output signal Vout.
The CMOS image sensors are classified as frontside illuminated (FSI) CMOS image sensors and backside illuminated CMOS image sensors according to their different light entering paths.
The light entering path in the frontside illuminated CMOS image sensor passes through a plurality of metal interconnection layers. Since the metal layers are opaque, the incident light is blocked or reflected in the metal layers, so that the amount of incident light that actually enters the photodiode is significantly reduced.
In the backside illuminated CMOS image sensor, a color filter and a microlens are directly formed on the backside of the photodiode. Since the metal interconnection layer is located on the frontside of a semiconductor substrate, the light entering path does not pass through the metal interconnection layers, and the amount of incident light that actually enters the photodiode is not reduced much.
With continuous shrinking of the process node of semiconductor integrated circuit manufacturing technologies, the device sizes keep on decreasing continuously, and dimensions of a pixel cell of the BSI CIS, including the longitudinal dimension and the lateral dimension, have also been shrinking. The reduction of the lateral dimension is prone to causing crosstalk between adjacent pixel cells. In addition to the crosstalk, the reduction of the longitudinal dimension shortens the absorption path of the infrared light, thereby reducing the quantum efficiency (QE) of red light.
The present application provides an isolation trench structure in a backside illuminated CMOS image sensor, which can improve the quantum efficiency of red light, thereby facilitating the reduction of the CIS device size. The present application also provides a method for manufacturing an isolation trench structure of a backside illuminated CMOS image sensor.
The present application provides an isolation trench structure of a backside illuminated CMOS image sensor. The backside illuminated CMOS image sensor is formed on a semiconductor substrate, a plurality of pixel cells are formed in a pixel area of the backside illuminated CMOS image sensor, and each of the pixel cells is respectively formed in an active area.
Each of the pixel cells includes a photodiode and a cell isolation trench structure; and the cell isolation trench structure is a part of the isolation trench structure.
A first cell trench combination structure formed by more than five first cell trenches is formed in each of the active areas, the cell isolation trench structure is formed in the first cell trench of the first cell trench combination structure, and the first cell trench is formed by etching the backside of the semiconductor substrate.
The photodiode is a longitudinal stack structure having an N-type area and a P-type area formed in the active area.
The first cell trench extends longitudinally through the N-type area of the photodiode or is located in the N-type area of the photodiode.
In a plan view, first ends of all the first cell trenches in the first cell trench combination structure converge toward the center of the active area, second ends of all the first cell trenches diverge from each other toward the edge of the active area, and two adjacent first cell trenches have an included angle.
An outline of the first cell trench combination structure is formed by connecting the second ends of the first cell trenches, and the active area within the outline of the first cell trench combination structure is divided into a plurality of active area subblocks by the first cell trenches; a light travel distance in the active area subblock is increased under a reflection action of a material layer of the cell isolation trench structure in the first cell trench on two sides of the active area subblock, and a total increase amount of the light travel distance in the active area is the sum of increase amounts of the light travel distances in all the active area subblocks.
In one example, the semiconductor substrate includes a silicon substrate.
In one example, the isolation trench structure further includes a deep trench isolation structure formed between the active areas of all the pixel cells, the deep trench isolation structure is formed in a second intercell trench, and the second intercell trench is formed by etching the backside of the semiconductor substrate.
In one example, the material of the cell isolation trench structure includes an oxide layer, a nitride layer, or a high dielectric constant layer.
In one example, the material of the deep trench isolation structure includes an oxide layer, a nitride layer, or a high dielectric constant layer.
In one example, the semiconductor substrate is P-type doped, an N-type epitaxial layer is formed on the frontside of the semiconductor substrate, the N-type area of the photodiode includes the N-type epitaxial layer of a formation area of the photodiode, and the N-type area of the photodiode includes the semiconductor substrate of the formation area of the photodiode.
In one example, the pixel cell further includes a CMOS pixel reading circuit, the CMOS pixel reading circuit being used to read photo-generated electrons of the photodiode; and
a color filter and a microlens are formed on the backside of the pixel cell.
In one example, the depth of the second intercell trench is greater than the depth of the first cell trench.
In one example, the included angles between the first cell trenches in the first cell trench combination structure are equal.
In order to solve the above technical problems, the present application provides a method for manufacturing an isolation trench structure of a backside illuminated CMOS image sensor, including the following steps:
step 1, forming a frontside structure of the backside illuminated CMOS image sensor on a semiconductor substrate, wherein in the frontside structure of the backside illuminated CMOS image sensor, the backside illuminated CMOS image sensor includes a plurality of pixel cells located in a pixel area, each of the pixel cells is respectively formed in an active area, each of the pixel cells includes a photodiode, and the photodiode is a longitudinal stack structure composed of an N-type area and a P-type area formed in the active area;
step 2, forming a first photoresist pattern on the backside of the semiconductor substrate;
step 3, etching the backside of the semiconductor substrate under the definition of the first photoresist pattern to form a first cell trench,
wherein more than five first cell trenches are formed in each of the active areas, and all of the first cell trenches form a first cell trench combination structure;
the first cell trench extends longitudinally through the N-type area of the photodiode or is located in the N-type area of the photodiode;
in a plan view, first ends of all the first cell trenches in the first cell trench combination structure converge toward the center of the active area, second ends of all the first cell trenches diverge from each other toward the edge of the active area, and two adjacent first cell trenches have an included angle;
an outline of the first cell trench combination structure is formed by connecting the second ends of the first cell trenches, and the active area within the outline of the first cell trench combination structure is divided into a plurality of active area subblocks by the first cell trenches; and
step 4: performing material filling in each of the first cell trenches of the first cell trench combination structure to form a cell isolation trench structure, wherein the cell isolation trench structure is a part of the isolation trench structure;
a light travel length (distance) in the active area subblock is increased under a reflection action of a material layer of the cell isolation trench structure in the first cell trench on two sides of the active area subblock, and a total increase amount of the light travel distance in the active area is the sum of increase amounts of the light travel distances in all the active area subblocks.
In one example, the semiconductor substrate includes a silicon substrate.
In one example, the isolation trench structure further includes a deep trench isolation structure formed between all the pixel cells; and forming the deep trench isolation structure includes sub-steps of:
forming a second photoresist pattern on the backside of the semiconductor substrate;
etching the frontside of the semiconductor substrate under the definition of the second photoresist pattern to form a second intercell trench; and
performing material filling in the second intercell trench to form the deep trench isolation structure.
In one example, the material of the cell isolation trench structure includes an oxide layer, a nitride layer, or a high dielectric constant layer.
In one example, the material of the deep trench isolation structure includes an oxide layer, a nitride layer, or a high dielectric constant layer.
In one example, the semiconductor substrate is P-type doped, an N-type epitaxial layer is formed on the frontside of the semiconductor substrate, the N-type area of the photodiode includes the N-type epitaxial layer of a formation area of the photodiode, and the N-type area of the photodiode includes the semiconductor substrate of the formation area of the photodiode.
In one example, the depth of the second intercell trench is greater than the depth of the first cell trench.
In one example, the included angles between the first cell trenches in the first cell trench combination structure are equal.
The present application provides a particular configuration for a top view structure of the first cell trench combination structure of the cell isolation trench structure formed in the pixel cell. i.e., a configuration where the first ends of all the first cell trenches in the first cell trench combination structure converge toward the center of the active area and the second ends diverge from each other toward the edge of the active area. Such the structure facilitates the division into the plurality of active area subblocks, and facilitates the configuration of the number of the active area subblocks as needed. For example, the number of the active area subblocks can be increased by increasing the number of the first cell trenches and reducing the included angle between the first cell trenches. The material layer of the cell isolation trench structure in the first cell trench on two sides of each active area subblock forms an optical reflection surface, facilitating the propagation of light from the backside of each active area subblock to the inside and thereby increasing the light travel distance By increasing the number of the active area subblocks, the total increase amount of the light travel distance in the active area can be increased, eventually improving the quantum efficiency of red light and thereby facilitating the decrease of the device size.
Based on the configuration of the deep trench isolation structure arranged between the pixel cells, the crosstalk between the pixel cells will meet the device requirements.
The present application is described in detail below with reference to the drawings and specific implementations:
An isolation trench structure of a backside illuminated CMOS image sensor in the embodiment of the present application is obtained on the basis of analyzing the defects of an existing isolation trench structure of a backside illuminated CMOS image sensor. Therefore, before the introduction of the isolation trench structure of a backside illuminated CMOS image sensor in the embodiment of the present application in detail, the existing three types of an isolation trench structure of a backside illuminated CMOS image sensor are introduced first and analyzed accordingly:
The First Kind of Existing Backside Illuminated CMOS Image Sensor
A metal interconnection layer 103 is formed on the frontside of the semiconductor substrate 101. A color filter 104 and a microlens 105 are formed on the backside of the semiconductor substrate 101. Moreover, in some areas of the backside illuminated CMOS image sensor where light collection is not required, a light blocking layer 106 needs to be formed in these areas.
Since the first kind of existing backside illuminated CMOS image sensor does not adopt a deep trench isolation (DTI) structure, incident light 107 easily enters the adjacent pixel cell, thereby causing relatively large crosstalk. The incident light 107 shown in
The Second Kind of Existing Backside Illuminated CMOS Image Sensor
The second kind of existing backside illuminated CMOS image sensor differs from the first kind of existing backside illuminated CMOS image sensor in that the DTI 208 is provided between active areas corresponding to the pixel cells. The DTI 208 can reduce crosstalk of incident light 207 between different pixel cells.
The Third Kind of Existing Backside Illuminated CMOS Image Sensor
The third kind of existing backside illuminated CMOS image sensor differs from the second kind of existing backside illuminated CMOS image sensor in that CDTI 309 is provided in the active area corresponding to the pixel cell.
In the range of the active area subblock 301a corresponding to
In addition, the bright area corresponding to the mark 702a is obviously larger the bright area corresponding to the mark 602a, that is, the crosstalk is increased after the CDTI 309 is introduced. As shown by the dashed line circle 307a in
Isolation trench structure of a backside illuminated CMOS image sensor in the embodiment of the present application:
Each of the pixel cells includes a photodiode (not shown in these cross sectional figures) and a cell isolation trench structure 407; and the cell isolation trench structure 407 is a part of the isolation trench structure.
A first cell trench combination structure formed by more than five first cell trenches 409 is formed in each of the active areas, the cell isolation trench structure 407 is formed in the first cell trench 409 of the first cell trench combination structure, and the first cell trench 409 is formed by etching the backside of the semiconductor substrate 401.
The photodiode is a longitudinal stack (perpendicular to the substrate) structure composed of an N-type area and a P-type area formed in the active area.
The first cell trench 409 extends longitudinally (vertically in the cross sectional view) through the N-type area of the photodiode or is located in the N-type area of the photodiode.
In a plan view, first ends of all the first cell trenches in the first cell trench 409 combination structure converge toward the center of the active area, second ends of all the first cell trenches 409 diverge from each other toward the edge of the active area, and two adjacent first cell trenches 409 have an included angle. In the embodiment of the present application, the included angles between the first cell trenches 409 in the first cell trench combination structure are equal. Eight first cell trenches 409 with the first ends thereof connected together are shown in
A dashed outline 409a of the first cell trench combination structure is formed by connecting the second ends of the first cell trenches 409, and the active area within the outline 409a of the first cell trench combination structure is divided into a plurality of active area subblocks 401a by the first cell trenches409. light travel distance in the active area subblock 401a is increased under a reflection action of a material layer of the cell isolation trench structure 407 in the first cell trench 409 on two sides of the active area subblock 401a, and a total increase amount of the light travel distance in the active area is the sum of increase amounts of the light travel lengths in all the active area subblocks 401a.
The semiconductor substrate 401 includes a silicon substrate.
The isolation trench structure further includes a deep trench isolation structure 408 formed between the active areas of all the pixel cells, the deep trench isolation structure 408 is formed in a second intercell trench 410, and the second intercell trench 410 is formed by etching the backside of the semiconductor substrate 401.
The material of the cell isolation trench structure 407 includes an oxide layer, a nitride layer, or a high dielectric constant layer.
The material of the deep trench isolation structure 408 includes an oxide layer, a nitride layer, or a high dielectric constant layer.
The semiconductor substrate 401 is P-type doped, an N-type epitaxial layer is formed on the frontside of the semiconductor substrate 401, the N-type area of the photodiode includes the N-type epitaxial layer in a formation area of the photodiode, and the N-type area of the photodiode includes the semiconductor substrate 401 of the formation area of the photodiode.
The pixel cell further includes a CMOS pixel reading circuit (not shown), and the CMOS pixel reading circuit is used to read photo-generated electrons of the photodiode.
The depth of the second intercell trench 408 is greater than the depth of the first cell trench 409. The backside of the deep trench isolation structure 408 is flush with the backside of the cell isolation trench structure 407, and the top surface of the deep trench isolation structure 408 is higher than the top surface of the cell isolation trench structure 407.
A color filter 404 and a microlens 405 are formed on the backside of the pixel cell. Moreover, a light blocking layer 406 is formed in some areas of the backside illuminated CMOS image sensor where light collection is not required.
A metal interconnection layer 403 is formed on the frontside of the semiconductor substrate 401.
Referring to
The present application provides a particular configuration for a top view structure of the first cell trench 409 combination structure of the cell isolation trench structure 407 formed in the pixel cell. i.e., a configuration where the first ends of all the first cell trenches 409 in the first cell trench 409 combination structure converge toward the center of the active area and the second ends diverge from each other toward the edge of the active area. Such the structure facilitates the division into the plurality of active area subblocks, and facilitates the configuration of the number of the active area subblocks as needed. For example, the number of the active area subblocks can be increased by increasing the number of the first cell trenches 409 and reducing the included angle between the first cell trenches 409. The material layer of the cell isolation trench structure 407 in the first cell trench 409 on two sides of each active area subblock forms an optical reflection surface, facilitating the propagation of light from the backside of each active area subblock to the inside and thereby increasing the light travel length. By increasing the number of the active area subblocks, the total increase amount of the light travel distance in the active area can be increased, eventually improving the quantum efficiency of red light and thereby facilitating the decrease of the device size.
Because the configuration of the deep trench isolation structure 408 is arranged between the pixel cells, the crosstalk between the pixel cells can satisfy the requirements.
Method for manufacturing an isolation trench structure of a backside illuminated CMOS image sensor in the embodiment of the present application:
The method for manufacturing an isolation trench structure of a backside illuminated CMOS image sensor in the embodiment of the present application includes the following steps.
Step 1. A frontside structure of the backside illuminated CMOS image sensor is formed on a semiconductor substrate 401, wherein in the frontside structure of the backside illuminated CMOS image sensor, the backside illuminated CMOS image sensor includes a plurality of pixel cells located in a pixel area, each of the pixel cells is respectively formed in an active area, each of the pixel cells includes a photodiode, and the photodiode is a longitudinal stack structure composed of an N-type area and a P-type area formed in the active area.
In the embodiment of the present application, the semiconductor substrate 401 includes a silicon substrate.
The pixel cell further includes a CMOS pixel reading circuit, and the CMOS pixel reading circuit is used to read photo-generated electrons of the photodiode.
Step 2. A first photoresist pattern is formed on the backside of the semiconductor substrate 401, wherein the first photoresist pattern is defined by means of a photomask.
Step 3. The backside of the semiconductor substrate 401 is etched under the definition of the first photoresist pattern to form a first cell trench 409.
More than five first cell trenches 409 are formed in each of the active areas, and all of the first cell trenches 409 form a first cell trench combination structure.
The first cell trench 409 extends longitudinally through the N-type area of the photodiode or is located in the N-type area of the photodiode.
In a plan view, first ends of all the first cell trenches 409 in the first cell trench combination structure converge toward the center of the active area, second ends of all the first cell trenches 409 diverge from each other toward the edge of the active area, and two adjacent first cell trenches 409 have an included angle. In method of the embodiment of the present application, the included angles between the first cell trenches 409 in the first cell trench combination structure are equal. In a method of other embodiments, the included angles between the first cell trenches 409 in the first cell trench combination structure can be unequal.
An outline 409a of the first cell trench combination structure is formed by connecting the second ends of the first cell trenches 409, and the active area within the outline 409a of the first cell trench combination structure is divided into a plurality of active area subblocks 401a by the first cell trenches 409.
Step 4. Material filling is performed in each of the first cell trenches 409 of the first cell trench combination structure to form a cell isolation trench structure 407, wherein the cell isolation trench structure 407 is a part of the isolation trench structure.
The material of the cell isolation trench structure 407 includes an oxide layer, a nitride layer, or a high dielectric constant layer.
A light travel length in the active area subblock 401a is increased by the reflection from a material layer of the cell isolation trench structure 407 in the first cell trench 409 on two sides of the active area subblock 401a, and a total increase amount of the light travel length in the active area is the sum of increase amounts of the light travel lengths in all the active area subblocks 401a.
The isolation trench structure further includes a deep trench isolation structure 408 formed between all the pixel cells, and the deep trench isolation structure 408 belongs to the backside structure of the backside illuminated CMOS image sensor. Forming the deep trench isolation structure 408 includes the following sub-steps:
A second photoresist pattern on the backside of the semiconductor substrate 401.
The frontside of the semiconductor substrate 401 is etched under the definition of the second photoresist pattern to form a second intercell trench 410. In the method of the embodiment of the present application, the depth of the second intercell trench 410 is greater than the depth of the first cell trench 409.
Material filling is performed in the second intercell trench 410 to form the deep trench isolation structure 408.
The material of the deep trench isolation structure 408 includes an oxide layer, a nitride layer, or a high dielectric constant layer.
The semiconductor substrate 401 is P-type doped, an N-type epitaxial layer is formed on the frontside of the semiconductor substrate 401, the N-type area of the photodiode includes the N-type epitaxial layer of a formation area of the photodiode, and the N-type area of the photodiode includes the semiconductor substrate 401 of the formation area of the photodiode.
In the method of the embodiment of the present application, the isolation trench structure includes the cell isolation trench structure 407 located in the pixel cell and the deep trench isolation structure 408 located between the pixel cells.
The method further includes the following backside process:
A color filter and a microlens are formed on the backside of the pixel cell.
The present application is described in detail above by using specific embodiments, which, however, are not intended to limit the present application. Without departing from the principles of the present application, those skilled in the art can also make many modifications and improvements, which should also be regarded as the scope of protection of the present application.
Number | Date | Country | Kind |
---|---|---|---|
202111010037.9 | Aug 2021 | CN | national |