The exemplary embodiments described herein relate generally to semiconductor device design and integrated circuit design, and more specifically, to a large surface VBPR for robust alignment in advanced technology nodes.
The examples described herein facilitate process integration, where aligning and landing of the BPR to VBPR is simplified, as the VBPR contact region is much larger due to the herein described structure. A larger cross section is provided (and a more easily engineered configuration) for the VBPR, which reduces contact resistance between the BPR and the VBPR.
In one aspect, a semiconductor device includes a contact comprising a first section and a second section; wherein the first section of the contact is located on a front side of a source or drain; wherein the second section extends from the front side of the source or drain to a backside of the source or drain; wherein the second section of the contact is comprised of a via and a connection area; wherein the via has a first width and the connection area has a second width, and wherein the second width is larger than the first width.
In another aspect, a method includes forming, within a wafer, a via etch into at least an isolation layer; removing a portion of the isolation layer next to the etch, to increase a connection area of a via to be larger than a transfer section of the via; filling the via etch with metal to form the via; filling the removed portion of the isolation layer with metal to form the connection area of the via; forming a backside power rail; and connecting the connection area of the via to the backside power rail.
In another aspect, a method of forming a semiconductor device includes forming, within a wafer, a contact etch into at least an isolation layer; forming a contact at least partially within the contact etch, the contact comprising a first section and a second section; forming the first section of the contact to be located on a front side of a source or drain; forming the second section of the contact to extend from the front side of the source or drain to a backside of the source or drain; forming the second section of the contact to comprise a via and a connection area; and forming the via to have a first width and the connection area to have a second width, wherein the second width is larger than the first width.
In another aspect, a semiconductor device includes a backside power rail; a source or drain; and a via to connect the source or drain to the backside power rail, the via comprising a transfer section having a first width and a connection area having a second width, the second width larger than the first width; wherein the connection area of the via is curved from at least a surface of the transfer section to a portion of the connection area that joins to the backside power rail, to vary the second width of the connection area towards the backside power rail.
The foregoing and other aspects of exemplary embodiments are made more evident in the following Detailed Description, when read in conjunction with the attached Drawing Figures, wherein:
The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. All of the embodiments described in this Detailed Description are exemplary embodiments provided to enable persons skilled in the art to make or use the invention and not to limit the scope of the invention which is defined by the claims.
Described herein is a semiconductor device comprising a contact that includes a first section and a second section, wherein the first section of the contact is located on a frontside of a source/drain, wherein the second section extends from the frontside of the source/drain to the backside of the source/drain, wherein the second section of the contact is comprised of a via and connection area, wherein the via has a first width and the connection area has a second width, and wherein the second width is larger than the first width.
In particular, described herein is a large surface VBPR for robust alignment in advanced technology nodes. In a first embodiment, the process flow includes forming a VBPR trench into an STI layer, partially removing the STI layer, and VBPR metallization. At the VBPR, part of the STI layer is replaced with the VBPR body. The cross-section area between the VBPR and the BPR is determined by a bottom area of the STI layer. The depth of the enlarged VBPR into the BPR is adjustable by varying the thickness of the STI being replaced.
There are several high value attributes and technical effects of the first embodiment and the examples described herein. For example, the herein described examples are easier for process integration, where aligning and landing of the BPR to VBPR is simplified, as the VBPR contact region is much larger due to the herein described structure. The herein described structure provides a larger cross section (and a more easily engineered configuration) for the VBPR, which reduces contact resistance between the BPR and the VBPR. Further, there is no liner inside the VBPR for current traveling from the BEOL metal layer to the BPR.
In
A main benefit of the final structure 1001 is the overlay 1008 between the VBPR 708 and the BPR 1006 can be more robust with an enlarged area. There is less resistance with greater cross-section 1012. Also, referring to item 1010, there is no liner between 708 VBPR and the BPR 1006, resulting in better conductance. Regarding item 1010, refer also to option 1 shown in
In a second embodiment, a process flow includes fabrication of a VBPR trench into an STI layer, partially removing the STI layer, and VBPR metallization. A dielectric liner is applied at the sidewall of the VBPR. At the VBPR, part of the STI is replaced with the VBPR body. The cross-section area between the VBPR and BPR is determined by the STI layer's bottom area. The depth of the enlarged VBPR into the BPR is adjustable by varying the thickness of the STI being replaced. In this embodiment, a method includes local partial replacement of the STI layer with VBPR material.
There are several high value attributes and technical effects of the second embodiment and the examples described herein. For example, process integration is easier, as there is easier alignment between the VBPR and the BPR. There is also less concern of shorting between the VBPR and immediate epi/CA. There is a larger cross-section for the VBPR, which is more easily engineered. The larger cross-section for the VBPR also reduces contact resistance between the BPR and the VBPR. Also, in this embodiment, there is no metal liner inside the VBPR for current traveling across the VBPR.
In
Compared to the first embodiment described with respect to
Similar to the benefit of the final structure 1001, a main benefit of the final structure 1801 is the overlay 1830 between the VBPR 1808 and the BPR 1806 can be more robust with an enlarged area. There is less resistance with greater cross-section 1840. Also, the interface between VBPR 1808 and BPR 1806 shows the absence of liner, which provides better conductance.
As also can be seen in
In a third embodiment, a process for fabricating a semiconductor device includes forming two STI layers, removing the first STI layer, and performing VBPR metallization. At the VBPR, part of the STI is replaced with a VBPR body. The cross-section area between the VBPR and BPR is determined by the STI's bottom area. The depth of the enlarged VBPR buried inside the BPR is adjustable by varying the thickness of the STI being replaced. A method includes forming two or more STI layers, and local partial replacement of the STI.
There are several significant high value attributes of the third embodiment. Process integration is easier, as aligning and landing of the BPR to VBPR is simplified, as the VBPR contact region is much larger due to the structure described herein. A larger more easily engineered cross-section for the VBPR is provided, which reduces contact resistance between the BPR and VBPR. There is even greater contact area between the BPR and VBPR. There is no metal line inside the VBPR for current traveling across the VBPR.
In
In a fourth embodiment, two layers of STI are formed, the first layer of STI is locally removed, and a VBPR metallization is performed. A cross-section of the VBPR at its liner-free interface with the BPR is increased, which provides much better conductance. At the VBPR, part of the STI is replaced with the VBPR body. The cross-section area between the VBPR and the BPR is determined by the STI layer's bottom area. Certain STI areas not used for the VBPR formation consist of a two layered STI. In the fourth embodiment, two or more STI layers are formed, and there is a local partial replacement of one or more of the STI layers with VBPR material.
There are significant high value attributes and technical effects of the fourth embodiment, including easier process integration. Aligning and landing of the BPR to VBPR is simplified, as the VBPR contact region is much larger due to the structure. The structure provides a larger cross-section for the VBPR, which reduces contact resistance between the BPR and the VBPR. The structure is more easily engineered. There is no metal liner inside the VBPR for current traveling across the VBPR.
In
Accordingly, described herein is a semiconductor device including a backside power rail, a source or drain, and a via to connect the source or drain to the backside power rail, the via comprising a transfer section having a first width and a connection area having a second width, the second width larger than the first width. The semiconductor device may further include a contact joined to a front side of the source or drain and to the via. The semiconductor device may further include dielectric liner along at least one sidewall of the via. The dielectric liner is configured to isolate the via from the source or drain. A cross-section area of the connection area between the via and the backside power rail is determined with a bottom area of an isolation layer. The transfer section extends from a front side of the source or drain to a backside of the source or drain. The semiconductor device further includes back end of line metal connected with the via to the backside power rail. The connection area of the contact connects the back end of line metal to the backside power rail without liner.
Referring now to all the Figures, in one exemplary embodiment, a semiconductor device includes a contact comprising a first section and a second section; wherein the first section of the contact is located on a front side of a source or drain; wherein the second section extends from the front side of the source or drain to a backside of the source or drain; wherein the second section of the contact is comprised of a via and a connection area; wherein the via has a first width and the connection area has a second width, and wherein the second width is larger than the first width.
The semiconductor device may further include wherein the connection area of the contact connects back end of line metal to a backside power rail. The connection area of the contact connects the back end of line metal to the backside power rail without liner inside the contact. The semiconductor device may further include dielectric liner along at least one sidewall of the contact, the dielectric liner configured to isolate the contact from at least one epitaxial gate.
In another embodiment, a method includes forming, within a wafer, a via etch into at least an isolation layer; removing a portion of the isolation layer next to the etch, to increase a connection area of a via to be larger than a transfer section of the via; filling the via etch with metal to form the via; filling the removed portion of the isolation layer with metal to form the connection area of the via; forming a backside power rail; and connecting the connection area of the via to the backside power rail.
The method may further include forming a nitride spacer within the via etch; and continuing to form the via etch within a substrate layer of the wafer. The method may further include forming dielectric liner along at least one sidewall of the via etch, the dielectric liner configured to isolate the via from at least one epitaxial gate. The method may further include forming back end of line metal; connecting the back end of line metal to the backside power rail using the via without liner inside the via; and forming a contact to connect the via to at least one gate. The method may further include forming a first isolation layer of the isolation layer; and forming a second isolation layer of the isolation layer. The method may further include removing the first isolation layer; and filling the metal within an area formed with the removal of the first isolation layer to form the connection area of the via. The first isolation layer may be formed as part of the second isolation layer, or the first isolation layer may be formed within a substrate layer of the wafer deeper into the wafer than the second isolation layer. The method may further include adjusting a depth of the connection area with varying a thickness of a portion of the isolation layer being replaced.
In another embodiment, a method of forming a semiconductor device includes forming, within a wafer, a contact etch into at least an isolation layer; forming a contact at least partially within the contact etch, the contact comprising a first section and a second section; forming the first section of the contact to be located on a front side of a source or drain; forming the second section of the contact to extend from the front side of the source or drain to a backside of the source or drain; forming the second section of the contact to comprise a via and a connection area; and forming the via to have a first width and the connection area to have a second width, wherein the second width is larger than the first width.
The method may further include forming dielectric liner along at least one sidewall of the contact, the dielectric liner configured to isolate the contact from at least one epitaxial gate. The method may further include forming back end of line metal; connecting the back end of line metal to a backside power rail using the contact without liner inside the contact; and forming another contact to connect the via to at least one gate. The method may further include removing a portion of the isolation layer next to the etch, to increase the connection area of the contact; filling the contact etch with metal to form the contact; filling the removed portion of the isolation layer with metal to form the connection area of the contact; forming a backside power rail; and connecting the connection area of the via to the backside power rail. The method may further include adjusting a depth of the connection area with varying a thickness of a portion of an isolation layer being replaced. The method may further include forming a first isolation layer of the isolation layer; and forming a second isolation layer of the isolation layer. The method may further include removing the first isolation layer; and filling the metal within an area formed with the removal of the first isolation layer to form the connection area of the contact. The first isolation layer may be formed as part of the second isolation layer the first isolation layer may be formed within a substrate layer of the wafer deeper into the wafer than the second isolation layer.
In another embodiment, a semiconductor device includes a backside power rail; a source or drain; and a via to connect the source or drain to the backside power rail, the via comprising a transfer section having a first width and a connection area having a second width, the second width larger than the first width; wherein the connection area of the via is curved from at least a surface of the transfer section to a portion of the connection area that joins to the backside power rail, to vary the second width of the connection area towards the backside power rail.
The semiconductor device may further include a contact joined to a front side of the source or drain and to the via. The semiconductor device may further include dielectric liner along at least one sidewall of the via. The dielectric liner may be configured to isolate the via from the source or drain. A cross-section area of the connection area between the via and the backside power rail may be determined with a bottom area of an isolation layer. The transfer section may extend from a front side of the source or drain to a backside of the source or drain. The semiconductor device may include back end of line metal connected with the via to the backside power rail. The connection area of the contact may connect the back end of line metal to the backside power rail without liner. The connection area may be in a shape of a dome. The connection area of the via may be convexly curved from at least the surface of the transfer section to the portion of the connection area that joins to the backside power rail, to gradually increase the second width of the connection area towards the backside power rail.
References to a ‘computer’, ‘processor’, etc. should be understood to encompass not only computers having different architectures such as single/multi-processor architectures and sequential or parallel architectures but also specialized circuits such as field-programmable gate arrays (FPGAs), application specific circuits (ASICs), signal processing devices and other processing circuitry. References to computer program, instructions, code etc. should be understood to encompass software for a programmable processor or firmware such as, for example, the programmable content of a hardware device whether instructions for a processor, or configuration settings for a fixed-function device, gate array or programmable logic device etc.
The memory(ies) as described herein may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memory, magnetic memory devices and systems, optical memory devices and systems, non-transitory memory, transitory memory, fixed memory and removable memory. The memory(ies) may comprise a database for storing data.
As used herein, circuitry may refer to the following: (a) hardware circuit implementations, such as implementations in analog and/or digital circuitry, and (b) combinations of circuits and software (and/or firmware), such as (as applicable): (i) a combination of processor(s) or (ii) portions of processor(s)/software including digital signal processor(s), software, and memory(ies) that work together to cause an apparatus to perform various functions, and (c) circuits, such as a microprocessor(s) or a portion of a microprocessor(s), that require software or firmware for operation, even if the software or firmware is not physically present. As a further example, as used herein, circuitry would also cover an implementation of merely a processor (or multiple processors) or a portion of a processor and its (or their) accompanying software and/or firmware. Circuitry would also cover, for example and if applicable to the particular element, a baseband integrated circuit or applications processor integrated circuit for a mobile phone or a similar integrated circuit in a server, a cellular network device, or another network device.
List of abbreviations, which abbreviations may be appended with each other or other characters using e.g. a dash or hyphen (“-”):
In the foregoing description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be appreciated by one of ordinary skill of the art that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or processing steps may have been omitted or may have not been described in order to avoid obscuring the presented embodiments.
The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limiting in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical applications, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular uses contemplated.