Aspects of this document relate generally to semiconductor packages. More specific implementations involve thinned power semiconductor packages with a dual side metallization structure and methods of making such thinned power semiconductor packages.
Semiconductor package fabrication processes may involve many steps. In some processes a wafer receives one or more layers, such as electrically conductive layers. Electrically conductive layers may be used to provide electrical contact areas of individual semiconductor devices singulated from the wafer. Further, in some processes the overall size of the semiconductor package may designed to be minimized.
Implementations of a semiconductor substrate may include a plurality of die including at least one contact; and a plurality of portions of an encapsulant on a surface of the semiconductor substrate, wherein each portion of the plurality of portions extends immediately above a plane of the at least one contact.
Implementations of semiconductor substrates may include one, all, or any of the following:
The plurality of portions of encapsulant may be formed through laser ablating the encapsulant over the at least one contact of the plurality of die.
The laser ablating further may include spot ablation over the at least one contact of the plurality of die.
The laser ablating further may include scanning ablation over the at least one contact of the plurality of die.
The laser ablating further may include bulk ablation over the at least one contact of the plurality of die.
The laser ablating further may include multi-pass ablation over the at least one contact of the plurality of die.
The at least one contact may be exposed by ablating the plurality of portions of the encapsulant over the plane.
Implementations of a method of forming a semiconductor package may include forming a plurality of electrical connectors on a first side of a wafer; and applying a mold compound to the first side of the wafer. The mold compound may encapsulate the plurality of electrical connectors. The method may include exposing the plurality of electrical connectors through the mold compound by ablating the mold compound immediately above each electrical connector of the plurality of electrical connectors with a laser.
Implementations of a method of forming a semiconductor package may include one, all, or any of the following:
Exposing the plurality of electrical connectors through the mold compound by ablating the mold compound with a laser further may include spot ablation over the plurality of electrical connectors.
Exposing the plurality of electrical connectors through the mold compound by ablating the mold compound with a laser further may include scanning ablation over the plurality of electrical connectors.
Exposing the plurality of electrical connectors through the mold compound by ablating the mold compound with a laser further may include bulk ablation over the plurality of electrical connectors.
Exposing the plurality of electrical connectors through the mold compound by ablating the mold compound with a laser further may include multi-pass ablation over the plurality of electrical connectors in multiple passes.
Implementations of a semiconductor package may include at least one electrical contact including a perimeter; and a mold compound raised above a largest planar area of the contact immediately around the perimeter of the at least one electrical contact.
Implementations of a semiconductor package may include one, all, or any of the following:
The at least one electrical contact may be exposed by ablating the mold compound over the largest planar area.
The ablating further may include spot ablation over the largest planar area of the contact around the perimeter of the at least one electrical contact.
The ablating further may include scanning ablation over the largest planar area of the contact around the perimeter of the at least one electrical contact.
The ablating further may include bulk ablation over the largest planar area of the contact around the perimeter of the at least one electrical contact.
The ablating further may include multi-pass ablation over the largest planar area of the contact around the perimeter of the at least one electrical contact.
The raising of the mold compound may be formed through laser ablating over the at least one electrical contact.
The foregoing and other aspects, features, and advantages will be apparent to those artisans of ordinary skill in the art from the DESCRIPTION and DRAWINGS, and from the CLAIMS.
Implementations will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:
This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended methods of ablation will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such methods of ablation, and implementing components and methods, consistent with the intended operation and methods.
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In various implementations, the plurality of recesses 6 may be formed with, by non-limiting example, a saw, a laser, a plasma etch, a chemical etch, or any other method for forming a recess in a wafer. In still other implementations, the sidewalls of the plurality of recesses 6 may be slightly patterned or ridged which may facilitate adhesion of a mold compound to the sidewalls of the plurality of recesses 6. In various implementations, the plurality of recesses 6 may be positioned in the wafer 2 so that they are between the semiconductor devices in the wafer. In other implementations, the plurality of recesses 6 may be positioned in the wafer so they are between the various semiconductor die formed in/on the wafer.
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In various implementations, the semiconductor packages disclosed herein may include power semiconductor devices, however, in other implementations other semiconductor device types (transistors, microprocessors, passive components, etc.) may be included in the semiconductor packages. In various implementations, the semiconductor package includes a die. The die may be a silicon die, and in such implementations, the silicon die could be any type of silicon die including, by non-limiting example, an epitaxial silicon die, silicon-on-insulator, polysilicon, silicon carbide any combination thereof, or any other silicon-containing die material. Further, it is also understood that in various implementations a die other than a silicon-containing die may be used, such as, by non-limiting example, gallium arsenide, ruby, sapphire, a metal-containing die, or any other semiconductor die type.
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In particular implementations, the backside metal layer may include, by non-limiting example, Ti/Ni/Cu, Ti/Cu, TiW/Cu, or any other type of metal stack or metal alloy including copper. In various implementations, and as illustrated by
In implementations where a back metal layer is employed (and also in implementations where it is not used), a stress relief etch may be utilized in various method implementations. This stress relief etch may be carried out after backgrinding and with or without back metal. In some implementations, the stress relief wet etching may take place after protecting the front side (die side) of the semiconductor substrate. The stress relief etching may reduce the backside damage to the semiconductor substrate that is caused by the backgrinding process. The use of the stress relief etching may also facilitate adhesion of any back metal applied to the ground surface. While the use of wet etching has been disclosed, in various implementations the use of dry etching could be employed in various implementations.
Whether the particular thinned die or wafer utilizes a back metal (and for some, before backmetal is applied to the thinned die or wafer), the various thinned die/wafers disclosed in this document have one or more electrical contacts exposed. Referring to
In various implementations, the ablation may be spot ablation. In implementations of spot ablation, the ablation may take place through targeting specific locations across the wafer where electrical connectors are located and then removing the mold compound to expose those electrical connectors. In implementations of scanning ablation, a scanning pattern is employed where the implement (laser, water jet etc.) follows a predetermined pattern across the wafer while activated, ablating material as it passes. In implementations of bulk ablation the ablation implement scans across all or substantially all of the surface of the wafer (for those ablation techniques that are utilize scanning) or works directly to ablate all or substantially all of the mold compound on the wafer surface. For implementations of multi-pass ablation, the ablation implement may be employed to pass over at least a portion of a previously ablated surface one or more additional times to further ablate the material.
For situations where laser ablation is employed, a single laser light beam may used to perform the ablation. In other implementations, multiple laser beams may be used to simultaneously ablate by indexing across the wafer on opposite portions of the wafer. In various implementations, these laser beams may index for at least part of the time spaced apart across a midpoint of the wafer. The particular alignment/feed speeds, etc. of the laser beam(s) in various implementations where single or dual laser light beams are employed may be determined by a wide variety of factors, including, by non-limiting example, laser power, optical configuration, throughput, mold compound thickness, and any other factor driven by tool configuration, throughput, or process effectiveness.
In various implementations, two laser beams may begin on opposite sides of the wafer and index towards each other toward the midpoint; in others, they may begin adjacent to the midpoint, and index away from each other. The spacing of the beams may be as close as adjacent electrical contacts may be any number of electrical contact locations away from each other. In this implementation, and in all other multiple laser beam implementations disclosed in this document, the two or more laser beams may have the same characteristics, or may be different from one another in one or more of the following respects, by non-limiting example: laser type, laser wavelength, spot size, power, pulse energy, pulse width, repetition rate/frequency, indexing speed, dwell time, ablation depth into the mold compound, numerical aperture, average power, and any other desired laser characteristic. Also, the two or more laser beams may be generated by the same or different laser devices in various implementations.
In various implementations, the path followed by the single or dual laser beams may be an alternating single pass path, where the laser indexes across the wafer first in the y direction, over in the x direction, and then indexes in the opposite y direction in various steps across the wafer. In various implementations, the spacing of steps in the x direction may the same. In other implementations, however, the spacing of steps may vary across the wafer, either for an initial period, or for the entire distance across the wafer in the x direction, depending on how the mold compound ablates or the location of the electrical connectors.
In some implementations, the single/dual laser beams may employ an intersecting dual pass path. In various versions of the paths, the paths are first irradiated by the laser during the first pass, and then irradiated again by the laser during the second pass. The use of dual pass paths may allow for, by non-limiting example, the enhancement of the ablation of the mold compound, improve sidewall shape, reduce risk of burning/carbonization of the material of the material of the mold compound, reduce flow of the mold compound under the heat of the laser, permit sufficient cooling time, or otherwise adjust the structure of the ablated mold compound between passes. This may, in turn, enhance the thickness or other desired characteristics of the damage layer formed.
In various implementations, single pass spiral paths may be employed. In various implementations, various combinations and arrangements of spiral paths may be employed, such as multi-pass paths, and spirals of various shapes and designs (more tightly arranged spirals at the beginning or end of the spiral) and various overlapping arrangements of spirals may be used. Also, for spiral (and alternating/intersecting paths), where pulsed rather than continuous wave laser irradiation is employed, the frequency of pulses of laser irradiation along the path may be varied along the path (more points at the beginning, middle, or end of the path, or in different portions of the path than in other portions).
In various implementations where intersecting dual pass paths are employed, the second pass may be angled rather than executed at about 90 degrees to the first pass. The angle at which the second pass is performed relative to the first pass may be determined by various factors, including, by desired throughput rates through the laser process tool, location of the various electrical connectors, the ablation characteristics of the particular mold compound being ablated, and any other process characteristic that affects the speed or efficacy of the laser ablation process. In various implementations, some of the locations along the path of laser irradiation may be common between the first pass and the second pass while other locations are unique to one of the passes.
In some other implementations of a dual intersecting pass path all of the locations along the second pass may be oriented substantially parallel with the locations of the first pass and none are shared between the two passes. The use of this technique may, in various implementations, assist with allowing the mold compound to react to the damage of the first pass before the second pass is carried out. In some implementations, the wafer may be laser ablated using a dual intersecting pass path which is executed in the reverse order another path. In various implementations, the dual pass path may be executed in varying orders from substrate to substrate as the mold compound ablation may not be affected by the order of execution of the paths. In other implementations, the order in which the dual pass path is executed may affect the characteristics of the mold compound being ablated or remaining after ablation, so all substrates have to be processed in the same order. Where the mold compound ablation and/or characteristics of the remaining mold compound depend on the execution order of the dual pass path, this may be caused by a wide variety of factors, including, by non-limiting example, the material characteristics of the particular mold compound being ablated, the glass transition temperature of the mold compound, the oxidation rate of the mold compound, the absorption percentage of light by the mold compound for the laser length being used, or any other material characteristics of the mold compound and/or the laser light.
Many different single pass, dual pass, and more than two pass paths for processing wafers may constructed using the principles disclosed in this document. Also, many different intersecting, spiral, alternating, alternating+spiral, random, and semi-random paths may be constructed using the principles disclosed herein. What paths are employed will depend on many of the different laser and mold compound material factors desired, as well as the locations of the electrical contacts across the wafer.
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In some method implementations, the method may further include ablating one or more of the portions 13 (referring to
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In various implementations, alignment of the substrate or wafer prior to the ablation or etching process may take place using a variety of methods. For example, notches may be formed along the edge of the wafer that permit alignment of the wafer to be carried out prior to ablation beginning. In other implementations, an infrared camera may be used to identify alignment features in the side of the wafer opposite the site being ablated (a backside of the wafer in various implementations). In other implementations, at least three areas on the topside of the wafer may not be encapsulated or only partially encapsulated to expose alignment features for use in alignment. In yet other implementations, another imaging technique may be employed to penetrate below or through the mold compound like X-rays to allow the alignment system to identify the alignment features. A wide variety of structures and systems may be employed to ensure the wafer/substrate is aligned as needed to perform the ablation/etching process in the various implementations disclosed herein.
In other method and process implementations, laser ablation or the other material removal methods disclosed herein may be used in combination with other methods of partially thinning the mold compound prior to ablating/etching the material. For example, grinding may be used to partially thin the mold compound prior to laser ablating using any method disclosed herein. In other implementations, polishing or lapping may be employed prior to laser ablating or etching using any method disclosed herein. A wide variety of process variations may be constructed using the principles disclosed herein.
In places where the description above refers to particular implementations of ablation methods and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other ablation methods and related implementing components.