Claims
- 1. A method of fabricating a RESURF LDMOS transistor on a semiconductor layer of a first conductivity type comprising the steps of:
- forming a masking layer on said semiconductor layer to define an implant area;
- implanting a dopant of a second conductivity type into said defined implant area;
- forming a thick insulator layer on said defined implant area to create a low resistance RESURF drift region, wherein said thick insulator layer and said drift region are self-aligned to each other for improved breakdown characteristics;
- removing said masking layer after said step of forming said thick insulator layer;
- implanting a body of the first conductivity type into said semiconductor layer adjacent said drift region;
- implanting a source region and a drain region of said second conductivity type in said semiconductor layer, said source region within said body, said drain region adjacent said drift region: and
- forming a conductive gate insulatively disposed on said body extending from said source region to said thick insulator layer.
- 2. The method of claim 1, wherein said semiconductor layer comprises a thin epitaxial layer of said second conductivity type on a first conductivity type layer.
- 3. The method of claim 1, wherein said conductive gate is formed on a portion of said thick insulator layer.
- 4. The method of claim 1, further comprising the step of forming a channel region within said body between said source region and said drift region.
- 5. The method of claim 2, wherein said thin epitaxial layer is grown to provide a continuous path for current flow between said drift region and said channel region.
- 6. The method of claim 2, wherein said drift region is implanted with a higher dopant concentration than said thin epitaxial layer.
- 7. The method of claim 2, wherein said drift region is implanted to extend through said thin epitaxial layer to the first conductivity type layer of the semiconductor layer.
- 8. The method of claim 1, wherein said step of forming a masking layer comprises the step of forming a nitride mask.
- 9. The method of claim 8, wherein said nitride mask also defines isolation regions.
- 10. The method of claim 9, further comprising the steps of:
- forming a resist mask on said nitride mask to mask said isolation regions prior to said step of implanting said defined implant areas; and
- removing said resist mask prior to said step of forming said thick insulator layer such that said thick insulator regions are also formed in said isolation regions.
- 11. A method of fabricating a high voltage RESURF LDMOS transistor on a semiconductor layer of a first conductivity type comprising the steps of:
- forming a masking layer on said semiconductor layer to define an implant area;
- implanting a dopant of a second conductivity type into said defined implant area;
- simultaneously forming a LOCOS region on said defined implant area and a low resistance RESURF drift region, wherein said LOCOS region and said drift region are self-aligned to each other for improved breakdown characteristics;
- removing said masking layer after said step of forming said LOCOS region and said drift region;
- implanting a body of the first conductivity type into said semiconductor layer adjacent said drift region;
- implanting a source region and a drain region of said second conductivity type in said semiconductor layer, said source region within said body, said drain region adjacent said drift region; and
- forming a conductive gate insulatively disposed on said body extending from said source region to said LOCOS region.
Parent Case Info
This is a continuation of application Ser. No. 08/191,228, filed Feb. 1, 1994 U.S. Pat. No. 5,406,110; which is a divisional of application Ser. No. 07/815,732, filed on Dec. 30, 1991, now U.S. Pat. No. 5,306,652.
US Referenced Citations (15)
Divisions (1)
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Number |
Date |
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Parent |
815732 |
Dec 1991 |
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Continuations (1)
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Number |
Date |
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191228 |
Feb 1994 |
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