Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication

Abstract
Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.
Description
FIELD OF THE INVENTION

This invention relates generally to lattice-mismatched semiconductor heterostructures and, more specifically, to the selective channel material regrowth in connection with the integration of dissimilar semiconductor materials.


BACKGROUND OF THE INVENTION

The increasing operating speeds and computing power of microelectronic devices have recently given rise to the need for an increase in the complexity and functionality of the semiconductor structures from which that these devices are fabricated. Hetero-integration of dissimilar semiconductor materials, for example, III-V materials, such as gallium arsenide, gallium nitride, indium aluminum arsenide, and/or germanium with silicon or silicon-germanium substrate, is an attractive path to increasing the functionality and performance of the CMOS platform. In particular, heteroepitaxial growth can be used to fabricate many modern semiconductor devices where lattice-matched substrates are not commercially available or to potentially achieve monolithic integration with silicon microelectronics. Performance and, ultimately, the utility of devices fabricated using a combination of dissimilar semiconductor materials, however, depends on the quality of the resulting structure. Specifically, a low level of dislocation defects is important in a wide variety of semiconductor devices and processes, because dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties, which, in turn, results in poor material quality and limited performance. In addition, the threading dislocation segments can degrade physical properties of the device material and can lead to premature device failure.


As mentioned above, dislocation defects typically arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material—often referred to as “heterostructure”—due to different crystalline lattice sizes of the two materials. This lattice mismatch between the starting substrate and subsequent layer(s) creates stress during material deposition that generates dislocation defects in the semiconductor structure.


Misfit dislocations form at the mismatched interface to relieve the misfit strain. Many misfit dislocations have vertical components, termed “threading segments,” which terminate at the surface. These threading segments continue through all semiconductor layers subsequently added to the heterostructure. In addition, dislocation defects can arise in the epitaxial growth of the same material as the underlying substrate where the substrate itself contains dislocations. Some of the dislocations replicate as threading dislocations in the epitaxially grown material. Other kinds of dislocation defects include stacking faults, twin boundaries, and anti-phase boundaries. Such dislocations in the active regions of semiconductor devices, such as diodes, lasers and transistors, may significantly degrade performance.


To minimize formation of dislocations and associated performance issues, many semiconductor heterostructure devices known in the art have been limited to semiconductor layers that have very closely—e.g. within 0.1%—lattice-matched crystal structures. In such devices a thin layer is epitaxially grown on a mildly lattice-mismatched substrate. As long as the thickness of the epitaxial layer is kept below a critical thickness for defect formation, the substrate acts as a template for growth of the epitaxial layer, which elastically conforms to the substrate template. While lattice matching and near matching eliminate dislocations in a number of structures, there are relatively few lattice-matched systems with large energy band offsets, limiting the design options for new devices.


Accordingly, there is considerable interest in heterostructure devices involving greater epitaxial layer thickness and greater lattice misfit than known approaches would allow. For example, it has long been recognized that gallium arsenide grown on silicon substrates would permit a variety of new optoelectronic devices marrying the electronic processing technology of silicon VLSI circuits with the optical component technology available in gallium arsenide. See, for example, Choi et al, “Monolithic Integration of Si MOSFET's and GaAs MESFET's”, IEEE Electron Device Letters, Vol. EDL-7, No. 4, April 1986. Highly advantageous results of such a combination include high-speed gallium arsenide circuits combined with complex silicon VLSI circuits, and gallium arsenide optoelectronic interface units to replace wire interconnects between silicon VLSI circuits. Progress has been made in integrating gallium arsenide and silicon devices. See, for example, Choi et al, “Monolithic Integration of GaAs/AlGaAs Double-Heterostructure LED's and Si MOSFET's” IEEE Electron Device Letters, Vol. EDL-7, No. 9, September 1986; Shichijo et al, “Co-Integration of GaAs MESFET and Si CMOS Circuits”, IEEE Electron Device Letters, Vol. 9, No. 9, September 1988. However, despite the widely recognized potential advantages of such combined structures and substantial efforts to develop them, their practical utility has been limited by high defect densities in gallium arsenide layers grown on silicon substrates. See, for example, Choi et al, “Monolithic Integration of GaAs/AlGaAs LED and Si Driver Circuit”, IEEE Electron Device Letters, Vol. 9, No. 10, October 1988 (p. 513). Thus, while basic techniques are known for integrating gallium arsenide and silicon devices, there exists a need for producing gallium arsenide layers having a low density of dislocation defects.


To control dislocation densities in highly-mismatched deposited layers, there are three known techniques: wafer bonding of dissimilar materials, substrate patterning, and composition grading. Bonding of two different semiconductors may yield satisfactory material quality. Due to the limited availability and high cost of large size Ge or III-V wafers, however, the approach may not be practical.


Techniques involving substrate patterning exploit the fact that the threading dislocations are constrained by geometry, i.e. that a dislocation cannot end in a crystal. If the free edge is brought closer to another free edge by patterning the substrate into smaller growth areas, then it is possible to reduce threading dislocation densities. In the past, a combination of substrate patterning and epitaxial lateral overgrowth (“ELO”) techniques was demonstrated to greatly reduce defect densities in gallium nitride device, leading to fabrication of laser diodes with extended lifetimes. This process substantially eliminates defects in ELO regions but highly defective seed windows remain, necessitating repetition of the lithography and epitaxial steps to eliminate all defects. In a similar approach, pendeo-epitaxy eliminates substantially all defects in the epitaxial region proximate to the substrate but requires one lithography and two epitaxial growth steps. Furthermore, both techniques require the increased lateral growth rate of gallium nitride, which has not been demonstrated in all heteroepitaxial systems. Thus, a general defect-reduction process utilizing a minimum of lithography/epitaxy steps that does not rely on increased lateral growth rates would be advantageous both to reduce process complexity and facilitate applicability to various materials systems.


Another known technique termed “epitaxial necking” was demonstrated in connection with fabricating a Ge-on-Si heterostructure by Langdo et al. in “High Quality Ge on Si by Epitaxial Necking,” Applied Physics Letters, Vol. 76, No. 25, April 2000. This approach offers process simplicity by utilizing a combination of selective epitaxial growth and defect crystallography to force defects to the sidewall of the opening in the patterning mask, without relying on increased lateral growth rates. Specifically, as shown in FIGS. 1A and 1B, in the (111)<110> diamond cubic slip system, misfit dislocations lie along <110> directions in the (100) growth plane while the threading segments rise up on (111) planes in <110> directions. Threading segments in <110> directions on the (111) plane propagate at a 45° angle to the underlying Si (100) substrate surface. Thus, if the aspect ratio of the holes in the patterning mask is greater than 1, threading segments will be blocked by the mask sidewall, resulting in low-defect top Ge “nodules” formed directly on Si. One important limitation of epitaxial necking, however, is the size of the area to which it applies. In general, as discussed in more detail below, the lateral dimensions (designated as 1 in FIG. 1A) in both dimensions have to be relatively small in order for the dislocations to terminate at sidewalls.


Thus, there is a need in the art for versatile and efficient methods of fabricating semiconductor heterostructures that would constrain dislocation defects in a variety of lattice-mismatched materials systems. There is also a need in the art for semiconductor devices utilizing a combination of integrated lattice-mismatched materials with reduced levels of dislocation defects for improved functionality and performance.


SUMMARY OF THE INVENTION

Accordingly, embodiments of the present invention provide semiconductor heterostructures with significantly minimized interface defects, and methods for their fabrication, that overcome the limitations of known techniques. In contrast with the prior art approach of minimizing dislocation defects by limiting misfit epitaxial layers to less than their critical thicknesses for elastic conformation to the substrate, in its various embodiments, the present invention utilizes greater thicknesses and limited lateral areas of component semiconductor layers to produce limited-area regions having upper portions substantially exhausted of threading dislocations and other dislocation defects such as stacking faults, twin boundaries, or anti-phase boundaries. As a result, the invention contemplates fabrication of semiconductor devices based on monolithic lattice-mismatched heterostructures long sought in the art but heretofore impractical due to dislocation defects.


In particular applications, the invention features semiconductor structures of Ge or III-V devices integrated with a Si substrate, such as, for example, an optoelectronic device including a gallium arsenide layer disposed over a silicon wafer, as well as features methods of producing semiconductor structures that contemplate integrating Ge or III-V materials on selected areas on a Si substrate.


In general, in one aspect, the invention is directed to a method of forming a semiconductor heterostructure. The method includes providing a substrate that contains, or consists essentially of, a first semiconductor material, and then providing a dislocation-blocking mask over the substrate. The mask has an opening extending to the surface of the substrate and defined by at least one sidewall. At least a portion of the sidewall meets the surface of the substrate at an orientation angle to a selected crystallographic direction of the first semiconductor material. The method further includes depositing in the opening a regrowth layer that includes a second semiconductor material, such that the orientation angle causes threading dislocations in the regrowth layer to decrease in density with increasing distance from the surface of the substrate. The dislocation-blocking mask may include a dielectric material, such as, for example, silicon dioxide or silicon nitride.


Embodiments of this aspect of the invention include one or more of the following features. An overgrowth layer that includes the second semiconductor material can be deposited over the regrowth layer and over at least a portion of the dislocation-blocking mask. At least at least a portion of the overgrowth layer can be crystallized. The regrowth layer can be planarized, for example, such that, following the planarizing step, a planarized surface of regrowth layer is substantially co-planar with a top surface of the dislocation-blocking mask. The planarizing step may include chemical-mechanical polishing.


In addition, in various embodiments of the invention, the first semiconductor material is silicon or a silicon germanium alloy. The second semiconductor material can include, or consist essentially of, either a group II, a group III, a group IV, a group V, or a group VI element, or a combination thereof, for example, germanium, silicon germanium, gallium arsenide, aluminum antimonide, indium aluminum antimonide, indium antimonide, indium arsenide, indium phosphide, or gallium nitride. In some embodiments, the second semiconductor material is compositionally graded.


In many embodiments of the invention, the selected crystallographic direction of the first semiconductor material is aligned with at least one direction of propagation of threading dislocations in the regrowth layer. In certain versions of these embodiment, the orientation angle ranges from about 30 to about 60 degrees, for example, is about 45 degrees.


The surface of the substrate may have (100), (110), or (111) crystallographic orientation. In some embodiments, the selected crystallographic direction is substantially aligned with a <110> crystallographic direction of the first semiconductor material. In other embodiments, the portion of the sidewall meets the surface of the substrate in substantial alignment with a <100> crystallographic direction of the first semiconductor material.


In certain embodiments of this and other aspects of the invention, the first semiconductor material is non-polar, the second semiconductor material is polar, and the orientation angle causes anti-phase boundaries in the regrowth layer to decrease in density with increasing distance from the surface of the substrate. In some embodiments, the threading dislocations terminate at the sidewall of the opening in the dislocation-blocking mask at or below a predetermined distance H from the surface of the substrate. In some versions of these embodiments, the opening in the dislocation-blocking mask has a variable width. In other versions, the sidewall of the opening in the dislocation-blocking mask includes a first portion disposed proximal to the surface of the substrate, and a second portion disposed above the first portion. A height of the first portion can be at least equal to the predetermined distance H from the surface of the substrate. The first portion of the sidewall can be substantially parallel to the second portion. Also, in some versions, the second portion of the sidewall is flared outwardly. Further, in certain embodiments of this and other aspects of the invention, the orientation angle causes stacking faults and/or twin boundaries in the regrowth layer to decrease in density with increasing distance from the surface of the substrate.


Further yet, in certain embodiments of this and other aspects of the invention, the sidewall of the opening in the dislocation-blocking mask has a height at least equal to a predetermined distance H from the surface of the substrate. In these embodiments, the opening is substantially rectangular and has a predetermined width W that is smaller than a length L of the opening. For example, the width W of the opening can be less than about 500 nm, and the length L of the opening can exceed each of W and H. In some versions of these embodiments, the substrate consists essentially of silicon and has a (100) crystallographic orientation, the orientation angle is about 45 degrees to the direction of propagation of defects in the regrowth layer, and the predetermined distance H is at least W √2. In other versions, the substrate consists essentially of silicon and has a (110) crystallographic orientation, the orientation angle is about 45 degrees, and the predetermined distance H is at least W √6/3. In still other versions, the substrate consists essentially of silicon and has a (111) crystallographic orientation, the orientation angle is about 45 degrees, and the predetermined distance H is at least 2W.


In other embodiments of this aspect of the invention, the method additionally includes depositing a lattice-mismatched layer over at least a portion of the substrate prior to providing the dislocation-blocking mask thereon. The lattice-mismatched layer preferably includes a third semiconductor material and is at least partially relaxed. The lattice-mismatched layer can be planarized prior to providing the dislocation-blocking mask. The second semiconductor material and the third semiconductor material can be or include the same semiconductor material.


In general, in another aspect, the invention features a method of forming a semiconductor heterostructure that begins with providing a substrate including a first semiconductor material. The method additionally includes providing a dislocation-blocking mask over the substrate. The mask has an opening extending to the surface of the substrate and defined by at least one sidewall. At least a portion of the sidewall meets the surface of the substrate at an orientation angle to a selected crystallographic direction of the first semiconductor material. The method further includes the steps of depositing in the opening a regrowth layer that includes a second semiconductor material and subjecting the regrowth layer to thermal cycling, thereby causing threading dislocations to terminate at the sidewall of the opening in the dislocation-blocking mask at or below a predetermined distance from the surface of the substrate.


In various embodiments of this and other aspects of the invention, threading dislocations (and/or other dislocation defects such as stacking faults, twin boundaries, or anti-phase boundaries) in the regrowth layer decrease in density with increasing distance from the surface of the substrate. The first semiconductor material may include, or consist essentially of, silicon or a silicon germanium alloy. The second semiconductor material may include, or consist essentially of, a group II, a group III, a group IV, a group V, and/or a group VI element, and/or combinations thereof, for example, selected from the group consisting of germanium, silicon germanium, gallium arsenide, and gallium nitride. In some embodiments, the second semiconductor material is compositionally graded.


Generally, in yet another aspect, the invention focuses on a semiconductor structure that includes a substrate and a dislocation-blocking mask disposed over the substrate. The substrate includes, or consists essentially of, a first semiconductor material, such as, for example, silicon or a silicon germanium alloy. The dislocation-blocking mask may include a dielectric material, such as, for example, silicon dioxide or silicon nitride. The mask has an opening extending to the surface of the substrate and defined by at least one sidewall at least a portion of which meeting the surface of the substrate at an orientation angle to a selected crystallographic direction of the first semiconductor material. A regrowth layer comprising a second semiconductor material is formed in the opening, such that the orientation angle causes threading dislocations and/or other dislocation defects such as stacking faults, twin boundaries, or anti-phase boundaries in the regrowth layer to decrease in density with increasing distance from the surface of the substrate.


In various embodiments of this aspect of the invention, the threading dislocations terminate at the sidewall of the opening in the dislocation-blocking mask at or below a predetermined distance H from the surface of the substrate. In some embodiments of this aspect of the invention, the selected crystallographic direction of the first semiconductor material is aligned with at least one propagation direction of threading dislocations in the regrowth layer. In certain versions of these embodiments, the orientation angle ranges from about 30 to about 60 degrees, for example, is about 45 degrees.


The surface of the substrate may have (100), (110), or (111) crystallographic orientation. In some embodiments, the selected crystallographic direction is substantially aligned with a <110> crystallographic direction of the first semiconductor material. In other embodiments, the portion of the sidewall meets the surface of the substrate in substantial alignment with a <100> crystallographic direction of the first semiconductor material.


Also, certain embodiments of this aspect of the invention include an overgrowth layer disposed over the regrowth layer and over at least a portion of the dislocation-blocking mask, as well as a lattice-mismatched layer disposed over at least a portion of the substrate underneath the dislocation-blocking mask. The overgrowth layer and/or the lattice-mismatched layer may include a second semiconductor material and may be at least partially relaxed.


Further, in still another aspect, the invention features a semiconductor device formed over a substrate that includes a source region, a drain region, and a channel region therebetween. The substrate includes, or consists essentially of, a first semiconductor material, for example, a silicon. Also, a dislocation-blocking mask is disposed over the substrate. The mask has an opening extending to the surface of the substrate and is defined by at least one sidewall. The device additionally includes a regrowth region formed in the opening. At least a portion of the sidewall meets the surface of the substrate at an orientation angle to a selected crystallographic direction of the first semiconductor material, for example, about 45 degrees to the direction of propagation of threading dislocations in the regrowth region. The regrowth region has a first portion disposed proximal to the surface of the substrate, where threading dislocations and/or other dislocation defects such as stacking faults, twin boundaries, or anti-phase boundaries in the regrowth region substantially terminate, and a second portion disposed above the first portion and having the channel region formed therein. The first portion of the regrowth region includes a second semiconductor material and the second portion includes a third semiconductor material. The second and third semiconductor materials may be, or include, the same material.


In one embodiment, the semiconductor substrate includes a silicon wafer, an insulating layer disposed thereon, and a strained semiconductor layer disposed on the insulating layer. The strained semiconductor layer may include silicon or germanium. As used herein, the term “strain” encompasses uniaxial and biaxial strain, as well as tensile and compressive strain. In another embodiment, the semiconductor substrate includes a silicon wafer, a compositionally uniform relaxed Si1-xGex layer (where 0<x<1) deposited thereon, a strained silicon layer deposited on the relaxed Si1-xGex layer. A compositionally graded Si1-xGex layer can be disposed between the compositionally uniform Si1-xGex relaxed layer and the silicon wafer. Also, an insulating layer can be disposed between the compositionally uniform relaxed Si1-xGex layer and the silicon wafer. In yet another embodiment, at least partially relaxed lattice-mismatched layer is disposed between at least a portion of the substrate and the dislocation-blocking mask.


The second semiconductor material and/or the third semiconductor material can include, or consist essentially of, a group II, a group III, a group IV, a group V, and/or a group VI element, and/or combinations thereof, for example, germanium, silicon germanium, gallium arsenide, gallium nitride, indium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, aluminum antimonide, indium aluminum antimonide, indium antimonide, and/or indium phosphide. In some embodiments, the first portion of the regrowth region may include silicon germanium and the second portion of the regrowth region may include a layer of strained germanium or strained silicon germanium. In other embodiments, the first portion of the regrowth region includes indium phosphide and the second portion of the regrowth region includes a layer of indium gallium arsenide disposed over a layer of indium aluminum arsenide. In other embodiments, the first portion of the regrowth region may include indium aluminum antimonide and the second portion of the regrowth region may include a layer of indium antimonide.


In various embodiments of the invention, the selected crystallographic direction of the first semiconductor material is aligned with at least one propagation direction of threading dislocations in the regrowth region. Threading dislocations in the regrowth region may substantially terminate at the sidewall of the opening in the dislocation-blocking mask at or below a predetermined distance from the surface of the substrate. The dislocation-blocking mask may include a dielectric material, for example, silicon dioxide or silicon nitride. In a particular embodiment, the dislocation-blocking mask includes a silicon nitride layer disposed over a silicon dioxide layer.


In certain embodiments, the source region and the drain region of the device are epitaxially deposited over the dislocation-blocking mask; for example, they may represent a structure epitaxially deposited over the dislocation-blocking mask proximal to the regrowth region following formation thereof. In some versions of these embodiments, the structure includes a first material forming a Schottky junction at the interface with the regrowth region. The structure may further include a second material, which may be strained, unstrained, or amorphous. A gate insulator can be disposed over the regrowth region, and, in some embodiments, a silicon layer having thickness ranging from about 5 Å to about 15 Å is disposed between the gate insulator and the regrowth region.


In general, in still another aspect, the invention features an integrated circuit that includes a substrate and a dislocation-blocking mask disposed over the substrate. The mask has an opening extending to the surface of the substrate and defined by at least one sidewall. The substrate includes, or consists essentially of, a first semiconductor material, such as, for example, silicon. At least a portion of the sidewall meets the surface of the substrate at an orientation angle to a selected crystallographic direction of the first semiconductor material. The integrated circuit also includes a regrowth region formed in the opening. The regrowth region has a first portion disposed proximal to the surface of the substrate, and threading dislocations and/or other dislocation defects such as stacking faults, twin boundaries, or anti-phase boundaries in the regrowth region substantially terminate in the first portion. The regrowth layer also has a second portion disposed above the first portion. The first and second portions include, or consist essentially of, either different or the same semiconductor material(s). Further, a p-transistor is formed over a first area of the semiconductor substrate and an n-transistor is formed over a second area of the semiconductor substrate, each transistor has a channel through the second portion of the regrowth region. The transistors are interconnected in a CMOS circuit.


In yet another aspect, the invention relates to a method of forming a non-planar FET. The method begins with providing a substrate that includes, or consists essentially of, a first semiconductor material, such as, for example, silicon. The method further includes the steps of providing a dislocation-blocking mask over the substrate and forming an opening in the mask extending to the surface of the substrate and defined by at least one sidewall. The mask has a first dielectric layer disposed over a second dielectric layer. At least a portion of the sidewall meets the surface of the substrate at an orientation angle to a selected crystallographic direction of the first semiconductor material. The method additionally includes selectively forming in the opening a regrowth region that contains a second semiconductor material. The orientation angle and/or the image force causes threading dislocations and/or other dislocation defects such as stacking faults, twin boundaries, or anti-phase boundaries in the regrowth region to decrease in density with increasing distance from the surface of the substrate. The method further includes selectively removing at least a portion of the first dielectric layer to expose at least a portion of the regrowth region, thereby forming a semiconductor fin structure. A gate dielectric region is provided over at least a portion of the fin structure. A gate contact is disposed over the gate dielectric region. A source region and a drain region can be formed in the fin structure. The regrowth region can be planarized, for example, by chemical-mechanical polishing, prior to selectively removing at least a portion of the first dielectric layer.


Also, in a further aspect, the invention contemplates a method of forming an optoelectronic device. The method begins with providing a substrate that includes, or consists essentially of, a first semiconductor material, such as, for example, silicon. The method further includes the steps of providing a dislocation-blocking mask over the substrate and forming an opening in the mask extending to the surface of the substrate. The opening is defined by at least one sidewall. At least a portion of the sidewall meets the surface of the substrate at an orientation angle to a selected crystallographic direction of the first semiconductor material. The method additionally includes selectively depositing in the opening a first portion of the regrowth region that contains, or consists essentially of, a second semiconductor material, while in situ doping the second semiconductor material until thickness of the first portion approximates or exceeds the predetermined distance. The orientation angle causes threading dislocations and/or other dislocation defects such as stacking faults, twin boundaries, or anti-phase boundaries in the first portion to substantially terminate at or below a predetermined distance from the surface of the substrate. The method continues with the step of selectively depositing a second portion of the regrowth region that contains, or consists essentially of, a third semiconductor material, in the opening to a thickness selected to achieve a predetermined level of absorption of incident light; and then forming a doped region in the second portion. In various embodiments, the method further includes, prior to providing a dislocation-blocking mask, the step of forming a p-type or n-type region in the substrate.





BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following drawings, in which:



FIG. 1A depicts a schematic cross-sectional side view of a silicon substrate with a germanium layer formed thereon according to an “epitaxial necking” technique known in the art;



FIG. 1B is an XTEM image illustrating the semiconductor heterostructure of FIG. 1A;



FIGS. 2A, 2B, and 2C are schematic diagrams showing the three types of crystalline orientation for silicon;



FIGS. 3A, 3B, 4A, 4B, 4C, 4D, 4E, 5A, and 5B depict schematic views of different lattice-mismatched semiconductor heterostructures and structures for blocking dislocations therein, according to various embodiments of the invention;



FIGS. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, 7A, 7B, and 7C depict schematic cross-sectional side views of the lattice-mismatched semiconductor heterostructures having increased active area, according to various embodiments of the invention;



FIGS. 8, 9, 10A, and 10B depict various applications of dislocation blocking techniques for semiconductor devices, according to various embodiments of the invention;



FIGS. 11 and 12 depict Ge or III-V photodetector integration into Si substrate according to particular embodiments of the invention;



FIGS. 13A, 13B, and 13C depict semiconductor heterostructures employing dislocation-blocking techniques according to alternative embodiments of the invention; and



FIGS. 14A, 14B, 14C, 15A, 15B, 15C, 15D, 16A, 16B, 16C and 16D depict a method of trapping defects by forming grooves in a semiconductor substrate in accordance with various embodiments of the invention.





DETAILED DESCRIPTION

In accordance with its various embodiments, the present invention contemplates fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper surfaces substantially exhausted of threading dislocations and other dislocation defects, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.


Silicon (Si) is recognized as presently being the most ubiquitous semiconductor for the electronics industry. Most of silicon that is used to form silicon wafers is formed from single crystal silicon. The silicon wafers serve as the substrate on which CMOS devices are formed. The silicon wafers are also referred to as a semiconductor substrate or a semiconductor wafer. While described in connection with silicon substrates, however, the use of substrates that include, or consist essentially of, other semiconductor materials, is contemplated without departing from the spirit and scope of the present invention.


In crystalline silicon, the atoms which make up the solid are arranged in a periodic fashion. If the periodic arrangement exists throughout the entire solid, the substance is defined as being formed of a single crystal. If the solid is composed of a myriad of single crystal regions the solid is referred to as polycrystalline material. As readily understood by skilled artisans, periodic arrangement of atoms in a crystal is called the lattice. The crystal lattice also contains a volume which is representative of the entire lattice and is referred to as a unit cell that is regularly repeated throughout the crystal. For example, silicon has a diamond cubic lattice structure, which can be represented as two interpenetrating face-centered cubic lattices. Thus, the simplicity of analyzing and visualizing cubic lattices can be extended to characterization of silicon crystals. In the description herein, references to various planes in silicon crystals will be made, especially to the (100), (110), and (111) planes. These planes define the orientation of the plane of silicon atoms relative to the principle crystalline axes. The numbers {xyz} are referred to as Miller indices and are determined from the reciprocals of the points at which the crystal plane of silicon intersects the principle crystalline axes. Thus, FIGS. 2A-2C show three orientations of the crystal plane of silicon. In FIG. 2A, the crystal plane of silicon intersects the x-axis at 1 and never intersects the y or z-axis. Therefore, the orientation of this type of crystalline silicon is (100). Similarly, FIG. 2B shows (110) crystalline silicon and FIG. 2C shows (111) silicon. The (111) and (100) orientations are the two primary wafer orientations in commercial use. Notably, for any given plane in a cubic crystal there are five other equivalent planes. Thus, the six sides of the cube comprising the basic unit cell of the crystal are all considered (100) planes. The notation {xyz} refers to all six of the equivalent (xyz) planes. Throughout the description, reference will also be made to the crystal directions, especially the <100>, <110> and <111> directions. These are defined as the normal direction to the respective plane. Thus, the <100> direction is the direction normal to the (100) plane. The notation <xyz> refers to all six equivalent directions.


As discussed above, there is a need in the art for versatile and efficient methods of fabricating semiconductor heterostructures that would constrain substrate interface defects in a variety of lattice-mismatched materials systems. One conventional technique mentioned above that addresses control of threading dislocation densities in highly-mismatched deposited layers, termed “epitaxial necking,” is applicable only to devices with relatively small lateral dimensions. Specifically, in the prior art, metal oxide semiconductor (“MOS”) transistors are typically fabricated on (100) silicon wafers with the gates oriented such that current flows parallel to the <110> directions. Thus, for a FET device built on a (100) Si wafer with device channel orientation aligning with the <110> direction, both the channel width and channel length should be small compared to the height of a epitaxial necking mask, in order for the dislocations in a lattice-mismatched semiconductor layer to terminate at a sidewall of the mask on both directions. However, in modern CMOS circuits, the MOSFET device width often substantially exceeds the channel length, which, as a result of CMOS scaling, is frequently very small. Accordingly, under the conventional necking approach, a number of dislocations will not be terminated at the sidewall of the mask in the direction of the channel width.


In contrast with the prior art approach of minimizing dislocation defects, in its various embodiments, the present invention addresses the limitations of known techniques, by utilizing greater thicknesses and limited lateral areas of component semiconductor layers to produce limited-area regions having upper portions substantially exhausted of dislocation defects. Referring to FIGS. 3A-3B, a substrate 310 is provided that includes, or consists essentially of, a first semiconductor material, such as, for example, a group IV element, e.g., germanium or silicon. The first semiconductor material may be crystalline. The substrate 310 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. In one embodiment, the substrate 310 includes or consists essentially of (100) silicon. The substrate 310 may include a material having a first conductivity type, e.g., n- or p-type, such as n+ Si.


A dislocation-blocking mask 320 is disposed over the substrate. The mask has an opening 325 extending to the surface of the substrate and defined by at least one sidewall 330. In various embodiments, the opening 325 is generally rectangular. The dislocation-blocking mask may include a dielectric material, such as, for example, silicon dioxide or silicon nitride. At least a portion of the sidewall meets the surface of the substrate at an orientation angle α to a selected crystallographic direction of the first semiconductor material. In addition, at least a portion of the sidewall is generally vertical, i.e. disposed at about 80 to 120 degrees to the surface of the substrate, and, in a particular embodiment, substantially perpendicular to the surface of the substrate.


A regrowth layer 340 that includes a second semiconductor material is deposited in the opening. In one embodiment, the selected crystallographic direction of the first semiconductor material is aligned with direction of propagation of threading dislocations in the regrowth layer. In certain embodiments, the orientation angle ranges from about 30 to about 60 degrees, for example, is about 45 degrees to such crystallographic direction. The surface of the substrate may have (100), (110), or (111) crystallographic orientation. In some embodiments, the selected crystallographic direction is substantially aligned with a <110> crystallographic direction of the first semiconductor material.


In various embodiments, the first semiconductor material may include, or consist essentially of, silicon or a silicon germanium alloy. The second semiconductor material may include, or consist essentially of, a group II, a group III, a group IV, a group V, and/or a group VI element, and/or combinations thereof, for example, selected from the group consisting of germanium, silicon germanium, gallium arsenide, aluminum antimonide, indium aluminum antimonide, indium antimonide, indium arsenide, indium phosphide, and gallium nitride.


The regrowth layer can be formed in the opening by selective epitaxial growth in any suitable epitaxial deposition system, including, but not limited to, atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD), by molecular beam epitaxy (MBE), or by atomic layer deposition (ALD). In the CVD process, selective epitaxial growth typically includes introducing a source gas into the chamber. The source gas may include at least one precursor gas and a carrier gas, such as, for example hydrogen. The reactor chamber is heated, such as, for example, by RF-heating. The growth temperature in the chamber ranges from about 300° C. to about 900° C. depending on the composition of the regrowth layer. The growth system also may utilize low-energy plasma to enhance the layer growth kinetics.


The epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. Suitable CVD systems commonly used for volume epitaxy in manufacturing applications include, for example, EPI CENTURA single-wafer multi-chamber systems available from Applied Materials of Santa Clara, Calif., or EPSILON single-wafer epitaxial reactors available from ASM International based in Bilthoven, The Netherlands.


In some embodiments, the regrowth layer is compositionally graded, for example, includes Si and Ge with a grading rate in the range of >5% Ge/μm to 100% Ge/μm, preferably between 5% Ge/μm and 50% Ge/μm, to a final Ge content of between about 10% to about 100% While the overall grading rate of the graded layer is generally defined as the ratio of total change in Ge content to the total thickness of the layer, a “local grading rate” within a portion of the graded layer may be different from the overall grading rate. For example, a graded layer including a 1 μm region graded from 0% Ge to 10% Ge (a local grading rate of 10% Ge/μm) and a 1 μm region graded from 10% Ge to 30% Ge (a local grading rate of 20% Ge/μm) will have an overall grading rate of 15% Ge/μm. Thus, the regrowth layer may not necessarily have a linear profile, but may comprise smaller regions having different local grading rates. In various embodiments, the graded regrowth layer is grown, for example, at 600-1200° C. Higher growth temperatures, for example, exceeding 900° C. may be preferred to enable faster growth rates while minimizing the nucleation of threading dislocations. See, generally, U.S. Pat. No. 5,221,413, incorporated herein by reference in its entirety.


In a particular embodiment, the first semiconductor material is silicon and the second semiconductor material is germanium. In this embodiment, threading dislocations 350 in the regrowth layer propagate along a <110> direction, and lie at an angle of 45-degrees to the surface of the first semiconductor material. The dislocation mask having a generally rectangular opening is disposed over the substrate such that the sidewall of the opening is disposed at a 45-degree angle to a <100> direction and is substantially aligned with a <110> crystallographic direction. As a result of such orientation of the opening, dislocations will reach and terminate at the sidewalls of the opening in the dislocation-blocking mask at or below a predetermined distance H from the surface of the substrate, such that threading dislocations in the regrowth layer decrease in density with increasing distance from the surface of the substrate. Accordingly, the upper portion of the regrowth layer is substantially exhausted of threading dislocations, enabling formation of semiconductor devices having increased channel width.


In certain versions of this and other embodiments of the invention, the sidewall of the opening in the dislocation-blocking mask has a height at least equal to a predetermined distance H from the surface of the substrate. In these embodiments, the opening is substantially rectangular and has a predetermined width W that is smaller than a length L of the opening. For example, the width W of the opening can be less than about 500 nm, and the length L of the opening can exceed each of W and H. In some versions of these embodiments, the substrate consists essentially of silicon and has a (100) crystallographic orientation, the orientation angle is about 45 degrees to propagation of dislocations in the regrowth layer, and the predetermined distance H is at least W √2. In other versions, the substrate consists essentially of silicon and has a (110) crystallographic orientation, the orientation angle is about 45 degrees, and the predetermined distance H is at least W √6/3. In still other versions, the substrate consists essentially of silicon and has a (111) crystallographic orientation, the orientation angle is about 45 degrees, and the predetermined distance H is at least 2W.


In various embodiments of the invention, blocking of the dislocations is promoted both by geometry and orientation of the mask discussed above as well as because of the ‘image force’ whereby dislocations are attracted to substantially vertical surfaces, as explained in more detail below. In many embodiments, the image force alone is sufficient to cause the upper portion of the regrowth layer to be substantially exhausted of threading dislocations and other dislocation defects.


As skilled artisans will readily recognize, a dislocation near a surface experiences forces generally not encountered in the bulk of a crystal, and, in particular, is attracted towards a free surface because the material is effectively more compliant there and the dislocation energy is lower. See Hull & Bacon, Introduction to Dislocations, 4th edition, Steel Times (2001). Image force is determined by material properties of the semiconductor being grown, as well as the distance between a given dislocation and the free surface. Thus, even when the dislocations have an orientation that does not favor trapping at sidewalls, the approach discussed above is still effective at certain dimensions because of the boundary forces that draw dislocations to free surfaces in order to reduce the elastic energy of the crystal. Mathematically, these forces arise because the boundary conditions of the expressions for strain require strain components normal to a surface to be zero at that surface. Thus, force per unit of dislocation length on an edge dislocation, toward a vertical sidewall can be represented by the formula:







F
I

=


Gb
2


4

π






d


(

1
-
v

)









where


F1=Image force


G=Shear modulus


d=distance from free surface


b=Burgers vector


ν=Poisson's ratio


Referring to FIGS. 4A-4B, as used herein, the term “60° dislocation” refers to a dislocation for which the angle between the Burgers vector and the dislocation line is 60°. These dislocations typically form in diamond-cubic or zincblende lattice-mismatched systems where the strain is relatively low (e.g. <2%). In the absence of forces on threads (which can come from other dislocations nearby or from a free surface nearby) they rise from the substrate surface at a 45° angle in <110> directions. However, when viewed from above (normal to the surface) they appear to lie in <100> directions.


Experimentally, it has been shown that for the case of germanium on silicon (4% mismatch) dislocations within approximately 300 nm of a SiO2 sidewall are trapped. This is understood to be due to the influence of the image force. The angle between these dislocations and the sidewall appears to range between approximately 45-55°.


The relevant material constants for Ge are:


G=4.1e11 dyne/cm2


ν=0.26; and


b=3.99 Å


Based on the above formula and the experimental observation that for d≦300 nm dislocations in Ge on Si are bent toward an SiO2 sidewall, the force necessary to bend a dislocation in a cubic semiconductor crystal toward a free surface is approximately 2.3 dyne/cm. Thus, distance from free surface d for other materials can be estimated with certain degree of accuracy based on their known values for G, ν, and b. For example, by these calculations:


For GaAs d=258 nm


For InP d=205 nm


For AlSb d=210 nm


For InSb d=164 nm


Referring to FIG. 4C, for full trapping, the hole or trench lateral dimension w is preferably less than or equal to approximately 2*d, while the vertical dimension h is preferably at least approximately d, where d is calculated discussed above. These criteria are expected to be substantially independent of the orientation of the boundary of the sidewall and the substrate surface. Thus, in various embodiments of the invention, dislocations in the lower portion of the regrowth layer are trapped by employing a dislocation-blocking mask with an elongated opening, e.g. a trench, having a width calculated as discussed above and oriented without any regard for the direction of propagation of dislocations in the regrowth layer.


Further, as shown in FIG. 4D and used herein, the term “90° dislocation” refers to a dislocation for which the angle between the Burgers vector and the dislocation line is 90°. These dislocations primarily form in mismatched systems where the strain is relatively high (e.g. >2%). In the absence of forces on threading dislocation (which can come from other dislocations nearby or from a free surface nearby) they rise from the substrate surface at a 90° angle in <100> directions. Thus, these dislocations can be trapped most optimally by using a dislocation-blocking mask with slanted, rather than vertical sidewalls, as shown in FIG. 4E.


The following summarizes mechanisms for trapping dislocations in different kind of diamond-cubic or zincblende semiconductor heterostructures:


1. Low mismatch, low image force

    • 60° dislocations predominate
    • Threads lie in <110> directions, rising from surface at 45°
    • Best approach for trapping dislocations is to rely on appropriate orientation of sidewalls and appropriate dimensioning of openings, as described above in connection with FIGS. 3A-3B;


2. Low mismatch, high image force

    • 60° dislocations predominate
    • Threads bend toward free substantially vertical surfaces
    • Best approach for trapping dislocations is described above in connection with FIGS. 4A-4C;


3. High mismatch, high image force

    • 90° dislocations predominate
    • Threads bend toward free substantially vertical surfaces
    • Best approach for trapping dislocations is described above in connection with FIGS. 4A-4C; and


4. High mismatch, low image force

    • 90° dislocations predominate
    • Threads lie in <100> directions, rising from surface at 90°
    • Best approach for trapping dislocations is described above in connection with FIGS. 4D-4E


Hexagonal semiconductors, such as the III-nitride (III-N) materials, are of great interest for high-power high-speed electronics and light-emitting applications. For epitaxy of hexagonal semiconductors such as III-nitrides on Si, the (111) surface of Si is commonly preferred over the (100). This is because the (111) surface of Si is hexagonal (even though Si is a cubic crystal). This makes a better template for hexagonal crystal growth than the cubic (100) face. However, as mentioned above, epitaxial necking approach discussed above is less effective in these applications, because the threading dislocations in the hexagonal semiconductors disposed over the lattice-mismatched Si (111) substrates may not be effectively confined by the vertical sidewalls because the threading dislocations in such materials typically have a different orientation relative to the substrate, compared to the more commonly used cubic semiconductors, such as Si, Ge, and GaAs. For example, as described above in connection with FIG. 4E, for certain surface orientations of substrate and crystalline structure of lattice-mismatched regrowth region, the threading defects tend to propagate perpendicular to the substrate, which may not favor trapping by vertical sidewalls of the dislocation-blocking mask. This is the case when GaN is grown on the (100) surface of Si. In such a case, in some embodiments, the angle of the sidewalls of the opening can be slanted relative to the substrate, as shown in FIG. 4E such that vertically propagating defects intersect the angled sidewalls.


In other embodiments, the surface of the underlying substrate itself exposed in the opening is configured to enable confinement of the threading dislocations. Referring to FIG. 5A, after the dislocation-blocking mask is disposed over the Si (100) substrate and an opening is defined therethrough, an etch that is selective to the (111) crystallographic plane of Si, for example, a KOH solution, is applied to the portion of the substrate exposed at the bottom of the seed window to expose (111) surfaces. A lattice-mismatched semiconductor material is then deposited in the opening over the substrate, and the epitaxial deposition continues such that a heteroepitaxial region is grown over the material disposed in the opening, laterally expanding over the mask. Because of the configuration of the underlying surface, orientation of the threading dislocations in the heteroepitaxial region is at approximately 45° to the surface of the substrate, facilitating trapping of the dislocation by substantially vertical sidewalls of the mask, as shown in FIG. 5B. Then, if small areas of hexagonal semiconductor material are desired for device active areas, the heteroepitaxial overgrowth regions expanding from the individual openings can be planarized (e.g. via CMP), to be substantially co-planar with the adjacent insulator areas. Alternatively, if a large area is desired, growth can proceed until neighboring regions coalesce, followed optionally by planarization of the resulting structure. In the latter case, because lateral growth rates of hexagonal semiconductor can be dramatically increased over growth rate normal to the surface employing various known approaches, these semiconductor materials afford process flexibility not available with cubic semiconductors grown on (100) surfaces. Specifically, differential growth rates of these materials allows for widely-spaced seed trenches; for example, spacing may be five times trench width or even greater, offering a substantial advantage over closely-spaced seed trenches, if the defects which are known to form when epitaxial growth fronts coalesce cannot be substantially eliminated.



FIGS. 6A-6F depicts schematic cross-sectional side views of the lattice-mismatched semiconductor heterostructures having increased surface area according to various embodiments of the invention. Specifically, as discussed in more detail below, the area of the upper portion of the lattice-mismatched heterostructure substantially exhausted of threading dislocations is increased, compared to the embodiments described above with reference to FIGS. 3A-3B. For example, as described in more detail below, in some embodiments, the opening in the dislocation-blocking mask has a variable width. In other versions, the sidewall of the opening in the dislocation-blocking mask includes a first portion disposed proximal to the surface of the substrate, and a second portion disposed above the first portion. A height of the first portion can be at least equal to a predetermined distance H from the surface of the substrate, where the threading dislocations terminate at the sidewall of the opening in the dislocation-blocking mask at or below the distance H. In some versions of these embodiments, the first portion of the sidewall can be substantially parallel to the second portion. Also, in some versions, the second portion of the sidewall is flared outwardly.


In many of the embodiments described below, a substrate 510 includes, or consists essentially of, silicon. The regrowth layer includes, or consists essentially of, a semiconductor material that is one of a group II, a group III, a group IV, a group V, and/or a group VI elements, and/or combinations thereof, for example, selected from the group consisting of germanium, silicon germanium, gallium arsenide, aluminum antimonide, indium aluminum antimonide, indium antimonide, indium arsenide, indium phosphide and gallium nitride. A dislocation-blocking mask 520 having an opening therein is disposed over the substrate. The dislocation-blocking mask may include a dielectric material, such as, for example, silicon dioxide or silicon nitride. At least a portion of the sidewall meets the surface of the substrate at an orientation angle α to a selected crystallographic direction of the first semiconductor material. A regrowth layer 540 that includes a second semiconductor material is deposited in the opening. In various embodiments, the selected crystallographic direction of the first semiconductor material is aligned with direction of propagation of threading dislocations in the regrowth layer. In various embodiments, the orientation angle ranges from about 30 to about 60 degrees, for example, is about 45 degrees. As mentioned above, in many embodiments of the invention, blocking of the dislocations is promoted by geometry and orientation of the mask discussed above and/or the ‘image force.’


Referring to FIG. 6A, in one embodiment, the dislocation-blocking mask is formed by depositing a first low-temperature oxide layer 521 having thickness h1 over the substrate. The thickness h1 is selected to be at least equal to the distance from the surface of the substrate at which the threading dislocations (and/or other dislocation defects such as stacking faults, twin boundaries, or anti-phase boundaries) terminate at the sidewall of the opening in the dislocation-blocking mask, as discussed above. A first aperture having a diameter d1 or a first trench having a width w1, both the width w1 and diameter d1 being smaller than the thickness h1, are formed in the layer 521 by a conventional masking/etching technique. After the mask is stripped, a second low-temperature oxide layer 522 having a thickness h2 is deposited over the layer 521. Then, a second aperture of diameter d2 or a second trench having a width w2 is formed in the layer 522 by a conventional masking/etching technique, such that w1<w2 (or d1<d2). After the mask is stripped, the regrowth layer of second semiconductor material is deposited in the first and second apertures or in first and second trenches by selective epitaxy, according to any of the techniques disclosed in U.S. Patent Application Publication No. 2004/0045499A by Langdo et al., incorporated herein by reference. As discussed above, following deposition, threading dislocations and/or other dislocation defects substantially terminate in the first aperture (or in the first trench) at or below thickness h1. As a result, the regrowth layer portion having thickness h2 that is substantially exhausted of threading dislocations is obtained with an upper surface that is larger compared to the embodiments described above with reference to FIGS. 3A-3B.


Referring to FIG. 6B, in another embodiment, an overgrowth layer 555 that includes the second semiconductor material is deposited over the regrowth layer 540 and over a portion of the dislocation-blocking mask 520 adjacent to the regrowth layer. At least a portion of the overgrowth layer may be deposited as non-crystalline (i.e. amorphous) material and can be crystallized subsequently, for example by an anneal step at a temperature higher than the deposition temperature. Thus, in this embodiment, crystallization of the overlayer is used to create crystal material in the overlayer regions over the regrowth layer, which is amorphous upon deposition. The arrows in FIG. 6B indicate a crystallized region expanding outward from the opening in the dislocation blocking mask, as amorphous material which may form at least a portion of the overgrowth layer 555 is crystallized.


Referring to FIG. 6C, in yet another embodiment, deposition of the regrowth layer in the opening of the dislocation-blocking mask is followed by a step of lateral epitaxial deposition to increase the useful surface area. It may also utilize the higher growth rates typical of (100) surfaces compared to (110) or (111) surface to increase lateral overgrowth in this embodiment. For example, the overgrowth regions can be used as source/drain areas which typically have less stringent material quality requirement than the channel material.


Referring to FIG. 6D, in still another embodiment, the useful upper area of the regrowth layer 540 is increased by gradually increasing the size of the regrowth region. Similar to the embodiment described above with reference to FIG. 6A, the dislocation-blocking mask includes two layers—a first layer having thickness h1, and a second layer having thickness h2. The thickness h1 is selected to be at least equal to the distance from the surface of the substrate at which the threading dislocations and/or other dislocation defects terminate at the sidewall of the opening in the dislocation-blocking mask, as discussed above. That is, a first aperture having a diameter d1 or a first trench having a width w1, both the width w1 and diameter d1 being smaller than the thickness h1, are formed in the layer 521 by a conventional masking/etching technique. After the mask is stripped, a second low temperature oxide layer 522 having a thickness h2 is deposited over the layer 521. Then, a second aperture of diameter d2 or a second trench having a width w2 is formed in the layer 522 by a conventional masking/etching technique, such that w1<w2 (or d1<d2). In contrast to the embodiment depicted in FIG. 6A, however, the width w2 of the second trench is gradually increased such that the sidewall of the trench, i.e. the opening in the layer 522, gradually flares outwardly. This effect can be achieved, for example, by conventional masking/etching techniques wherein the etchant and masking material are chosen such that the masking material is eroded laterally during the etching process, gradually exposing more of the dislocation-blocking mask below, resulting in an opening in the dislocation-blocking mask that flares outward. For example, the masking material could be conventional photoresist and the etchant could be a mixture of the gases CF4 and H2, used in a conventional RIE system. After the mask is stripped, the regrowth layer of second semiconductor material is deposited by selective epitaxy in the opening defined by the layers 521, 522. As discussed above, following deposition, threading dislocations (and/or other dislocation defects such as stacking faults, twin boundaries, or anti-phase boundaries) substantially terminate in the first aperture (or in the first trench) at or below thickness h1. Thus, in this embodiment, the dislocations are terminated in the first portion of the regrowth region at or below thickness h1, and then the regrowth layer becomes larger and larger gradually, allowing for high-quality epitaxial growth with large surface area for large device fabrication.


Referring to FIG. 6E, in an alternative version of the embodiment discussed above in connection with FIG. 6D, a dislocation-blocking mask having an opening with outward slanted sidewalls, i.e. the structure that is substantially narrower at the bottom than the top, can be formed with only one lithography step, followed by spacer deposition and etch. This technique is generally more economical and may overcome lithographic alignment problems, or lithographic minimum feature limitations, inherent with the lithography-and-etch approach. The spacers can be formed from the same or different material than the insulator layer. For either case, selective epitaxial growth follows creation of the opening or trench.



FIGS. 6F-6H show further techniques to increase the surface area. Referring to FIG. 6F (as well as, again, to FIG. 6B), in one embodiment, silicon nitride is utilized instead of silicon dioxide as a dielectric material for the dislocation-blocking mask 520 that defines two openings 535. After the regrowth regions 540 are epitaxially grown in the openings, overgrowth regions 560 are deposited thereover. Using silicon nitride facilitates merging two overgrown regions on the surface of dislocation-blocking mask 520 layer with fewer defects, resulting in larger surface area. Referring to FIG. 6G, in one particular version of the embodiment of FIG. 6F, a layer of second semiconductor material 570 is deposited over the substrate 510 before forming the dislocation-blocking mask 520 thereon, such that the regrowth regions 540 merge at the top of the dislocation-blocking mask with pre-defined lattice spacing. This lattice spacing in the regrowth regions follows the lattice spacing of the layer 570 and thus it has less lattice misalignment when two epitaxy structures merge. Referring to FIG. 6H, in another version of the embodiment of FIG. 6F, the dislocation-blocking mask defines two or more closely spaced flared openings, such that a horizontal top surface of the mask is minimized or, in certain implementations, eliminated. In this version, the lateral overgrowth region, often prone to defects, is negligible or altogether absent, thereby improving the quality of the resulting merged overgrowth region.


Further, referring to FIGS. 7A-7C, in some embodiments, the invention focuses on creating large active areas within the heteroepitaxial region by a combination of epitaxial necking and ELO techniques, employing a self-assembled dislocation-blocking mask. Specifically, a dielectric layer defining an array of openings therethrough can be formed using self-assembly techniques, thereby avoiding traditional time-consuming lithography and etch approaches. For an example of how a self-assembled array of vertical openings in an insulator layer could be created on a Si substrate, see an article by Wenchong Hu et al. entitled “Growth of well-aligned carbon nanotube arrays on silicon substrates using porous alumina film as a nanotemplate,” published in Applied Physics Letters, Vol. 79, No. 19 (2001) and incorporated herein by reference, describing how anodic oxidation of the aluminum can be used to create a self-assembled array of vertical openings similar to that shown in FIG. 7A-7B, where the insulator is alumina (Al2O3). The process described by Hu et al., however, leaves a small residual layer of alumina at the bottom of each hole. To remove this residual layer, an anisotropic dry etch (much higher etch rate normal to the wafer surface than parallel to the wafer surface) could be performed, exposing the silicon which is the ‘seed’ for subsequent epitaxial necking. Then, heteroepitaxial regions are selectively grown within and out of the openings, at least until resulting overgrowth regions coalesce. Depending on lateral dimensions of the aperture, degree of mismatch, and rigidity of sidewall oxide, either plastic or elastic relaxation of the heteroepitaxial “pillars” may dominate. The resulting heteroepitaxial layer is then planarized (FIG. 7C), e.g. via CMP, and the active-area, substantially exhausted of threading dislocations and/or other dislocation defects is used for device fabrication.



FIGS. 8-10 depict various applications of dislocation-blocking techniques according to various embodiments of the invention for fabrication of CMOS devices. FIG. 8 shows various device structures disposed over regrowth or overgrown regions fabricated according to the invention, such as MOSFET devices including Ge, InGaAs, strained Ge/SiGe and other materials, or HEMT devices, e.g. including InGaAs. The starting substrate can be Si substrate or SOI/SSOI substrate. In one example, n-FET and p-FET digital devices are fabricated on a SSOI substrate, while RF/analog devices are fabricated over a Ge region grown over the Si substrate using the approaches discussed above. By integrating advanced materials into Si substrate, electron and hole mobility can be enhanced significantly. In order to avoid the deleterious effects of dislocations defects on such FET devices, the channel, source, and drain region should be confined to an upper region of regrowth or overgrown material which is substantially defect-free. As discussed in detail above, blocking of the threading dislocations and other defects is promoted by geometry and orientation of the mask and/or the image force. In many embodiments, the image force alone is sufficient to cause the upper region of the regrowth or overgrown material to be substantially exhausted of threading dislocations and other dislocation defects.


Furthermore, still referring to FIG. 8, a wide bandgap material which will suppress junction leakage (such as AlSb) can be used for initial growth, followed by a material with high electron mobility for the FET channel (such as InAs). In this embodiment, preferably, the two semiconductor materials have similar lattice constants, to reduce the possibility of dislocations forming at the interface between them. Also in this embodiment, the growth of the wide bandgap material may be followed by a planarization step so that its surface is substantially planar with the top of the dislocation blocking mask; subsequently a thin layer of the high-mobility material can be grown to accommodate the MOS channel. Preferably, the bottom of the FET junctions is disposed within the wide bandgap region to suppress junction leakage.



FIG. 9 depicts another application of the dislocation-blocking techniques according to various embodiments of the invention in CMOS. This method allows the Ge/III-V necking technique to be used in relatively large CMOS devices. When applying the dislocation-blocking technique in a CMOS device as in the embodiment of FIG. 8, the length of device active region Lactive should be small enough to satisfy the aspect ratio requirement discussed above. Lactive, which includes source/drain lengths as well, is, however, much larger than the device channel length Lg. The embodiment shown in FIG. 9 addresses a situation where Ge or GaAs growth is performed at a narrow channel region only; source/drain materials are then deposited separately. This approach allows for Ge or GaAs growth techniques to be applied to much larger devices, for example, 90 nm node CMOS devices instead of 22 nm node devices. This channel-only Ge/III-V dislocation-blocking approach may also be combined with other desirable source/drain engineering techniques, such as raised source/drain techniques, Schottky source/drain approaches, or the use of materials on the source/drain region different from the material in the channel region for source/drain dopant/conductivity optimization. The quasi source/drain “on-insulator” structure also reduces the junction capacitance. Proper deposition of source/drain materials may also introduce localized strain in the channel region for mobility enhancement purpose. The approach discussed above can be applied to pre-defined small channel regions only. The epitaxial deposition in the source/drain regions may be defective, but as long as the dislocations terminate on the sidewalls of the narrow channel region, the defect density in source/drain is acceptable.


Besides the conventional planar MOSFETs, the dislocation-blocking technique of the invention can also be used to fabricate non-planar FETs. As mentioned above, blocking of the threading dislocations and other defects is promoted by geometry and orientation of the mask and/or the image force. In many embodiments, the image force alone is sufficient to cause the upper region of the regrowth or overgrown material to be substantially exhausted of threading dislocations and other dislocation defects. FIGS. 10A and 10B show body-tied finFETs or tri-gate transistor structures which takes the advantage of the vertical shape of the lattice-mismatched material. One exemplary method includes depositing or growing an oxide layer, followed by depositing a nitride layer, masking and etching a trench of width w<0.5h; (the trench orientation may be in a <110> direction, so all the threading dislocations along <110> directions (which will lie at an angle of 45-degrees to the surface of the first semiconductor material) will intersect sidewalls within the height of h); selectively growing Ge or III-V in the trench; chemical-mechanical polishing to remove the portion of selective growth outside of the trench; selectively removing nitride, which results in fin structures; and then growing and/or depositing insulator material around the fin structures; followed by depositing, masking and etching gate electrodes and ion implantation to create source/drain regions. A second exemplary method includes depositing or growing an oxide layer, masking and etching a trench of width w<0.5h; selectively growing Ge or III-V in the trench; chemical-mechanical polishing to remove the portion of selective growth outside of the trench; selectively removing a portion of the oxide, which results in fin structures; and then growing and/or depositing insulator material around the fin structures; followed by depositing, masking and etching gate electrodes and ion implantation to create source/drain regions.


Besides FET devices, the dislocation-blocking techniques of the invention can also be used to fabricate other types of devices, such as optical devices. Referring to FIGS. 11-12, in some embodiments, Ge or III-V photodetectors are integrated into a Si substrate using such techniques. In an exemplary embodiment shown in FIG. 11, a lower contact is implanted on a Si substrate to form p+-type region; low-temperature oxide is deposited; apertures or trenches are etched through the low-temperature oxide layer to explore the Si substrate; and Ge or III-V materials are selectively grown on the apertures or trenches with in-situ doping until past the defect regions (p-type). Further, epitaxial growth continues until the thickness is sufficient to allow for desirable levels of absorption of incident light, and then the top layer is implanted to form an n-type region. In another configuration, the light comes from the side (e.g. from in-plane waveguide) instead of from the top, as shown in FIG. 12. This allows light detection to occur in-plane with the wafer surface and also to allow growth thickness to be independent of absorption depth.


In various embodiments described above, the dislocation-blocking is performed in a vertical direction. FIG. 13A shows an alternative embodiment where the dislocation-blocking may conduct in a lateral direction, for example from the source or drain region. Therefore, the device can be an SOI structure. In one embodiment, the gate oxide and gate stack can be formed first, before the dislocation-blocking growth under the gate, using a channel-replacement-type process. This approach addresses the self-alignment issue and any surface roughness issues.



FIG. 13B shows another method which allows dislocations be terminated for a large size epitaxial area. The method includes two steps of epitaxial growth, which take different growth directions, so that the dislocations in one direction terminate at the sidewall during the first epitaxial growth, and the dislocations in another direction, which may have large device dimensions, can terminate on the sidewall when the epitaxial growth changes the direction.


Conventional Ge/III-V necking forms crystal material in the vertical direction. Therefore, when building planar MOS or finFET type devices on that crystal, the device is typically a bulk-type or body-tied, not an “on-insulator” structure. Bulk-type of Ge or GaAs FET may exhibit large junction leakage and poor short-channel effect control. One solution is to build the device vertically instead of parallel to horizontal surface. FIG. 13C shows one embodiment of such structure: a vertical-channel FET, which incorporates the benefits that a vertical FET has, for example, SCE control, better scalability, etc. Another approach is to epitaxially grow an oxide layer that is lattice-matched to the second semiconductor material during selective deposition of the second semiconductor material. As result, there is an oxide layer within the regrowth region underlying a portion thereof subsequently used for device fabrication, as discussed in more detail in co-pending U.S. patent application Ser. No. 11/000,566 by Currie, incorporated herein by reference.



FIGS. 14-16 illustrate a method, in accordance with embodiments of the current invention, for reducing defects in lattice-mismatched semiconductor heterostructures by forming a recess or groove in a substrate, and also illustrate devices formed in accordance with the method. FIG. 14A shows a semiconductor structure 1400 that includes a substrate 310 and a dielectric layer 1404 disposed thereover. As discussed previously, with reference to FIGS. 3A-3B, the substrate 310 may include, or consist essentially of, a first semiconductor material, such as, for example, a group IV element, e.g., germanium or silicon. The first semiconductor material may be crystalline. The substrate 310 may be, for example, a bulk silicon wafer, a bulk germanium wafer, a semiconductor-on-insulator (SOI) substrate, or a strained semiconductor-on-insulator (SSOI) substrate. In one embodiment, the substrate 310 includes or consists essentially of (100) silicon. The substrate 310 may include a material having a first conductivity type, e.g., n- or p-type, such as n+ Si.


The dielectric layer 1404 may be formed over the substrate 310. The dielectric layer 1404 may include or consist essentially of a dielectric material, such as silicon nitride or silicon dioxide (SiO2). The dielectric layer 1404 may be formed by any suitable technique, e.g., thermal oxidation or plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the height h1 of the dielectric layer 1404 may be in the range of, e.g., 25-1000 nm. In a preferred embodiment, the height h1 is approximately 600 nm.


An opening or trench 1406 may be formed in the dielectric layer 1404, exposing a portion 1408 of the surface of the substrate 310. More than one opening 1406 may be formed, and each opening 1406 may have a height equal to the height of the dielectric layer, e.g., height h1, and a width w1. The opening(s) 1406 may be created by forming a mask, such as a photoresist mask, over the substrate 310 and the dielectric layer 1404. The mask may be patterned to expose a portion of the dielectric layer 1404. The exposed portion of the dielectric layer 1404 may be removed by, for example, reactive ion etching (RIE) to define the opening 1406. The opening 1406 may be defined by at least one sidewall 1407. In one embodiment, the opening 1406 is formed within the substrate 310, and the dielectric sidewall 1407 is formed within the opening 1406.


The opening 1406 may be substantially rectangular in terms of cross-sectional profile, a top view, or both. With respect to a top view, the width w1 may be smaller than the length l1 (not shown) of the opening. For example, the width w1 of the opening 1406 may be less than about 500 nm, e.g., about 10-500 nm, and the length l1 of the opening 1406 may exceed w1. The ratio of the height h1 of the opening to the width w1 of the opening 1407 may be ≧0.5, e.g., ≧1. The opening sidewall 1407 may not be strictly vertical.


Referring to FIG. 14B and also to FIG. 5A, a portion 1408 of the surface of the substrate 310 may be removed by, e.g., etching, to form a recess or groove 1410. The recess 1410 may be formed by wet etching the substrate 310 with, for example, KOH or NaOH, or by dry etching, such as plasma etching. In one embodiment, the surface 1412 in the recess 1410 features non-(100) surfaces, such as (111) semiconductor surfaces, e.g., (111) Si surfaces. The recess 1410 may have a maximum depth d corresponding to its deepest point farthest from the substrate surface and may have a v-shaped profile. The ratio of the height of the dielectric layer 1404 plus the maximum depth of the recess 1410 to the width of the opening may be greater than or equal to one, i.e., (h1+d1)/w1≧1.


In one embodiment, and with reference also to FIG. 6H, another portion of the dielectric layer 1404 may be partially removed with, for example, a hydrofluoric acid etch. A portion of the dielectric layer 1404 distal to the substrate 310 may be removed at a faster rate than a portion proximate the substrate 310, creating a non-vertical sidewall 1414. The remaining portion of the dielectric layer 1404 may resemble an inverted V when viewed in cross-section. In one embodiment, the sidewall 1414 is substantially parallel to the surface 1412 of the opening 1410. In another embodiment, a horizontal portion 1416 of the dielectric layer 1404 remains after the etch, and the width w2 of the horizontal portion 1416 is much less than the width w of the opening 1406.



FIG. 14C shows an alternative embodiment of the current invention in which the dielectric layer 1404 is removed from the substrate 310 after the formation of the recess(es) 1410. The dielectric layer 1404 including SiO2 may be removed with, for example, a hydrofluoric acid etch. This embodiment of the invention may be suitable for the growth of III-nitride semiconductor layers or layers of other semiconductor materials having hexagonal lattice structures. Any dislocation defects that form in a III-nitride material (or other suitable material) deposited on the surface of the substrate 310 may form perpendicularly to the opening surfaces 1412, rather than vertically, as the defects may typically form. The non-vertical formation of the defects may, therefore, create defect-free regions in the deposited material. In an alternative embodiment, the recesses 1410 improve the formation of GaAs (or other semiconductor materials having cubic or zinc blende lattice structures) heteroepitaxial structures.



FIG. 15A illustrates an embodiment of the current invention in which the dielectric layer 1404 is not removed from the substrate 310 after the formation of the recess(es) 1410. A second crystalline semiconductor material 1500, which is lattice-mismatched to the first crystalline semiconductor material in the substrate 310, may be formed within the recess 1410. In one embodiment, the second crystalline semiconductor material 1500 may be further formed within the opening 1406. The second crystalline semiconductor may be formed by, for example, metal-organic chemical vapor deposition (MOCVD) or molecular-beam epitaxy (MBE). The second crystalline semiconductor material 1500 may be a III-V material, such as GaAs or InP, a type-IV material, such as Ge or SiGe, or an alloy or mixture including any of these materials, such as InGaP. In one embodiment, an etch-stop layer (not shown), including a wide band-gap material, may be formed on top of the second crystalline semiconductor material 1500. Dislocation defects 1502 may form in the second crystalline semiconductor material 1500 near the interface 1504 between the substrate 310 and the second crystalline semiconductor material 1500. The defects may form along the (111) direction, which may be parallel to the surface 1412 of the substrate 310. The defects may terminate at a height H1 above the deepest point of the recess 1410. In one embodiment, the defects terminate within the recess 1410, and H1≦d1. In another embodiment (e.g., the embodiment illustrated in FIG. 15A), the defects terminate within the opening 1406, and H1≦h1+d1. In a third embodiment, the defects terminate at a height H1 that is less than or equal to the width w1.


The recess 1410 may effectively increase the height h of the opening 1406. The surfaces 1412 along the interface 1504 may define an angle 1501 with the horizontal of approximately 57 degrees. The depth d may thus be equal to tan(57°)×w1/2, and the effective height may be equal to h1+tan(57°)×w1/2. The height h1 may be effectively increased regardless of the material to be grown in the opening 1406. In one embodiment, the recess 1410 allows a reduction in the height h1 because the effective increase of h1 may cause any dislocation defects to terminate at a lower height above the substrate 310.


In one embodiment, the second crystalline semiconductor material 1500 does not extend above the height h of the dielectric layer 1404. In an alternative embodiment, the second crystalline semiconductor material 1500 extends above the height h of the dielectric layer 1404, and may coalesce with the second crystalline semiconductor material grown in a neighboring opening 1406 to form a single layer of the second crystalline semiconductor material 1500 above the dielectric layer 1404.


In one embodiment, a buffer layer 1503, comprising a third crystalline semiconductor material, is formed between the second crystalline semiconductor material 1500 and the substrate 310. The buffer layer may be formed on the surface 1412 of the substrate 310, and extend approximately up to the dielectric layer 1404. In another embodiment, the buffer layer 1503 is confined to the recess 1410. The boundary between the second 1500 and third 1503 crystalline semiconductor materials may be proximate the boundary defined by the interface between the exposed portion of the substrate 310 and the dielectric sidewall 1407. The buffer layer 1503 may be used to facilitate the formation of the second crystalline semiconductor material 1500 if there is a large difference between the lattice constants of the second crystalline semiconductor material 1500 and of the substrate 310. For example, the substrate 310 may include Si and the second crystalline semiconductor material 1500 may include InP, so that the two materials differ in lattice constants by approximately eight percent. In this example, GaAs may be used as the buffer layer, because its lattice constant differs from that of both Si and InP by approximately four percent. In another embodiment, Ge or another material having a lattice mismatch to the first and/or second crystalline semiconductor materials of less than eight percent may be used as a buffer layer.


In one embodiment, the buffer layer 1503 may include a constant concentration of the third crystalline semiconductor material, or the concentration may vary such that the lattice constant of the buffer layer 1503 is closer to that of the substrate 310 at the bottom of the buffer layer and closer to that of the second crystalline semiconductor material 1500 near the top of the buffer layer. In another embodiment, multiple buffer layers may be used. The use of one or more buffer layers may allow the formation of one or more heteroepitaxial material layers with large lattice-constant mismatches, while reducing the height h of the dielectric layer 1404 and/or depth d of the recess 1410. The heteroepitaxial material layers may be formed inside the openings 1406 or above the dielectric layer 1404.



FIG. 15B illustrates that, in one embodiment, the second crystalline semiconductor material 1500 may be planarized by, for example, CMP. A substantially smooth surface 1506 may be formed as a result of the planarization. The upper portion 1508 of the second crystalline semiconductor material 1500 may be substantially free of defects.



FIG. 15C shows, in one embodiment of the current invention, a device structure 1510 formed on the surface 1506 of the second crystalline semiconductor material 1500. In an alternative embodiment, the device structure 1510 is wholly or partially formed within the opening 1406. The device structure 1510 may include a diode; a transistor; a photonic device such as a photovoltaic device, LED, or laser diode; or any other passive or active semiconductor device. The device structure 1510 may include a single layer of a semiconductor material, or may include more than one layer. Each layer may include or consist essentially of a type-IV semiconductor material or a III-V semiconductor material. In one embodiment, semiconductor devices may be formed in regions of the substrate 310 proximate the device structure 1510.



FIG. 15D depicts, in one illustrative embodiment, a flip-chip wafer bonding process. A thin metal layer 1512 may first be formed on top of the device structure 1510. The thin metal layer 1512 may serve as both an electrical conductor and, in the case where the device structure 1510 is a photonic device, as an optical reflector. In various embodiments, the thin metal layer is approximately 100-200 nm thick and includes or consists essentially of aluminum (for photonic devices emitting visible light) or gold or silver (for infrared light). The semiconductor structure 1400 may then be bonded to a handle wafer 1514 to define a bonded structure 1515. The handle wafer 1514 may include or consist essentially of a semiconductor material such as Si. Finally, a top contact layer 1516 may be formed on a top surface of the handle wafer 1514 and a bottom contact layer 1518 may be formed on a bottom surface of the substrate 310.



FIG. 16A illustrates a flipped structure 1600, which may be the bonded structure 1520 rotated by 180 degrees. The substrate 310 may be removed with, for example, an etching process, exposing surfaces 1602 of the second crystalline semiconductor material 1500. The defects 1502 may now be near the exposed surfaces 1602 of the second crystalline semiconductor material 1500. The exposed portion of the second crystalline semiconductor material 1500 may include a non-planar surface.


The wafer bonding and flipping process may present advantages during the formation of the second crystalline semiconductor material 1500, because any layer or layers that include the second crystalline semiconductor material 1500 may ultimately be rotated 180 degrees. For example, with reference to FIG. 15A, a layer with a high bandgap may first be deposited on the substrate 310 first, then a layer with a medium bandgap, and finally a layer with a low bandgap. Because the first layer with a high bandgap may require a higher growth temperature than the materials with lower bandgaps, depositing the layers in this order may spare the low bandgap layer from being subjected to the high temperature required for the high bandgap layer. The low bandgap layer may require a lower growth temperature, which the high bandgap material may be better able to withstand. When the device structure 1400, including the illustrative high-, middle-, and low-bandgap layers of the second crystalline semiconductor material 1500, is rotated by the flipping process, the layers may be in an optimal configuration to form a photonic device.


Similarly, doping types in the layer or layers comprising the second crystalline semiconductor material 1500 may be chosen to take advantage of the bonding and flipping process. For example, later processing steps may raise the temperature of the device structure 1400 sufficiently to cause the material of substrate 310, e.g., Si, to diffuse into a first deposited layer or region in the second crystalline semiconductor material 1500. Because the material of substrate 310 may be a n-type dopant in III-V materials such as GaAs and InP, atoms of that material that diffuse into a first deposited p-type doped III-V layer may deleteriously compensate the p-type dopants in that layer. Depositing n-type-doped III-V material on the substrate 310 first, however, may insulate other p-type doped III-V layers against diffusion from the substrate 310.



FIG. 16B depicts, in one embodiment, the removal of a portion of the second crystalline semiconductor material 1500 by, for example, an etching process. The dielectric layer 1404 may be relatively unaffected by the etching process. In an alternative embodiment, a portion of the second crystalline semiconductor material 1500 and a portion of the dielectric layer 1404 may be removed simultaneously by, for example, CMP. The portion of the second crystalline semiconductor material 1500 that is removed may contain at least a majority of the defects 1502, leaving the remaining portion of the second crystalline semiconductor material 1500 substantially defect-free. The exposed surfaces 1604 of the second crystalline semiconductor material 1500 may comprise (100) surfaces.



FIG. 16C illustrates the structure 1600, in one embodiment, after the dielectric layer 1404 has been removed. A portion of the dielectric layer 1404 may have previously been removed by CMP, as illustrated in FIG. 16B, in which case the remaining portion of the dielectric layer 1404 may be removed. The exposed second crystalline semiconductor material 1500 may comprise one or more ridges 1606. Each ridge 1606 may have a width w, corresponding to the width w of the openings or trenches 1406. Adjacent ridges 1606 may be separated by a spacing s. The width w and the spacing s may each be less than or equal to a visible light wavelength. In one embodiment, the exposed second crystalline semiconductor material 1500 comprises a two-dimensional array of raised features. The width w and the spacing s of the ridges 1606 in a one- or two-dimensional array may be selected such that the ridges 1606 enhance the light absorption or extraction efficiency of the structure 1600 and/or improve the light beam quality. In one embodiment, the spacing s is approximately equal to the wavelength of the absorbed or emitted light.



FIG. 16D illustrates another embodiment of the structure 1600. A metal contact 1608, designed in accordance with standard methods, may be formed on the surface of the second crystalline semiconductor material 1500. In one embodiment, the metal contact 1608 conforms to at least one ridge 1606. In an alternative embodiment, the oxide layer 1404 is not removed before the metal contact 1608 is formed. In this embodiment, the top surface of the structure 1600 may be planarized before the metal contact 1608 is formed.


A photonic device 1510, such as a light-emitting diode or a photovoltaic device, formed in accordance with the method described in FIGS. 14-16, may exhibit several advantages. For example, an optical reflection layer may be formed, prior to bonding, on the handle wafer 1514 or on the semiconductor structure 1400. The optical reflection layer may therefore be disposed beneath the photonic device 1510, and may thereby enhance backlight reflection and photon recycling. An LED photonic device 1510 may exhibit increased light-extraction efficiency as a result of the placement, width, and spacing of the ridges 1606 formed on the surface of the crystalline semiconductor material 1500. In addition, the ridges 1606 may enhance the thermal cooling of the structure 1600, thereby improving the thermal depletion of the structure.


Other embodiments incorporating the concepts disclosed herein may be used without departing from the spirit of the essential characteristics of the invention or the scope thereof. The foregoing embodiments are therefore to be considered in all respects as only illustrative rather than restrictive of the invention described herein. Therefore, it is intended that the scope of the invention be only limited by the following claims.

Claims
  • 1. A method comprising: forming an insulator layer on a substrate surface, the insulator layer having self-assembled holes therethrough to the substrate surface, the substrate surface comprising a surface of first crystalline semiconductor material;forming a second crystalline semiconductor material in the self-assembled holes, the second crystalline semiconductor material being lattice-mismatched to the first crystalline semiconductor material; andforming a crystalline semiconductor layer over the insulator layer.
  • 2. The method of claim 1, wherein the forming the insulator layer comprises using anodic oxidation.
  • 3. The method of claim 1, wherein the second crystalline semiconductor material is relaxed by elastic relaxation in the self-assembled holes.
  • 4. The method of claim 1, wherein the second crystalline semiconductor material is relaxed by plastic relaxation in the self-assembled holes.
  • 5. The method of claim 1 further comprising planarizing the crystalline semiconductor layer.
  • 6. The method of claim 1, wherein the crystalline semiconductor layer is substantially exhausted of dislocation defects.
  • 7. The method of claim 1 further comprising forming a device in the crystalline semiconductor layer.
  • 8. The method of claim 1, wherein the forming the crystalline semiconductor layer comprises epitaxially growing the second crystalline semiconductor material out of the self-assembled holes, and coalescing the second crystalline semiconductor material over the insulator layer to form the crystalline semiconductor layer.
  • 9. A structure comprising: an insulator layer having an opening to a substrate, the substrate comprising a first crystalline semiconductor material;a wide bandgap crystalline material in the opening, the wide bandgap crystalline material being lattice mismatched from the first crystalline semiconductor material, dislocations in the wide bandgap crystalline material arising from the lattice mismatch, the dislocations terminating at a sidewall of the opening; anda high electron mobility crystalline material on the wide bandgap crystalline material.
  • 10. The structure of claim 9 further comprising a field effect transistor (FET) disposed at least partially in the high electron mobility crystalline material.
  • 11. The structure of claim 9, wherein the wide bandgap crystalline material comprises AlSb.
  • 12. The structure of claim 9, wherein the high electron mobility crystalline material comprises InAs.
  • 13. The structure of claim 9, wherein the wide bandgap crystalline material and the high electron mobility crystalline material are substantially lattice matched.
  • 14. The structure of claim 9, wherein a top surface of the wide bandgap crystalline material and a top surface of the insulator layer are co-planar.
  • 15. A structure comprising: an insulator layer having an opening to a substrate, the substrate comprising a first crystalline semiconductor material;a second crystalline semiconductor material in the opening, the second crystalline semiconductor material being lattice mismatched from the first crystalline semiconductor material, dislocations in the second crystalline semiconductor material arising from the lattice mismatch, the dislocations terminating at a sidewall of the opening; anda strained crystalline semiconductor material on the second crystalline semiconductor material.
  • 16. The structure of claim 15, wherein a portion of the second crystalline semiconductor material distal from the substrate is substantially exhausted of dislocations.
  • 17. The structure of claim 15 further comprising a field effect transistor (FET) disposed at least partially in the strained crystalline semiconductor material.
  • 18. The structure of claim 15, wherein at least a portion of the strained crystalline semiconductor material is a channel region of a field effect transistor (FET).
  • 19. The structure of claim 15, wherein source/drain regions of a field effect transistor (FET) are disposed in the strained crystalline semiconductor material and a portion of the second crystalline semiconductor material proximate the strained crystalline semiconductor material.
  • 20. The structure of claim 15, wherein the second crystalline semiconductor material is SiGe, and the strained crystalline semiconductor material is Ge.
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 14/104,924, filed Dec. 12, 2013, which is a continuation of U.S. patent application Ser. No. 13/903,762, filed May 28, 2013, which is a continuation of U.S. patent application Ser. No. 13/681,214, filed Nov. 19, 2012, which is a divisional of U.S. patent application Ser. No. 12/845,593, filed Jul. 28, 2010, which is a continuation of U.S. patent application Ser. No. 12/180,254, filed Jul. 25, 2008, which is a continuation-in-part of U.S. patent application Ser. No. 11/436,198, filed May 17, 2006, which claims priority to and benefit of U.S. Provisional Application Ser. No. 60/681,940 filed May 17, 2005. The entire disclosures of these applications are incorporated herein by reference. U.S. patent application Ser. No. 12/845,593, filed Jul. 28, 2010, is a continuation-in-part of U.S. patent application Ser. No. 11/436,062, filed May 17, 2006. The entire disclosures of these applications are incorporated herein by reference.

US Referenced Citations (431)
Number Name Date Kind
4307510 Sawyer et al. Dec 1981 A
4322253 Pankove et al. Mar 1982 A
4370510 Stirn Jan 1983 A
4545109 Reichert Oct 1985 A
4551394 Betsch et al. Nov 1985 A
4651179 Reichert Mar 1987 A
4727047 Bozler et al. Feb 1988 A
4774205 Choi et al. Sep 1988 A
4789643 Kajikawa Dec 1988 A
4826784 Salerno et al. May 1989 A
4860081 Cogan Aug 1989 A
4876210 Barnett et al. Oct 1989 A
4948456 Schubert Aug 1990 A
4963508 Umeno et al. Oct 1990 A
5032893 Fitzgerald, Jr. et al. Jul 1991 A
5034337 Mosher et al. Jul 1991 A
5061644 Yue et al. Oct 1991 A
5079616 Yacobi et al. Jan 1992 A
5091333 Fan et al. Feb 1992 A
5091767 Bean et al. Feb 1992 A
5093699 Weichold et al. Mar 1992 A
5098850 Nishida et al. Mar 1992 A
5105247 Cavanaugh Apr 1992 A
5108947 Demeester et al. Apr 1992 A
5156995 Fitzgerald, Jr. et al. Oct 1992 A
5159413 Calviello et al. Oct 1992 A
5164359 Calviello et al. Nov 1992 A
5166767 Kapoor et al. Nov 1992 A
5223043 Olson et al. Jun 1993 A
5236546 Mizutani Aug 1993 A
5238869 Shichijo et al. Aug 1993 A
5256594 Wu et al. Oct 1993 A
5269852 Nishida Dec 1993 A
5269876 Mizutani Dec 1993 A
5272105 Yacobi et al. Dec 1993 A
5281283 Tokunaga et al. Jan 1994 A
5285086 Fitzgerald, Jr. Feb 1994 A
5295150 Vangieson et al. Mar 1994 A
5356831 Calviello et al. Oct 1994 A
5403751 Nishida et al. Apr 1995 A
5405453 Ho et al. Apr 1995 A
5407491 Freundlich et al. Apr 1995 A
5410167 Saito Apr 1995 A
5417180 Nakamura May 1995 A
5427976 Koh et al. Jun 1995 A
5432120 Meister et al. Jul 1995 A
5438018 Mori et al. Aug 1995 A
5461243 Ek et al. Oct 1995 A
5518953 Takasu May 1996 A
5528209 MacDonald et al. Jun 1996 A
5545586 Koh Aug 1996 A
5548129 Kubena Aug 1996 A
5589696 Baba Dec 1996 A
5621227 Joshi Apr 1997 A
5622891 Saito Apr 1997 A
5640022 Inai Jun 1997 A
5710436 Tanamoto et al. Jan 1998 A
5717709 Sasaki et al. Feb 1998 A
5792679 Nakato Aug 1998 A
5825049 Simmons et al. Oct 1998 A
5825240 Geis et al. Oct 1998 A
5849077 Kenney Dec 1998 A
5853497 Lillington et al. Dec 1998 A
5869845 Vander Wagt et al. Feb 1999 A
5883549 De Los Santos Mar 1999 A
5886385 Arisumi et al. Mar 1999 A
5903170 Kulkarni et al. May 1999 A
5953361 Borchert et al. Sep 1999 A
5959308 Shichijo et al. Sep 1999 A
5966620 Sakaguchi et al. Oct 1999 A
5998781 Vawter et al. Dec 1999 A
6011271 Sakuma et al. Jan 2000 A
6015979 Sugiura et al. Jan 2000 A
6049098 Sato Apr 2000 A
6083598 Ohkubo et al. Jul 2000 A
6100106 Yamaguchi et al. Aug 2000 A
6110813 Ota et al. Aug 2000 A
6111288 Watanabe et al. Aug 2000 A
6121542 Shiotsuka et al. Sep 2000 A
6150242 Van der Wagt et al. Nov 2000 A
6153010 Kiyoku et al. Nov 2000 A
6191432 Sugiyama et al. Feb 2001 B1
6225650 Tadatomo et al. May 2001 B1
6228691 Doyle May 2001 B1
6229153 Botez et al. May 2001 B1
6235547 Sakuma et al. May 2001 B1
6252261 Usui et al. Jun 2001 B1
6252287 Kurtz et al. Jun 2001 B1
6271551 Schmitz et al. Aug 2001 B1
6274889 Ota et al. Aug 2001 B1
6300650 Sato Oct 2001 B1
6320220 Watanabe et al. Nov 2001 B1
6325850 Beaumont et al. Dec 2001 B1
6339232 Takagi Jan 2002 B1
6342404 Shibata et al. Jan 2002 B1
6348096 Sunakawa et al. Feb 2002 B1
6352942 Luan et al. Mar 2002 B1
6362071 Nguyen et al. Mar 2002 B1
6380051 Yuasa et al. Apr 2002 B1
6380590 Yu Apr 2002 B1
6403451 Linthicum et al. Jun 2002 B1
6407425 Babcock et al. Jun 2002 B1
6456214 van de Wagt Sep 2002 B1
6458614 Nanishi et al. Oct 2002 B1
6475869 Yu Nov 2002 B1
6492216 Yeo et al. Dec 2002 B1
6500257 Wang et al. Dec 2002 B1
6503610 Hiramatsu et al. Jan 2003 B2
6512252 Takagi et al. Jan 2003 B1
6521514 Gehrke et al. Feb 2003 B1
6552259 Hosomi et al. Apr 2003 B1
6566284 Thomas, III et al. May 2003 B2
6576532 Jones et al. Jun 2003 B1
6579463 Winningham et al. Jun 2003 B1
6603172 Segawa et al. Aug 2003 B1
6606335 Kuramata et al. Aug 2003 B1
6617643 Goodwin-Johansson Sep 2003 B1
6635110 Luan et al. Oct 2003 B1
6645295 Koike et al. Nov 2003 B1
6645797 Buynoski et al. Nov 2003 B1
6686245 Mathew et al. Feb 2004 B1
6703253 Koide Mar 2004 B2
6709982 Buynoski et al. Mar 2004 B1
6710368 Fisher et al. Mar 2004 B2
6720196 Kunisato et al. Apr 2004 B2
6727523 Morita Apr 2004 B2
6753555 Takagi et al. Jun 2004 B2
6756611 Kiyoku et al. Jun 2004 B2
6762483 Krivokapic et al. Jul 2004 B1
6767793 Clark et al. Jul 2004 B2
6784074 Shchukin et al. Aug 2004 B2
6787864 Paton et al. Sep 2004 B2
6794718 Nowak et al. Sep 2004 B2
6800910 Lin et al. Oct 2004 B2
6803598 Berger et al. Oct 2004 B1
6809351 Kuramoto et al. Oct 2004 B2
6812053 Kong et al. Nov 2004 B1
6812495 Wada et al. Nov 2004 B2
6815241 Wang Nov 2004 B2
6815738 Rim Nov 2004 B2
6825534 Chen et al. Nov 2004 B2
6831350 Liu et al. Dec 2004 B1
6835246 Zaidi Dec 2004 B2
6835618 Dakshina-Murthy et al. Dec 2004 B1
6838322 Pham et al. Jan 2005 B2
6841410 Sasaoka Jan 2005 B2
6841808 Shibata et al. Jan 2005 B2
6849077 Ricci Feb 2005 B2
6849487 Taylor, Jr. et al. Feb 2005 B2
6849884 Clark et al. Feb 2005 B2
6855583 Krivokapic et al. Feb 2005 B1
6855982 Xiang et al. Feb 2005 B1
6855990 Yeo et al. Feb 2005 B2
6867433 Yeo et al. Mar 2005 B2
6873009 Hisamoto et al. Mar 2005 B2
6882051 Majumdar et al. Apr 2005 B2
6887773 Gunn, III et al. May 2005 B2
6888181 Liao et al. May 2005 B1
6900070 Craven et al. May 2005 B2
6900502 Ge et al. May 2005 B2
6902965 Ge et al. Jun 2005 B2
6902991 Xiang et al. Jun 2005 B2
6909186 Chu Jun 2005 B2
6917068 Krivokapic Jul 2005 B1
6919258 Grant et al. Jul 2005 B2
6920159 Sidorin et al. Jul 2005 B2
6921673 Kobayashi et al. Jul 2005 B2
6921963 Krivokapic et al. Jul 2005 B2
6921982 Joshi et al. Jul 2005 B2
6936875 Sugii et al. Aug 2005 B2
6943407 Ouyang et al. Sep 2005 B2
6946683 Sano et al. Sep 2005 B2
6949769 Hu et al. Sep 2005 B2
6951819 Iles et al. Oct 2005 B2
6955969 Djomehri et al. Oct 2005 B2
6955977 Kong et al. Oct 2005 B2
6958254 Seifert Oct 2005 B2
6960781 Currie et al. Nov 2005 B2
6974733 Boyanov et al. Dec 2005 B2
6977194 Belyansky et al. Dec 2005 B2
6982204 Saxler et al. Jan 2006 B2
6982435 Shibata et al. Jan 2006 B2
6984571 Enquist Jan 2006 B1
6991998 Bedell et al. Jan 2006 B2
6994751 Hata et al. Feb 2006 B2
6995430 Langdo et al. Feb 2006 B2
6995456 Nowak Feb 2006 B2
6996147 Majumdar et al. Feb 2006 B2
6998684 Anderson et al. Feb 2006 B2
7001804 Dietz et al. Feb 2006 B2
7002175 Singh et al. Feb 2006 B1
7012298 Krivokapic Mar 2006 B1
7012314 Bude et al. Mar 2006 B2
7015497 Berger Mar 2006 B1
7015517 Grant et al. Mar 2006 B2
7033436 Biwa et al. Apr 2006 B2
7033936 Green Apr 2006 B1
7041178 Tong et al. May 2006 B2
7045401 Lee et al. May 2006 B2
7049627 Vineis et al. May 2006 B2
7061065 Horng et al. Jun 2006 B2
7074623 Lochtefeld et al. Jul 2006 B2
7078299 Maszara et al. Jul 2006 B2
7078731 D'Evelyn et al. Jul 2006 B2
7084051 Ueda Aug 2006 B2
7084441 Saxler Aug 2006 B2
7087965 Chan et al. Aug 2006 B2
7088143 Ding et al. Aug 2006 B2
7091561 Matsushita et al. Aug 2006 B2
7095043 Oda et al. Aug 2006 B2
7098508 Ieong et al. Aug 2006 B2
7101444 Shchukin et al. Sep 2006 B2
7109516 Langdo et al. Sep 2006 B2
7118987 Fu et al. Oct 2006 B2
7119402 Kinoshita et al. Oct 2006 B2
7122733 Narayanan et al. Oct 2006 B2
7125785 Cohen et al. Oct 2006 B2
7128846 Nishijima et al. Oct 2006 B2
7132691 Tanabe et al. Nov 2006 B1
7138292 Mirabedini et al. Nov 2006 B2
7138302 Xiang et al. Nov 2006 B2
7145167 Chu Dec 2006 B1
7154118 Lindert et al. Dec 2006 B2
7160753 Williams, Jr. Jan 2007 B2
7164183 Sakaguchi et al. Jan 2007 B2
7176522 Cheng et al. Feb 2007 B2
7179727 Capewell et al. Feb 2007 B2
7180134 Yang et al. Feb 2007 B2
7195993 Zheleva et al. Mar 2007 B2
7198995 Chidambarrao et al. Apr 2007 B2
7205586 Takagi et al. Apr 2007 B2
7205604 Ouyang et al. Apr 2007 B2
7211864 Seliskar May 2007 B2
7217882 Walukiewicz et al. May 2007 B2
7224033 Zhu et al. May 2007 B2
7244958 Shang et al. Jul 2007 B2
7247534 Chidambarrao et al. Jul 2007 B2
7247912 Zhu et al. Jul 2007 B2
7250359 Fitzgerald Jul 2007 B2
7262117 Gunn, III et al. Aug 2007 B1
7268058 Chau et al. Sep 2007 B2
7297569 Bude et al. Nov 2007 B2
7344942 Korber Mar 2008 B2
7361576 Imer et al. Apr 2008 B2
7372066 Sato et al. May 2008 B2
7420201 Langdo et al. Sep 2008 B2
7449379 Ochimizu et al. Nov 2008 B2
7582498 D'Evelyn et al. Sep 2009 B2
7626246 Lochtefeld et al. Dec 2009 B2
7638842 Currie et al. Dec 2009 B2
7655960 Nakahata et al. Feb 2010 B2
7777250 Lochtefeld Aug 2010 B2
7799592 Lochtefeld Sep 2010 B2
7825328 Li Nov 2010 B2
7875958 Cheng et al. Jan 2011 B2
8034697 Fiorenza et al. Oct 2011 B2
20010006249 Fitzgerald Jul 2001 A1
20010045604 Oda et al. Nov 2001 A1
20020011612 Hieda Jan 2002 A1
20020017642 Mizushima et al. Feb 2002 A1
20020022290 Kong et al. Feb 2002 A1
20020030246 Eisenbeiser et al. Mar 2002 A1
20020036290 Inaba et al. Mar 2002 A1
20020046693 Kiyoku et al. Apr 2002 A1
20020047155 Babcock et al. Apr 2002 A1
20020066403 Sunakawa et al. Jun 2002 A1
20020070383 Shibata et al. Jun 2002 A1
20020084000 Fitzgerald Jul 2002 A1
20020127427 Young et al. Sep 2002 A1
20020168802 Hsu et al. Nov 2002 A1
20020168844 Kuramoto et al. Nov 2002 A1
20020179005 Koike et al. Dec 2002 A1
20030030117 Iwasaki et al. Feb 2003 A1
20030045017 Hiramatsu et al. Mar 2003 A1
20030057486 Gambino et al. Mar 2003 A1
20030064535 Kub et al. Apr 2003 A1
20030070707 King et al. Apr 2003 A1
20030087462 Koide et al. May 2003 A1
20030089899 Lieber et al. May 2003 A1
20030155586 Koide et al. Aug 2003 A1
20030168002 Zaidi Sep 2003 A1
20030178677 Clark et al. Sep 2003 A1
20030178681 Clark et al. Sep 2003 A1
20030183827 Kawaguchi et al. Oct 2003 A1
20030203531 Shchukin et al. Oct 2003 A1
20030207518 Kong et al. Nov 2003 A1
20030227036 Sugiyama et al. Dec 2003 A1
20030230759 Thomas, III et al. Dec 2003 A1
20040005740 Lochtefeld et al. Jan 2004 A1
20040012037 Venkatesan et al. Jan 2004 A1
20040016921 Botez et al. Jan 2004 A1
20040031979 Lochtefeld et al. Feb 2004 A1
20040041932 Chao et al. Mar 2004 A1
20040043584 Thomas et al. Mar 2004 A1
20040072410 Motoki et al. Apr 2004 A1
20040075105 Leitz et al. Apr 2004 A1
20040075464 Samuelson et al. Apr 2004 A1
20040082150 Kong et al. Apr 2004 A1
20040087051 Furuya et al. May 2004 A1
20040092060 Gambino et al. May 2004 A1
20040118451 Walukiewicz et al. Jun 2004 A1
20040121507 Bude et al. Jun 2004 A1
20040123796 Nagai et al. Jul 2004 A1
20040142503 Lee et al. Jul 2004 A1
20040150001 Shchukin et al. Aug 2004 A1
20040155249 Narui et al. Aug 2004 A1
20040173812 Currie et al. Sep 2004 A1
20040183078 Wang Sep 2004 A1
20040185665 Kishimoto et al. Sep 2004 A1
20040188791 Horng et al. Sep 2004 A1
20040195624 Liu et al. Oct 2004 A1
20040227187 Cheng et al. Nov 2004 A1
20040247218 Ironside et al. Dec 2004 A1
20040256613 Oda et al. Dec 2004 A1
20040256647 Lee et al. Dec 2004 A1
20040262617 Hahm et al. Dec 2004 A1
20050001216 Adkisson et al. Jan 2005 A1
20050003572 Hahn et al. Jan 2005 A1
20050009304 Zheleva et al. Jan 2005 A1
20050017351 Ravi Jan 2005 A1
20050035410 Yeo et al. Feb 2005 A1
20050040444 Cohen Feb 2005 A1
20050045983 Noda et al. Mar 2005 A1
20050054164 Xiang Mar 2005 A1
20050054180 Han et al. Mar 2005 A1
20050056827 Li et al. Mar 2005 A1
20050056892 Seliskar Mar 2005 A1
20050072995 Anthony Apr 2005 A1
20050073028 Grant et al. Apr 2005 A1
20050093021 Ouyang et al. May 2005 A1
20050093154 Kottantharayil et al. May 2005 A1
20050104152 Snyder et al. May 2005 A1
20050104156 Wasshuber May 2005 A1
20050118793 Snyder et al. Jun 2005 A1
20050118825 Nishijima et al. Jun 2005 A1
20050121688 Nagai et al. Jun 2005 A1
20050127451 Tsuchiya et al. Jun 2005 A1
20050136626 Morse Jun 2005 A1
20050139860 Snyder et al. Jun 2005 A1
20050145941 Bedell et al. Jul 2005 A1
20050145954 Zhu et al. Jul 2005 A1
20050148161 Chen et al. Jul 2005 A1
20050156169 Chu Jul 2005 A1
20050156202 Rhee et al. Jul 2005 A1
20050161711 Chu Jul 2005 A1
20050164475 Peckerar et al. Jul 2005 A1
20050181549 Barr et al. Aug 2005 A1
20050184302 Kobayashi et al. Aug 2005 A1
20050205859 Currie et al. Sep 2005 A1
20050205932 Cohen Sep 2005 A1
20050211291 Bianchi Sep 2005 A1
20050212051 Jozwiak et al. Sep 2005 A1
20050217565 Lahreche et al. Oct 2005 A1
20050245095 Haskell et al. Nov 2005 A1
20050263751 Hall et al. Dec 2005 A1
20050274409 Fetzer et al. Dec 2005 A1
20050280103 Langdo et al. Dec 2005 A1
20060009012 Leitz et al. Jan 2006 A1
20060019462 Cheng et al. Jan 2006 A1
20060049409 Rafferty et al. Mar 2006 A1
20060057825 Bude et al. Mar 2006 A1
20060073681 Han Apr 2006 A1
20060105533 Chong et al. May 2006 A1
20060112986 Atwater, Jr. et al. Jun 2006 A1
20060113603 Currie Jun 2006 A1
20060128124 Haskell et al. Jun 2006 A1
20060131606 Cheng Jun 2006 A1
20060144435 Wanlass Jul 2006 A1
20060145264 Chidambarrao et al. Jul 2006 A1
20060160291 Lee et al. Jul 2006 A1
20060162768 Wanlass et al. Jul 2006 A1
20060166437 Korber Jul 2006 A1
20060169987 Miura et al. Aug 2006 A1
20060175601 Lieber et al. Aug 2006 A1
20060186510 Lochtefeld et al. Aug 2006 A1
20060189056 Ko et al. Aug 2006 A1
20060197123 Lochtefeld et al. Sep 2006 A1
20060197124 Lochtefeld et al. Sep 2006 A1
20060197126 Lochtefeld et al. Sep 2006 A1
20060202276 Kato Sep 2006 A1
20060205197 Yi et al. Sep 2006 A1
20060211210 Bhat et al. Sep 2006 A1
20060266281 Beaumont et al. Nov 2006 A1
20060267047 Murayama Nov 2006 A1
20060292719 Lochtefeld et al. Dec 2006 A1
20070025670 Pan et al. Feb 2007 A1
20070029643 Johnson et al. Feb 2007 A1
20070054465 Currie et al. Mar 2007 A1
20070054467 Currie et al. Mar 2007 A1
20070099315 Maa et al. May 2007 A1
20070099329 Maa et al. May 2007 A1
20070102721 DenBaars et al. May 2007 A1
20070105256 Fitzgerald May 2007 A1
20070105274 Fitzgerald May 2007 A1
20070105335 Fitzgerald May 2007 A1
20070181977 Lochtefeld et al. Aug 2007 A1
20070187668 Noguchi et al. Aug 2007 A1
20070187796 Rafferty et al. Aug 2007 A1
20070196987 Chidambarrao et al. Aug 2007 A1
20070248132 Kikuchi et al. Oct 2007 A1
20070267722 Lochtefeld et al. Nov 2007 A1
20080001169 Lochtefeld Jan 2008 A1
20080070355 Lochtefeld et al. Mar 2008 A1
20080073641 Cheng et al. Mar 2008 A1
20080073667 Lochtefeld Mar 2008 A1
20080093622 Li et al. Apr 2008 A1
20080099785 Bai et al. May 2008 A1
20080154197 Derrico et al. Jun 2008 A1
20080187018 Li Aug 2008 A1
20080194078 Akiyama et al. Aug 2008 A1
20080245400 Li Oct 2008 A1
20080257409 Li et al. Oct 2008 A1
20080286957 Lee et al. Nov 2008 A1
20090039361 Li et al. Feb 2009 A1
20090042344 Ye et al. Feb 2009 A1
20090065047 Fiorenza et al. Mar 2009 A1
20090072284 King et al. Mar 2009 A1
20090110898 Levy et al. Apr 2009 A1
20090321882 Park Dec 2009 A1
20100012976 Hydrick et al. Jan 2010 A1
20100025683 Cheng Feb 2010 A1
20100072515 Park et al. Mar 2010 A1
20100078680 Cheng et al. Apr 2010 A1
20100176371 Lochtefeld Jul 2010 A1
20100176375 Lochtefeld Jul 2010 A1
20100213511 Lochtefeld Aug 2010 A1
20100216277 Fiorenza et al. Aug 2010 A1
20100252861 Lochtefeld Oct 2010 A1
20100308376 Takada et al. Dec 2010 A1
20110011438 Li Jan 2011 A1
20110086498 Cheng et al. Apr 2011 A1
Foreign Referenced Citations (50)
Number Date Country
2550906 May 2003 CN
10017137 Oct 2000 DE
10320160 Aug 2004 DE
0352472 Jun 1989 EP
0600276 Jun 1994 EP
0817096 Jan 1998 EP
1551063 Jul 2005 EP
1796180 Jun 2007 EP
2215514 Sep 1989 GB
2062090 Mar 1990 JP
7230952 Aug 1995 JP
10126010 May 1998 JP
10284436 Oct 1998 JP
10284507 Oct 1998 JP
11251684 Sep 1999 JP
11307866 Nov 1999 JP
2000021789 Jan 2000 JP
2000216432 Aug 2000 JP
2000286449 Oct 2000 JP
2000299532 Oct 2000 JP
2001007447 Jan 2001 JP
2001102678 Apr 2001 JP
3202223 Aug 2001 JP
2001257351 Sep 2001 JP
2002118255 Apr 2002 JP
2002141553 May 2002 JP
2002241192 Aug 2002 JP
2002293698 Oct 2002 JP
2003163370 Jun 2003 JP
3515974 Apr 2004 JP
2004200375 Jul 2004 JP
2009177167 Aug 2009 JP
20030065631 Aug 2003 KR
20090010284 Jan 2009 KR
544930 Aug 2003 TW
WO0072383 Nov 2000 WO
WO0101465 Jan 2001 WO
WO0209187 Jan 2002 WO
WO02086952 Oct 2002 WO
WO02088834 Nov 2002 WO
WO03073517 Sep 2003 WO
WO2004004927 Jan 2004 WO
WO2004023536 Mar 2004 WO
WO2005013375 Feb 2005 WO
WO2005048330 May 2005 WO
WO2005098963 Oct 2005 WO
WO2005122267 Dec 2005 WO
WO2006025407 Mar 2006 WO
WO2006125040 Nov 2006 WO
WO2008124154 Oct 2008 WO
Non-Patent Literature Citations (273)
Entry
Kwok K. Ng, “Resonant-Tunneling Diode,” Complete Guide to Semiconductor Devices, Chapter 10. Nov. 3, 2010, pp. 75-83.
“Communication pursuant to Article 94(3) EPC,” Application No. 06 770 525.1-2203, Applicant: Taiwan Semiconductor Company, Ltd., Feb. 17, 2011, 4 pages.
68 Applied Physics Letters 7, 1999, pp. 774-779 (trans. of relevant portions attached).
Ames, “Intel Says More Efficient Chips are Coming,” PC World, available at: http://www.pcworld.com/printable/article/id,126044/printable.html (Jun. 12, 2006); 4 pages.
Asano et al., “AlGalnN laser diodes grown on an ELO-GaN substrate vs. on a sapphire substrate,” Semiconductor Laser Conference (2000) Conference Digest, IEEE 17th International, 2000, pp. 109-110.
Asaoka, et al., “Observation of 1 f x/noise of GalnP/GaAs triple barrier resonant tunneling diodes,” AIP Conf. Proc., vol. 780, Issue 1, 2005, pp. 492-495.
Ashby, et al., “Low-dislocation-density GaN from a single growth on a textured substrate,” Applied Physics Letters, vol. 77, No. 20, Nov. 13, 2000, pp. 3233-3235.
Ashley, et al., “Heternogeneous InSb Quantum Well Transistors on Silicon for Ultra-High Speed, Low Power Logic Applications,” 43 Electronics Letters 14, Jul. 2007, 2 pages.
Bai et al., “Study of the Defect Elimination Mechanisms in Aspect Ratio Trapping Ge Growth,” Applied Physics Letters, vol. 90, 2007, 3 ppages.
Bakkers et al., “Epitaxial Growth on InP Nanowires on Germanium,” Nature Materials, vol. 3, Nov. 2004, pp. 769-773.
Baron et al., “Chemical Vapor Deposition of Ge Nanocrystals on SiO2,” Applied Physics Letters, vol. 83, No. 7, Aug. 18, 2003, pp. 1444-1446.
Bean et al., “GexSi1-x/Si strained-later Superlattice grown by molecular beam Epitaxy,” Journal of Vacuum Science Technology A2 (2), Jun. 1984, pp. 436-440.
Beckett et al., “Towards a reconfigurable nanocomputer platform,” ACM International Conference Proceeding Series, vol. 19, 2002, pp. 141-150.
Beltz et al., “A Theoretical Model for Threading Dislocation Reduction During Selective Area Growth,” Materials Science and Engineering, A234-236, 1997, pp. 794-797.
Belyaev, et al., “Resonance and current instabilities in AIN/GaN resonant tunneling diodes,” 21 Physica E 2-4, 2004, pp. 752-755.
Berg, J., “Electrical Characterization of Silicon Nanogaps,” Doktorsavhandlingar vid Chalmers Tekniska Hagskola, 2005, No. 2355, 2 pages.
Bergman et al., “RTD/CMOS Nanoelectronic Circuits: Thin-Film InP-based Resonant Tunneling Diodes Integrated with CMOS circuits,” 20 Electron Device Letters 3, 1999, pp. 119-122.
Blakeslee, “The Use of Superlattices to Block the Propagation of Dislocations in Semiconductors,” Mat. Res. Soc. Symposium 148, 1989, pp. 217-227.
Bogumilowicz et al., “Chemical Vapour Etching of Si, SiGe and Ge with HCL: Applications to the Formation of Thin Relaxed SiGe Buffers and to the Revelation of Threading Dislocations in Semiconductors,” 20 Semicond. Sci. Tech. 2005, pp. 127-134.
Borland, “Novel Device structures by selective epitaxial growth (SEG),” Electron Devices Meeting, vol. 33, 1987, pp. 12-15.
Bryskiewicz, “Dislocation filtering in SiGe and InGaAs buffer layers grown by selective lateral overgrowth method,” Applied Physics Letters, vol. 66, No. 10, Mar. 6, 1995, pp. 1237-1239.
Burenkov et al., “Corner Effect in Double and Triple Gate FinFETs” European solid-state device research, 33rd Conference on Essderc '03 Sep. 16-18, 2003, Piscataway, NJ, USA, IEEE, vol. 16, pp. 135-138, XPo10676716.
Bushroa et al., “Lateral epitaxial overgrowth and reduction in defect density of 3C-SiC on patterned Si substrates,” Journal of Crystal Growth, vol. 271, No. 1-2, Oct. 15, 2004, pp. 200-206.
Calado, et al., “Modeling of a resonant tunneling diode optical modulator,” University of Algarve, Department of Electronics and Electrical Engineering, 2005, pp. 96-99.
Campo et al., “Comparison of Etching Processes of Silicon and Germanium in SF6-O2 Radio-Frequency Plasma,” 13 Journal of Vac. Sci. Tech., B-2, 1995, pp. 235-241.
Cannon et al., “Monolithic Si-based Technology for Optical Receiver Circuits,” Proceedings of SPIE, vol. 4999, 2003, pp. 145-155.
Chan et al., “Influence of Metalorganic Sources on the Composition Uniformity of Selectively Grown Gax In1-xP,” Japan. Journal of Applied Physics, vol. 33, 1994, pp. 4812-4819.
Chang et al. “3-D simulation of strained Si/SiGe heterojunction FinFETs” Semiconductor Device Research Symposium, Dec. 10-12, 2003, pp. 176-177.
Chang et al., “Effect of growth temperature on epitaxial lateral overgrowth of GaAs on Si substrate,” Journal of Crystal Growth, vol. 174, No. 1-4, Apr. 1997, pp. 630-634.
Chang et al., “Epitaxial Lateral Overgrowth of Wide Dislocation-Free GaAs on Si Substrates,” Electrochemical Society Proceedings, vol. 97-21, May 13, 1998, pp. 196-200.
Chau et al., Opportunities and Challenges of III-V Nanoelectronics for Future High-Speed, Low Power Logic Applications, IEEE CSIC Digest, 2005, pp. 17-20.
Chen et al., “Dislocation reduction in GaN thin films via lateral overgrowth from trenches,” Applied Physics Letters, vol. 75, No. 14, Oct. 4, 1999, pp. 2062-2063.
Chengrong, et al., “DBRTD with a high PVCR and a peak current density at room temperature,” Chinese Journal of Semiconductors vol. 26, No. 10, Oct. 2005, pp. 1871-1874.
Choi et al., “Monolithic Integration of GaAs/AIGaAs Double-Heterostructure LEDs and Si MOSFETs,” Electron Device Letters, vol. EDL-7, No. 9, Sep. 1986, 3 pages.
Choi et al., “Monolithic Integration of Si MOSFETs and GaAs MESFET5,” Electron Device Letters, vol. EDL-7, No. 4, Apr. 1986, 3 pages.
Choi, et al., “Low-voltage low-power K-band balanced RTD-based MMIC VCO,” 2006 IEEE, Department of EECS, Korea Advanced Institute of Science and Technology, 2006, pp. 743-746.
Cloutier et al., “Optical gain and stimulated emission in periodic nanopatterned crystalline silicon,” Nature Materials, Nov. 2005, 5 pages.
Currie et al., “Carrier Mobilities and Process Stability of Strained Si n- and p-MOSFETs on SiGe Virtual Substrates,” J. Vacuum Science Technology, B, vol. 19, No. 6, 2001, pp. 2268-2279.
Dadgar et al., “MOVPE growth of GaN on Si (111) substrates,” Journal of Crystal Growth, vol. 248, Feb. 1, 2003, pp. 556-562.
Datta et al., “Silicon and III-V Nanoelectronics,” IEEE International Conference on Indium Phosphide & Related Materials, 2005, pp. 7-8.
Datta et al., “Ultrahigh-Speed 0.5 V Supply Voltage In0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate,” 28 Electrohn Device Letters 8, 2007, pp. 685-687.
Davis et al., “Lateral epitaxial overgrowth of and defect reduction in GaN thin films,” Lasers and Electro-Optics Society Annual Meeting (1998) LEOS '98. IEEE, vol. 1, Dec. 1-4, 1998, pp. 360-361.
De Boeck et al., “The fabrication on a novel composite GaAs/SiO2 nucleation layer on silicon for heteroepitaxial overgrowth by molecular beam Epitaxy,” Material Science and Engineering, B9, 1991, pp. 137-141.
Donaton et al., “Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure,” 2006 IEDM, pp. 465-468.
Dong, Y., et al, “Selective area growth of InP through narrow openings by MOCVD and its application to InP HBT,” 2003 International Conference on Indium Phosphide and Related Materials, May 12-16, 2003, pp. 389-392.
European Patent Office, Extended European Search Report and Search Opinion dated Jan. 26, 2011 in EP Patent Application No. 10003084.0-2203 (9 pages).
European Search Report issued by the European Patent Office on Dec. 15, 2010 in European Patent Application No. 10002884.4 (10 pages).
Examination Report in European Patent Application No. 06800414.2, mailed Mar. 5, 2009, 3 pages.
Fang et al., “Electrically pumped hybrid AlGalnAs-silicon evanescent laser,” 14 Optics Express 20, 2006, pp. 9203-9210.
Feltin et al., “Epitaxial lateral overgrowth of GaN on Si (111),” Journal of Applied Physics, vol. 93, No. 1, Jan. 1, 2003, pp. 182-185.
Feng et al., “Integration of Germanium-on Insulator and Silicon Substrate,” 27 Electron Device Letters 11, 2006, pp. 911-913.
Fiorenza et al., “Film Thickness Constraints for Manufacturable Strained Silicon CMOS,” 19 Semiconductor Science Technology, 2004, p. L4.
Fischer et al., “Elastic stress relaxation in SiGe epilayers on patterned Si substrates,” 75 Journal of Applied Physics 1, 1994, pp. 657-659.
Fischer et al., “State of stress and critical thickness of Strained small-area SiGe layers,” Phys. Stat. Sol. (a) vol. 171, 1999, pp. 475-485.
Fitzgerald et al., “Elimination of Dislocations in Heteroepitaxial MBE and RTCVD GexSi1-x Grown on Patterned Si Substrates,” Journal of Electronic Materials, vol. 19, No. 9, 1990, pp. 949-955.
Fitzgerald et al., “Epitaxial Necking in GaAs Growth on Pre-patterned Si Substrates,” Journal of Electronic Materials, vol. 20, No. 10, 1991, pp. 839-853.
Fitzgerald et al., “Nucleation Mechanisms and the Elimination of Misfit Dislocations at Mismatched Interfaces by Reduction in Growth Areas,” Journal of Applied Physics, vol. 65, No. 6, Mar. 15, 1989, pp. 2220-2237.
Fitzgerald et al., “Structure and recombination in InGaAs/GaAs heterostructures,” 63 Journal of Applied Physics, vol. 3, 1988, pp. 693-703.
Fitzgerald et al., “Totally relaxed Gex Si1-x layers with low threading dislocation densities grown on Si Substrates,” vol.59, Applied Physics Letters 7, 1991, pp. 811-813.
Fitzgerald, “The Effect of Substrate Growth Area on Misfit and Threading Dislocation Densities in Mismatched Heterostructures,” Journal of Vacuum Science Technology, vol. 7, No. 4, Jul./Aug. 1989, pp. 782-788.
Gallagher et al., “Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip,” 50 IBM J. Research & Dev. 1, Jan. 2006, pp. 5-23A.
Gallas et al., “Influence of Doping on Facet Formation at the SiO2/Si Interface,” Surface Sci. 440, 1999, pp. 41-48.
Geppert, “Quantum transistors: toward nanoelectronics,” IEEE Spectrum, Sep. 2000, pp. 46-51.
Gibbon et al., “Selective-area low-pressure MOCVD of GalnAsP and related materials on planar InP substrates,” Semicond. Sci. Tech. vol. 8, 1993, pp. 998-1010.
Glew et al., “New DFB grating structure using dopant-induced refractive index step,” J. Crystal Growth 261, 2004, pp. 349-354.
Golka, et al., “Negative differential resistance in dislocation-free GaN/AlGan double-barrier diodes grown on bulk GaN,” 88 Applied Physics Letters 17, Apr. 2006, pp. 172106-1-172106-3.
Goodnick, S.M., “Radiation Physics and Reliability Issues in III-V Compound Semiconductor Nanoscale Heterostructure Devices,” Final Technical Report, Arizona State Univ. Dept. Electrical & Computer Eng, 80 pages, 1996-1999.
Gould et al., “Magnetic resonant tunneling diodes as voltage-controlled spin selectors,” 241 Phys. Stat. Sol. (B), vol. 3, 2004, pp. 700-703.
Groenert et al., “Monolithic integration of room-temperature cw GaAs/AlGaAs lasers on Si substrates via relaxed graded GeSi buffer layers,” 93 Journal of Applied Physics, No. 362, Jan. 2003, pp. 362-367.
Gruber, et al., “Semimagnetic Resonant Tunneling Diodes for Electron Spin Manipulation,” Nanostructures: Physics & Technology, 8th International Symposium, 2000, pp. 483-486.
Gustafsson et al., “Cathodoluminescence from relaxed Gex Si1-x grown by heteroepitaxial lateral overgrowth,” Journal of Crystal Growth 141, 1994, pp. 363-370.
Gustafsson et al., “Investigations of high quality Gex Si1-x grown by heteroepitaxial lateral overgrowth using cathodoluminescence,” Inst. Phys. Conf. Ser., No. 134, Section 11, Apr. 1993, pp. 675-678.
Hammerschmidt, “Intel to Use Trigate Transistors from 2009 on,” EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articleID=189400035 (Jun. 12, 2006). 1 page.
Hasegawa, et al., “Sensing Terahertz Signals with III-V Quantum Nanostructures,” Quantum Sensing: Evolution and Revolution from Past to Future, SPIE 2003, pp. 96-105.
Hayafuji et al., Japan, Journal of Applied Physics, vol. 29, 1990, pp. 2371.
Hersee et al., “The Controlled Growth of GaN Nanowires,” Nano Letters, vol. 6, No. 8, 2006, pp. 1808-1811.
Hiramatsu et al., “Fabrication and characterization of low defect density GaN using facet-controlled epitaxial lateral overgrowth (FACELO),” Journal of Crystal Growth, vol. 221, Dec. 2000, pp. 316-326.
Hollander et al., “Strain and Misfit Dislocation Density in Finite Lateral Size Si1-x GEx/Si Films Grown by Selective Epitaxy,” Thin Solid Films, vol. 292, 1997, pp. 213-217.
Hu et al., “Growth of Well-Aligned Carbon Nanotube arrays on Silicon Substrates Using Porous Alumina Film as a Nanotemplate,” 79 Applied Physics Letters 19, 2001, 3 pages.
Yanlong, et al., “Monolithically fabricated OEICs using RTD and MSM,” Chinese Journal Semiconductors vol. 27, No. 4, Apr. 2006, pp. 641-645.
Huang et al., “Electron and Hole Mobility Enhancement in Strained SOI by Wafer Bonding,” 49 IEEE Transactions on Electron Devices 9, 2002, pp. 1566-1570.
Ying-Long, et al., “Resonant tunneling diodes and high electron mobility transistors integrated on GaAs substrates,” Chinese Physics Letters 23, vol. 3, Mar. 2006, pp. 697-700.
Hydrick et al., “Chemical Mechanical Polishing of Epitaxial Germanium on Si02-patterned Si(001) Substrates,” ECS Transactions, 16 (10), 2008, (pp. 237-248).
Intel Press Release, “Intel's Tri-Gate Transistor to Enable Next Era in Energy-Efficient Performance,” Intel Corporation (Jun. 12, 2006). 2 pages.
Intel to Develop Tri-Gate Transistors Based Processors, available at: http://news.techwhack.com/3822/tri-gate-transistors/ (Jun. 13, 2006) 6 pages.
International Preliminary Report on Patentability for International Application No. PCT/US2006/019152 mailed Nov. 29, 2007, 2 pages.
International Preliminary Report on Patentability for International Application No. PCT/US2006/029247 mailed Feb. 7, 2008, 12 pages.
International Preliminary Report on Patentability for International Application No. PCT/US2006/033859 mailed Mar. 20, 2008, 14 pages.
International Preliminary Report on Patentability for International Application No. PCT/US2007/019568 mailed Mar. 19, 2009, 10 pages.
International Preliminary Report on Patentability for International Application No. PCT/US2007/020181 mailed Apr. 2, 2009, 9 pages.
International Preliminary Report on Patentability for International Application No. PCT/US2007/020777 mailed Apr. 9, 2009, 12 pages.
International Preliminary Report on Patentability for International Application No. PCT/US2007/021023 mailed Apr. 9, 2009, 8 pages.
International Preliminary Report on Patentability for International Application No. PCT/US2007/022392 mailed Apr. 30, 2009, 14 pages.
International Search Report and Written Opinion for International Application No. PCT/US2006/019152 mailed Oct. 19, 2006, 11 pages.
International Search Report and Written Opinion for International Application No. PCT/US2006/029247 mailed May 7, 2007, 19 pages.
International Search Report and Written Opinion for International Application No. PCT/US2008/068377, mailed Jul. 6, 2009, 19 pages.
International Search Report and Written Opinion for International Application No. PCT/US2006/033859 mailed Sep. 12, 2007, 22 pages.
International Search Report and Written Opinion for International Application No. PCT/US2007/007373, dated Oct. 5, 2007, 13 pages.
International Search Report and Written Opinion for International Application No. PCT/US2007/019568 mailed Feb. 6, 2008, 13 pages.
International Search Report and Written Opinion for International Application No. PCT/US2007/020181 mailed Jan. 25, 2008, 15 pages.
International Search Report and Written Opinion for International Application No. PCT/US2007/020777 mailed Feb. 8, 2008, 18 pages.
International Search Report and Written Opinion for International Application No. PCT/US2007/021023 mailed Jun. 6, 2008, 10 pages.
International Search Report and Written Opinion for International Application No. PCT/US2007/022392 mailed Apr. 11, 2008, 20 pages.
International Search Report for International Application No. PCT/US2006/019152, mailed May 17, 2005. 11 pages.
International Technology Roadmap for Semiconductors—Front End Processes, pp. 1-62 (2005).
Ipri et al., “MONO/POLY technology for fabricating low-capacitance CMOS integrated circuits,” Electron Devices, IEEE Transactions, vol. 35, No. 8, Aug. 1988 pp. 1382-1383.
Ishibashi, et al., “3rd Topical Workshop on Heterostructure Microelectronics for Information Systems Applications,” Aug.-Sep. 1998, 115 pages.
Ishitani et al., “Facet Formation in Selective Silicon Epitaxial Growth,” 24 Japan, Journal of Applied Physics, vol. 10, 1985, pp. 1267-1269.
Ismail et al., “High-quality GaAs on Sawtooth-patterned Si Substrates,” 59 Applied Physics Letters 19, 1991, pp. 2418-2420.
Jain et al., “Stresses in strained GeSi stripes and quantum structures: calculation using the finite element method and determination using micro-Raman and other measurements,” Thin Solid Films 292, 1997, pp. 218-226.
Jeong, et al., “Performance improvement of InP-based differential HBT VCO using the resonant tunneling diode,” 2006 International Conf. on Indium Phosphide and Related Mat. Conf. Proc., pp. 42-45.
Ju et al., “Epitaxial lateral overgrowth of gallium nitride on silicon substrate,” Journal of Crystal Growth, vol. 263, No. 1-4, Mar. 1, 2004, pp. 30-34.
Kamins et al., “Kinetics of Selective Epitaxial Depostion of Si1-xGex,” Hewlett-Packard Company, Palo Alto, CA, Appl. Phys. Lett. 61 (6), Aug. 10, 1992 (pp. 669-671).
Kamiyama, et al., “UV laser diode with 350.9-nm-lasing wavelength grown by hetero-epitaxial-lateral overgrowth technology,” Selected Topics in Quantum Electronics, IEEE Journal of Selected Topics in Quantum Electronics, vol. 11, No. 5, Sep.-Oct. 2005, pp. 1069-1073.
Kamiyama, et al., “UV light-emitting diode fabricated on hetero-ELO-grown Al0.22Ga0.78N with low dislocation density,” Physica Status Solidi A, vol. 192, No. 2, Aug. 2002, pp. 296-300.
Kawai, et al., “Epitaxial Growth of InN Films and InN Nano-Columns by RF-MBE,” The Institute of Electronics, Information and Communication Engineers, Gijutsu Kenkyu, vol. 13, No. 343 (CPM2003 102-116), 2003, pp. 33-37.
Kazi et al., “Realization of GaAs/AlGaAs Lasers on Si Substrates Using Epitaxial Lateral Overgrowth by Metalorganic Chemical Vapor Deposition,” Japan, Journal of Applied Physics, vol. 40, 2001, pp. 4903-4906.
Kidoguchi et al., “Air-bridged lateral epitaxial overgrowth of GaN thin Films,” Applied Physics Letters, vol. 76, No. 25, Jun. 19, 2000, pp. 3768-3770.
Kim et al., “Silicon-Based Field-Induced Band-to-Band Tunneling Effect Transistor,” IEEE Electron Device Letters, No. 25, No. 6, 2004, pp. 439-441.
Kim et al., “GaN nano epitaxial lateral overgrowth on holographically patterned substrates,” School of Physics and Inter-University Semiconductor Research Center, Seoul National University, Aug. 25-27, 2003, pp. 27-28.
Kimura et al., “Vibronic Fine Structure Found in the Blue Luminescence from Silicon Nanocolloids,” Japan, Journal of Applied Physics, vol. 38, 1999, pp. 609-612.
Klapper, “Generation and Propagation of Dislocations During Crystal Growth,” Mat. Chem. and Phys. vol. 66, 2000, pp. 101-109.
Knall et al., “Threading Dislocations in GaAs Grown with Free Sidewalls on Si mesas,” Journal of Vac. Sci. Technol. B, vol. 12, No. 6, Nov./Dec. 1994, pp. 3069-3074.
Kollonitsch, et al., “Improved Structure and Performance of the GaAsSb/InP Interface in a Resonant Tunneling Diode,” Journal of Crystal Growth, vol. 287, 2006, pp. 536-540.
Krishnamurthy, et al., “I-V characteristics in resonant tunneling devices: Difference Equation Method,” Journal of Applied Physics, vol. 84, Issue 9, Condensed Matter: Electrical and Magnetic Properties (PACS 71-76), 1998, 9.
Krost et al., “GaN-based Optoelectronics on Silicon Substrates,” Materials Science & Engineering, B93, 2002, pp. 77-84.
Sudirgo et al., “Si-Based Resonant Interband Tunnel Diode/CMOS Integrated Memory Circuits,” Rochester Institute of Technology, IEEE, 2006, pp. 109-112.
Kusakabe, K. et al., Characterization of Overgrown GaN layers on Nano-Columns Grown by RF-Molecular Beam Epitaxy, Japan, Journal of Applied Physics, Part 2, vol. 40, No. 3A, 2001, pp. L192-L194.
Kushida et al., “Epitaxial growth of PbTiO3 films on SrTiO3 by RF magnetron sputtering,” Ultrasonics, Ferroelectrics and Frequency Control, IEEE Transactions on Ultrasonics Ferroelectrics and Frequency Control, vol. 38, No. 6, Nov. 1991, pp. 656-662.
Kwok, “Barrier-Injection Transit Time Diode,” Complete Guide to Semiconductor Devices, 2nd ed., Chapter 18, 2002, pp. 137-144.
Lammers, “Trigate and High-k stack up vs. planar,” EETIMES Online, available at: http://www.eetimes.com/showArticle.jhtml?articlelD=188703323&pgno=2&printable=true (Jun. 12, 2006). 2 pages.
Langdo et al., “High Quality Ge on Si by Epitaxial Necking,” Applied Physics Letters, vol. 76, No. 25, Jun. 19, 2000, pp. 3700-3702.
Langdo, “Selective SiGe Nanostructures,” PhD Thesis, Massachusetts Institute of Technology, Jun. 2001, 215 pages.
Lee et al., “Growth of GaN on a nanoscale periodic faceted Si substrate by metal organic vapor phase epitaxy,” Compound Semiconductors: Post-Conference Proceedings, Aug. 25-27, 2003, pp. 15-21.
Lee et al., “Strain-relieved, Dislocation-free InxGa1-xAs/GaAs(001) Heterostructure by Nanoscale-patterned Growth,” Applied Physics Letters, vol. 85, No. 18, Nov. 1, 2004, pp. 4181-4183.
Li et al., “Defect Reduction of GasAs Epitaxy on Si (001) Using Selective Aspect Ratio Trapping,” 91 Applied Physics Letters, 2007, pp. 021114-1-021114-3.
Li et al., “Heteroepitaxy of High-quality Ge on Si by Nanoscale Ge seeds Grown through a Thin Layer of SiO2,” Applied Physics Letters, vol. 85, No. 11, Sep. 13, 2004, pp. 1928-1930.
Li et al., “Monolithic Integration of GaAs/InGaAs Lasers on Virtual Ge Substrates via Aspect-Ratio Trapping,” Journal of the Electrochemical Society, vol. 156, No. 7, 2009, pp. H574-H578.
Li et al., “Morphological Evolution and Strain Relaxation of Ge Islands Grown on Chemically Oxidized Si (100) by Molecular-Beam Epitaxy,” Journal of Applied Physics, vol. 98, 2005, pp. 073504-1-073504-8.
Li et al., “Selective Growth of Ge on Si (100) through Vias of Si02Nanotemplate Using Solid Source Molecular Beam Epitaxy,” Applied Physics Letters, vol. 83, No. 24, Dec. 15, 2003, pp. 5032-5034.
Liang et al., “Critical Thickness enhancement of Epitaxial SiGe films Grown on Small Structures,” Journal of Applied Physics, vol. 97, 2005, pp. 043519-1-043519-7.
Lim et al., “Facet Evolution in Selective Epitaxial Growth of Si by cold-wall ultrahigh vacuum chemical vapor deposition,” Journal of Vac. Sci. Tech., vol. B 22, No. 2, 2004, pp. 682.
Liu et al., “High Quality Single-crystal Ge on Insulator by Liquid-phase Epitaxy on Si Substrates,” Applied Physics Letters, vol. 84, No. 14, Apr. 4, 2004, pp. 2563-2565.
Liu et al., “Rapid Melt Growth of Germanium Crystals with Self Aligned Microcrucibles on Si Substrates,” Journal of the Electrochemical Society, vol. 152, No. 8, 2005, pp. G688-G693.
Loo et al., “Successful Selective Epitaxial Si1-xGexDeposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications,” 150 Journal of Electrochemical Society 10, 2003, pp. G638-G647.
Lourdudoss et al., “Semi-insulating epitaxial layers for optoelectronic devices,” Semiconducting and Insulating Materials Conference, SIMC-XI, 2000, pp. 171-178.
Luan et al., “High-quality Ge Epilayers on Si with Low Threading-dislocation Densities,” Applied Physics Letters, vol. 75, No. 19, Nov. 8, 1999, pp. 2909-2911.
Luan, “Ge Photodetectors for Si Microphotonics,” PhD Thesis, Massachusetts Institute of Technology, Department of Materials Science & Engineering, Jan. 12, 2001, 155 pages.
Lubnow et al., “Effect of III/V-Compound Epitaxy on Si Metal-Oxide-Semiconductor Circuits,” Japan, Journal of Applied Physics, vol. 33, 1994, pp. 3628-3634.
Luo et al., Enhancement of (In,Ga)N Light-Emitting Diode Performance by Laser Liftoff and Transfer From Sapphire to Silicon, IEEE Photonics Technology Letters, vol. 14, No. 10, 2002, pp. 1400-1402.
Luryi et al., “New Approach to the High Quality Epitaxial Growth of Latticed-Mismatched Materials,” Applied Physics Letters, vol. 49, No. 3, Jul. 21, 1986, pp. 140-142.
Ma, et al., “A small signal equivalent circuit model for resonant tunneling diode,” Chinese Physics Letters, vol. 23, No. 8, Aug. 2006, pp. 2292-2295.
Ma, et al., “Fabrication of an AIAs/In0.53/Ga0.47/As/InAs resonant tunneling diode on InP substrate for high-speed circuit applications,” 27 Chinese J. Semiconductors 6, Jun. 2006, pp. 959-962.
Maekawa, et al., “High PVCR Si/Si1-x/Gex DW RTD formed with a new triple-layer buffer,” Materials Science in Semiconductor Processing, vol. 8, 2005, pp. 417-421.
Maezawa, et al., “Metamorphic resonant tunneling diodes and its application to chaos generator ICs,” 44 Jap. J. Applied Physics, Part 1, No. 7A, Jul. 2005, pp. 4790-4794.
Maezawa, et al., “InP-based resonant tunneling diode/HEMT integrated circuits for ultrahigh-speed operation,” IEEE Nagoya University, Institute for Advanced Research, 2006, pp. 252-257.
Martinez et al., “Characterization of GaAs Conformal Layers Grown by Hydride Vapour Phase Epitaxy on Si Substrates by Microphotoluminescence Cathodoluminescence and MicroRaman,” Journal of Crystal Growth, vol. 210, 2000, pp. 198-202.
Matsunaga et al., “A New Way to Achieve Dislocation-Free Heteroepitaxial Growth by Molecular Beam Epitaxy: Vertical Microchannel Epitaxy,” Journal of Crystal Growth, vol. 237-239, 2002, pp. 1460-1465.
Matthews et al., “Defects in Epitaxial Multilayers-Misfit Dislocations,” Journal of Crystal Growth, vol. 27, 1974, pp. 118-125.
Monroy, et al., “High UV/visible Contrast Photodiodes Based on Epitaxial Lateral Overgrown GaN layers,” Electronics Letters, vol. 35, No. 17, Aug. 19, 1999, pp. 1488-1489.
Nakano et al., “Epitaxial Lateral Overgrowth of AIN Layers on Patterned Sapphire Substrates,” Source: Physica Status Solidi A, vol. 203, No. 7, May 2006, pp. 1632-1635.
Nam et al., “Lateral Epitaxy of Low Defect Density GaN Layers via Organometallic Vapor Phase Epitaxy,” Applied Physics Letters, vol. 71, No. 18, Nov. 3, 1997, pp. 2638-2640.
Naoi et al., “Epitaxial Lateral Overgrowth of GaN on Selected-area Si (111) Substrate with Nitrided Si Mask,” Journal of Crystal Growth, vol. 248, 2003, pp. 573-577.
Naritsuka et al., “InP Layer Grown on (001) Silicon Substrate by Epitaxial Lateral Overgrowth,” Japan, Journal of Applied Physics, vol. 34, 1995, pp. L1432-L1435.
Naritsuka et al., “Vertical Cavity Surface Emitting Laser Fabricated on GaAs Laterally Grown on Si Substrate,” Electrochemical Society Proceedings, vol. 97, No. 21, pp. 86-90.
Neudeck, et al., “Novel silicon Epitaxy for advanced MOSFET devices,” Electron Devices Meeting, IEDM Technical Digest International, 2000, pp. 169-172.
Neumann et al., “Growth of III-V Resonant Tunneling Diode on Si Substrate with LP-MOVPE,” Journal of Crystal Growth, vol. 248, 2003, pp. 380-383.
Noda, et al., “Current-voltage characteristics in double-barrier resonant tunneling diodes with embedded GaAs quantum rings,” Physica E 32, 2006, pp. 550-553.
Norman, et al., “Characterization of MOCVD Lateral Epitaxial Overgrown III-V Semiconductor Layers on GaAs Substrates,” Compound Semiconductors, Aug. 25-27, 2003, pp. 45-46.
Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority for PCT/US2010/029552, Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., May 26, 2010, 14 pages.
Oehrlein et al., “Studies of the Reactive Ion Etching of SiGe Alloys,” J. Vac. Sci. Tech, A9, No. 3, May/Jun. 1991, pp. 768-774.
Orihashi, et al., “Experimental and theoretical characteristics of sub-terahertz and terahertz oscillations of resonant tunneling diodes integrated with slot antennas,” 44 Jap. J. Applied Physics, Part 1, No. 11, Nov. 2005, pp. 7809-7815.
Parillaud et al., “High Quality InP on Si by Conformal Growth,” Applied Physics Letters, vol. 68, No. 19, May 6, 1996, pp. 2654-2656.
Park et al., “Defect Reduction and its Mechanism of Selective Ge Epitaxy in Trenches on Si(001) Substrates Using Aspect Ratio Trapping,” Mat. Res. Society Symp. Proc., vol. 994, 2007, 6 pages.
Park et al., “Fabrication of Low-Defectivity, Compressively Strained Geon Si0.2Ge0.8Structures Using Aspect Ratio Trapping,” Journal of the Electrochemical Society, vol. 156, No. 4, 2009, pp. H249-H254.
Park et al., “Growth of Ge Thick Layers on Si (001) Substrates Using Reduced Pressure Chemical Vapor Deposition,” 45 Japan, Journal of Applied Physics, vol. 11, 2006, pp. 8581-8585.
Partial International Search for International Application No. PCT/US2006/033859 mailed Jun. 22, 2007, 7 pages.
Partial International Search Report for International Application No. PCT/US2008/004564 completed Jul. 22, 2009, mailed Oct. 16, 2009, 5 pages.
Partial International Search Report for International Application No. PCT/US2008/068377, completed Mar. 19, 2008, mailed Apr. 22, 2008, 3 pages.
PCT International Search Report of PCT/US2009/057493, from PCT/ISA/210, mailed Mar. 22, 2010, Applicant: Amberwave System Corporation et al., 2 pages.
Pidin et al., “MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node,” Symposium on VLSI Technology, Dig. Tech. Papers, 2004, pp. 54-55.
Piffault et al., “Assessment of the Strain of InP Films on Si Obtained by HVPE Conformal Growth,” Indium Phosphide and Related Materials, Conference Proceedings, Sixth International Conference on Mar. 27-31, 1994, pp. 155-158.
Pribat et al., “High Quality GaAs on Si by Conformal Growth,” Applied Physics Letters, vol. 60, No. 17, Apr. 27, 1992, pp. 2144-2146.
Prost, ed. “QUDOS Technical Report,” 2002-2004, 77 pages.
Prost, et al., “High-speed InP-based resonant tunneling diode on silicon substrate,” Proceedings of the 31st European Solid-State Device Research Conf., 2005, pp. 257-260.
Radulovic, et al., “Transient Quantum Drift-Diffusion Modelling of Resonant Tunneling Heterostructure Nanodevices,” Physics of Semiconductors: 27th International Conference on the Physics of Semiconductors—ICPS-27, Jun. 2005 AIP Conf. Proc., pp. 1485-1486.
Reed et al., “Realization of a Three-Terminal Resonant Tunneling Device: The Bipolar Quantum Resonant Tunneling Transistor,” 54 Applied Physics Letters 11, 1989, p. 1034.
Ren et al., “Low-dislocation-density, Nonplanar GaN Templates for Buried Heterostructure Lasers Grown by Lateral Epitaxial Overgrowth,” Applied Physics Letters, vol. 86, No. 11, Mar. 14, 2005, pp. 111901-1-3.
Rim et al., “Enhanced Hole Mobilities in Surface-Channel Strained-Si p-MOSFETs,” 1995 IEDM, pp. 517-520.
Rim et al., “Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SDDOI) MOSFETs,” IEDM Tech. Dig., 2003, pp. 49-52.
Ringel et al., “Single-junction InGaP/GaAs Solar Cells Grown on Si Substrates with SiGe Buffer Layers,” Prog. Photovolt., Res. & Applied, vol. 10, 2002, pp. 417-426.
Rosenblad et al., “A Plasma Process for Ultrafast Deposition of SiGe Graded Buffer Layers,” 76 Applied Physics Letters 4, 2000, pp. 427-429.
Sakai, “Defect Structure in Selectively Grown GaN Films with Low Threading Dislocation Density,” Applied Physics Letters 71, vol. 16, 1997, pp. 2259-2261.
Sakai, “Transmission Electron Microscopy of Defects in GaN Films Formed by Epitaxial Lateral Overgrowth,” 73 Applied Physics Letters 4, 1998, pp. 481-483.
Sakawa et al., “Effect of Si Doping on Epitaxial Lateral Overgrowth of GaAs on GaAs-Coated Si Substrate,” Japan, Journal of Applied Physics, vol. 31, 1992, pp. L359-L361.
Pae, et al., “Multiple Layers of Silicon-on-Insulator Islands Fabrication by Selective Epitaxial Growth,” Electron Device Letters, IEEE, vol. 20, No. 5, May 1999, pp. 194-196.
Sass, et al., “Strain in GaP/GaAs and GaAs/GaP resonant tunneling heterostructures,” Journal of Crystal Growth, vol. 248, Feb. 2003, pp. 375-379.
Schaub, et al., “Resonant-Cavity-Enhanced High-Speed Si photodiode Grown by Epitaxial Lateral Overgrowth,” Photonics Technology Letters, IEEE, vol. 11, No. 12, Dec. 1999, pp. 1647-1649.
Seabaugh et al., Promise of Tunnel Diode Integrated Circuits, Tunnel Diode and CMOS/HBT Integration Workshop, Naval Research Laboratory, Dec. 9, 1999, 13 pages.
Shahidi, et al., “Fabrication of CMOS on Ultrathin SOI Obtained by Epitaxial Lateral Overgrowth and Chemical-Mechanical Polishing,” Electron Devices Meeting, Technical Digest, International, Dec. 9-12, 1990, pp. 587-590.
Shichijo et al., “Co-Integration of GaAs MESFET & Si CMOS Circuits,” 9 Elec. Device Letters 9, Sep. 1988, pp. 444-446.
Shubert, E.F., “Resonant tunneling diode (RTD) structures,” Rensselear Polytechnic Institute, 2003, pp. 1-14.
Siekkinen, et al., “Selective Epitaxial Growth Silicon Bipolar Transistors for Material Characterization,” Electron Devices, IEEE Transactions on Electron Devices, vol. 35, No. 10, Oct. 1988, pp. 1640-1644.
Su et al., “Catalytic Growth of Group III-nitride Nanowires and Nanostructures by Metalorganic Chemical Vapor Deposition,” Applied Physics Letters, vol. 86, 2005, pp. 013105-1-013105-3.
Su et al., “New Planar Self-Aligned Double-Gate Fully-depleted P-MOSFETs Using Epitaxial Lateral Overgrowth (ELO) and selectively grown source/drain (S/D),” 2000 IEEE Int'l. SOI Conf., pp. 110-111.
Suhara, et al, “Characterization of argon fast atom beam source and its application to the fabrication of resonant tunneling diodes,” 2005 International Microprocesses and Nanotechnology Conf. Di. of Papers, 2005, pp. 132-133.
Sun et al., Electron resonant tunneling through InAs/GaAs quantum dots embedded in a Schottky diode with an AIAs insertion layer, 153 J. Electrochemical Society 153, 2006, pp. G703-G706.
Sun et al., “Room-temperature observation of electron resonant tunneling through InAs/AlAs quantum dots,” 9 Electrochemical and Solid-State Letters 5, May 2006, pp. G167-G170.
Sun et al. “InGaAsP Multi-Quantum Wells at 1.5 /splmu/m Wavelength Grown on Indium Phosphide Templates on Silicon,” Indium Phosphide and Related Materials, May 12-16, 2003, pp. 277-280.
Sun et al., “Selective Area Growth of InP on InP Precoated Silicon Substrate by Hydride Vapor Phase epitaxy,” Indium Phosphide and Related Materials Conference, IPRM. 14th, 2002, pp. 339-342.
Sun et al., “Sulfur Doped Indium Phosphide on Silicon Substrate Grown by Epitaxial Lateral Overgrowth,” Indium Phosphide and Related Materials 16th IPRM, May 31-Jun. 4, 2004, pp. 334-337.
Sun et al., “Temporally Resolved Growth of InP in the Opening Off-Oriented from [110] Direction,” Idium Phosphide and Related Materials, Conference Proceedings, 2000 International Conference, pp. 227-230.
Sun et al., “Thermal Strain in Indium Phosphide on Silicon Obtained by Epitaxial Lateral Overgrowth,” 94 Journal of Applied Physics 4, 2003, pp. 2746-2748.
Suryanarayanan et al., “Microstructure of Lateral Epitaxial Overgrown InAs on (100) GaAs Substrates,” Applied Physics Letters, vol. 83, No. 10, Sep. 8, 2003, pp. 1977-1979.
Suzuki, et al., “Mutual injection locking between sub-THz oscillating resonant tunneling diodes,” Japan Science and Technology Agency, IEEE, Joint 30th International Conference on Infrared and Millimeter Waves & 13th International Conference on Terahertz Electronics, 2005, pp. 150-151.
Takasuka et al., “AIGaAs/InGaAs DFB Laser by One-Time Selective MOCVD Growth on a Grating Substrate,” 43 Japan, Journal of Applied Physics, 4B, 2004, pp. 2019-2022.
Takasuka et al., “InGaAs/AIGaAs Quantum Wire DFB Buried HeteroStructure Laser Diode by One-Time Selective MOCVD on Ridge Substrate,” 44 Japan, Journal of Applied Physics, 4B, 2005, pp. 2546-2548.
Tamura et al., “Heteroepitaxy on High-Quality GaAs on Si for Optical Interconnections on Si Chip,” Proceedings of the SPIE, vol. 2400, 1995, pp. 128-139.
Tamura et al., “Threading Dislocations in GaAs on Pre-patterned Si and in Post-patterned GaAs on Si,” Journal of Crystal Growth, vol. 147, 1995, pp. 264-273.
Tanaka et al., “Structural Characterization of GaN Lateral Overgrown on a (111) Si Substrate,” Applied Physics Letters, vol. 79, No. 7, Aug. 13, 2001, pp. 955-957.
Thean et al., “Uniaxial-Biaxial Hybridization for Super-Critical Strained-Si Directly on Insulator (SC-SSOI) PMOS with Different Channel Orientations,” IEEE, 2005, pp. 1-4.
Thelander, et al., “Heterostructures incorporated in one-dimensional semiconductor materials and devices,” Physics of Semiconductors, vol. 171, 2002, 1 page. Abstract Only.
Thompson et al., “A Logic Nanotechnology Featuring Strained-Silicon,” 25 IEEE Electron Device Letters 4, 2004, pp. 191-193.
Tomiya et al., “Dislocation Related Issues in the Degradation of GaN-Based Laser Diodes,” Selected Topics in Quantum Electronics, IEEE Journal of Selected Topics in Quantum Electronics, vol. 10, No. 6, Nov./Dec. 2004, pp. 1277-1286.
Tomiya, “Dependency of crystallographic tilt and defect distribution of mask material in epitaxial lateral overgrown GaN layers,” Applied Physics Letters vol. 77, No. 5, pp. 636-638.
Tran et al., “Growth and Characterization of InP on Silicon by MOCVD,” Journal of Crystal Growth, vol. 121, 1992, pp. 365-372.
Tsai, et al., “InP/InGaAs resonant tunneling diode with six-route negative differential resistances,” 13th European Gallium Arsenide and other Compound Semiconductors Application Symp., 2006, pp. 421-423.
Tsang et al., “The heteroepitaxial Ridge-Overgrown Distributed Feedback Laser,” Quantum Electronics, IEEE Journal of Quantum Electronics, vol. 21, No. 6, Jun. 1985, pp. 519-526.
Tsaur, et al., “Low-Dislocation-Density GaAs epilayers Grown on Ge-Coated Si substrates by Means of Lateral Epitaxial Overgrowth,” Applied Physics Letters, vol. 41, No. 15, Aug. 1982, pp. 347-349.
Tseng et al., “Effects of Isolation Materials on Facet Formation for Silicon Selective Epitaxial Growth,” 71 Applied Physics Letters 16, 1997, pp. 2328.
Tsuji et al., Selective Epitaxial Growth of GaAs on Si with Strained Sort-period Superlattices by Molecular Beam Epitaxy under Atomic Hydrogen Irradiation, J. Vac. Sci. Technol. B, vol. 22, No. 3, May/Jun. 2004, pp. 1428-1431.
Ujiie, et al., Epitaxial Lateral Overgrowth of GaAs on a Si Substrate, 28, Japan, Journal of Applied Physics, vol. 3, Mar. 1989, pp. L337-L339.
Usuda et al., “Strain Relaxation of Strained-Si Layers on SiGe-on-Insulator (SGOI) Structures After Mesa Isolation,” Applied Surface Science, vol. 224, 2004, pp. 113-116.
Usui et al., “Thick GaN Epitaxial Growth with Low Dislocation Density by Hydride Vapor Phase Epitaxy,” vol. 36, Japan, Journal of Applied Physics, 1997, pp. L899-L902.
Vanamu et al., “Epitaxial Growth of High-Quality Ge Films on Nanostructured Silicon Substrates,” Applied Physics Letters, vol. 88, 2006, pp. 204104.1-204-104.3.
Vanamu et al., “Growth of High Quality Ge/Si1-xGexon Nano-scale Patterned Si Structures,” J. Vac. Sci. Technology. B, vol. 23, No. 4, Jul./Aug. 2005, pp. 1622-1629.
Vanamu et al., “Heteroepitaxial Growth on Microscale Patterned Silicon Structures,” Journal of Crystal Growth, vol. 280, 2005, pp. 66-74.
Vanamu et al., “Improving Ge SisGe1-x Film Quality through Growth onto Patterned Silicon Substrates,” Advances in Electronics Manufacturing Technology, Nov. 8, 2004, pp. 1-4.
Vescan et al., “Lateral Confinement by Low Pressure Chemical Vapor Deposition-Based Selective Epitaxial Growth of Si1-xGex/Si Nanostructures,” No. 81, Journal of Applied Physics 10, 1997, pp. 6709-6715.
Vetury et al., “First Demonstration of AIGaN/GaN Heterostructure Field Effect Transistor on GaN Grown by Lateral Epitaxial Overgrowth (ELO),” Inst. Phys. Conf. Ser. No. 162: Ch. 5, Oct. 1998, pp. 177-183.
Walker, et al., “Magnetotunneling spectroscopy of ring-shaped (InGa)As quantum dots: Evidence of excited states with 2pz character,” 32 Physica E 1-2, May 2006, pp. 57-60.
Wang et al, “Fabrication of Patterned Sapphire Substrate by Wet Chemical Etching for Maskless Lateral Overgrowth of GaN,” Journal of Electrochemical Society, vol. 153, No. 3, Mar. 2006, pp. C182-C185.
Ting, et al., “Modeling Spin-Dependent Transport in InAS/GaSb/AISb Resonant Tunneling Structures,” 1 J. Computational Electronics, 2002, pp. 147-151.
Watanabe, et al., “Fluoride resonant tunneling diodes on Si substrates,” IEEE International Semiconductor Device Research Symp. Dec. 2005, pp. 177-178.
Wernersson et al., “InAs Epitaxial Lateral Growth of W Marks,” Journal of Crystal Growth, vol. 280, 2005, pp. 81-86.
Williams et al., “Etch Rates for Micromachining Processing—Part II,” Journal of Microelectromechanical Systems, vol. 4, 1996, pp. 761-778.
Williams et al., “Etch Rates for Micromachining Processing—Part II,” Journal of Microelectromechnical Systems, vol. 5, No. 4, Dec. 1996, pp. 256-269.
Wu et al., “Enhancement-mode InP n-channel metal-oxide-semiconductor field-effect-transistors with atomic-layer-deposited AI2O3 dielectrics,” Applied Physics Letters 91, 022108-022110 (2007).
Wu et al., Gross-Sectional Scanning/Tunneling Microscopy Investigations of Cleaned III-V Heterostructures, Technical report, Dec. 1996, 7 pages.
Wu et al., “Inversion-type enhancement-mode InP MOSFETs with ALD A12O3, HfAIO nanolaminates as high-k gate dielectrics,” Proceedings of the 65th Device Research Conf., 2007, pp. 49-52.
Wuu et al., “Defect Reduction and Efficiency Improvement of Near-Ultraviolet Emitters via Laterally Overgrown GaN on a GaN/Patterned Sapphire Template,” Applied Physics Letters, vol. 89, No. 16, Oct. 16, 2006, pp. 161105-1-3.
Xie et al., “From Porous Si to Patterned Si Substrate: Can Misfit Strain Energy in a Continuous Heteropitaxial Film Be Reduced?” Journal of Vacuum Science Technology, B, vol. 8, No. 2, Mar./Apr. 1990, pp. 227-231.
Xu et al., “Spin-Filter Devices Based on Resonant Tunneling Antisymmetrical Magnetic Semiconductor Hybrid Structures,” vol. 84, Applied Physics Letters 11, 2004, pp. 1955-1957.
Yamaguchi et al., “Analysis for Dislocation Density Reduction in Selective Area Growth GaAs Films on Si Substrates,” Applied Physics Letters, vol. 56, No. 1, Jan. 1, 1990, pp. 27-29.
Yamaguchi et al., “Defect Reduction Effects in GaAs on Si Substrates by Thermal Annealing,” Applied Physics Letters. vol. 53, No. 23, 1998, pp. 2293.
Yamaguchi et al., GaAs Solar Cells Grown on Si Substrates for Space Use: Prog. Photovolt.: Res. Appl., vol. 9, 2001; pp. 191-201.
Yamaguchi et al., “Super-High-Efficiency Multi-junction Solar Cells,” Prog. Photovolt.: Res. Appl., vol. 13, 2005, pp. 125-132.
Yamamoto et al., “Optimization of InP/Si Heteroepitaxial Growth Conditions Using Organometallic Vapor Phase Epitaxy,” Journal of Crystal Growth, vol. 96, 1989, pp. 369-377.
Yang et al., “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” IEDM Tech. Dig., 2003, pp. 453-456.
Yang et al., “Selective Area Deposited Blue GaN-InGaN Multiple-quantum Well Light Emitting Diodes over Silicon Substrates,” Applied Physics Letter, vol. 76, No. 3, Jan. 17, 2000, pp. 273-275.
Yili, et al., “Physics-based hydrodynamic simulation of direct current characteristics in DBRTD,” 29 Chinese J. Electron Devices 2, Jun. 2006, pp. 365-368.
Yin et al., “Ultrathin Strained-SOI by Stress Balance on Compliant Substrates and FET Performance,” 52 IEEE Trans on Electron Devices 10, 2005, pp. 2207-2214.
Dong et al., “Selective area growth of InP through narrow openings by MOCVD and its application to inP HBT,” Indium Phosphide and Related Materials, International Conference, May 12-16, 2003, pp. 389-392.
Yoon et al., “Selective Growth of Ge Islands on Nanometer-scale Patterned SiO2/Si Substrate by Molecular Beam Epitaxy,” Applied Physics Letters, vol. 89, 2006, pp. 063107.1-063107.3.
Yoshizawa et al., “Growth of self-Organized GaN Nanostructures on AI 2O3 (0001) by RF-Radial Source Molecular Beam Epitaxy”, Japan, Journal of Applied Physics, Part 2, vol. 36, No. 4B, 1997, pp. L459-L462.
Zamir et al., Thermal Microcrack Distribution Control in GaN Layers on Si Substrates by Lateral Confined Epitaxy, Applied Physics Letters, vol. 78, No. 3, Jan. 15, 2001, pp. 288-290.
Zang et al., “Nanoheteroepitaxial lateral overgrowth of GaN on nanoporous Si (111),” Applied Physics Letters, vol. 88, No. 14, Apr. 3, 2006, pp. 141925.
Zang et al., “Nanoscale lateral epitaxial overgrowth of GaN on Si (111),” Applied Physics Letters, vol. 87, No. 19 (Nov. 7, 2005) pp. 193106.1-193106.3.
Zela et al., “Single-crystalline Ge Grown Epitaxially on Oxidized and Reduced Ge/Si (100) Islands,” Journal of Crystal Growth, vol. 263, 2004, pp. 90-93.
Zhang et al., “Removal of Threading Dislocations from Patterned Heteroepitaxial Semiconductors by Glide to Sidewalls,” Journal of Electronic Materials, vol. 27, No. 11, 1998, pp. 1248-1253.
Zhang et al., “Strain Status of Self-Assembled InAs Quantum Dots,” Applied Physics Letters, vol. 77, No. 9, Aug. 28, 2000, pp. 1295-1297.
Zheleva et al., “Lateral Epitaxy and Dislocation Density Reduction in Selectively Grown GaN Structures,” Journal of Crystal Growth, vol. 222, No. 4, Feb. 4, 2001, pp. 706-18.
Zubia et al., “Initial Nanoheteroepitaxial Growth of GaAs on Si (100) by OMVPE,” Journal of Electronic Materials, vol. 30, No. 7, 2001, pp. 812-816.
Related Publications (1)
Number Date Country
20140374798 A1 Dec 2014 US
Provisional Applications (1)
Number Date Country
60681940 May 2005 US
Divisions (1)
Number Date Country
Parent 12845593 Jul 2010 US
Child 13681214 US
Continuations (4)
Number Date Country
Parent 14104924 Dec 2013 US
Child 14313699 US
Parent 13903762 May 2013 US
Child 14104924 US
Parent 13681214 Nov 2012 US
Child 13903762 US
Parent 12180254 Jul 2008 US
Child 12845593 US
Continuation in Parts (2)
Number Date Country
Parent 11436198 May 2006 US
Child 12180254 US
Parent 11436062 May 2006 US
Child 12845593 US