Patent Application
20230178428
The instant application relates to semiconductor devices, and in particular relates to methods of forming semiconductor packages and corresponding semiconductor packages.
System Integration is a major development target of the semiconductor industry. In power device applications, there is a need to integrate multiple different devices in a single semiconductor package. For example, an integrated semiconductor package for power applications may include multiple power device dies along with one or more logic dies. This arrangement requires multiple isolated die pads in a single semiconductor package. This can create numerous design challenges. For example, in a lead frame packaging technique, the lead frame may not have sufficient mechanical stability to accommodate multiple die pads and/or the semiconductor dies mounted thereon. Moreover, multi-die packages require a high number of electrical connections, which may be difficult or impossible to effectuate within a desirably small package footprint. Moreover, in power applications, spacing requirements such as creepage and clearance requirements that dictate minimum distances between conductors of different potential, place constraints on the minimum achievable package size.
Thus, there is a need for improved integrated power semiconductor device packages and corresponding methods of manufacture.
A method of forming a semiconductor package is disclosed. According to an embodiment, the method comprises providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate comprising an upper surface that is structured to comprise a first mesa that is elevated from recessed regions of the central metal plate, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body of electrically insulating mold compound on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.
Separately or in combination, the central metal plate comprises a base section of substantially uniform thickness, wherein the first mesa projects upwards from the base section, and wherein thinning the central metal plate comprises removing the base section.
Separately or in combination, a rear surface of the base section is exposed at the lower surface of the encapsulant body before or during the thinning of the central metal plate, and wherein removing the base section comprises processing a rear side of the semiconductor package comprising the lower surface of the encapsulant body and the central metal plate until the base section is completely removed.
Separately or in combination, processing the rear side of the semiconductor package comprises planarizing the rear side of the semiconductor so as to remove material from the encapsulant body and the base section simultaneously, and wherein after the planarizing the lower surface of the encapsulant body is coplanar with an exposed rear surface of the first mesa.
Separately or in combination, processing the rear side of the semiconductor package comprises etching at the exposed rear surface of the base section until the base section is removed.
Separately or in combination, the upper surface of the central metal plate is structured to comprise a second mesa that is elevated from recessed regions of the central metal plate and laterally spaced apart from the first mesa, and wherein thinning the central metal plate isolates the first and second mesas from one another at the lower surface of the encapsulant body.
Separately or in combination, the first mesa is configured as a die pad, and wherein the semiconductor die mounted on the first mesa such that the lower surface of the semiconductor die is at completely disposed on the first mesa.
Separately or in combination, the second mesa is configured as a die pad, wherein the method further comprises mounting a second semiconductor die on the upper surface of central metal plate such that a lower surface of the second semiconductor die is at least partially disposed on the second mesa.
Separately or in combination, the second mesa is configured as a conductive track, and wherein forming the electrical interconnections between terminals of the semiconductor die and the lead frame comprises electrically connecting one of the terminals of the semiconductor die to the second mesa by an electrical interconnect element.
Separately or in combination, the lead frame further comprises a peripheral structure that is connected to the central metal plate by a tie bar, wherein the upper surface of the central metal plate is structured to comprise a tie bar attachment mesa that is elevated from recessed regions of the central metal plate, wherein the tie bar is connected to the tie bar attachment mesa, wherein thinning the central metal plate from the rear surface isolates the first mesa from the tie bar attachment mesa.
Separately or in combination, the method further comprises forming the electrical interconnections comprises providing electrical interconnect elements between the terminals of the semiconductor die and the leads before forming the encapsulant body.
Separately or in combination, the method further comprises providing electrical interconnect elements between the terminals of the semiconductor die and the peripheral structure before forming the encapsulant body.
According to another embodiment, the method comprises providing a lead frame that comprises a central metal plate and a plurality of leads that extend away from outer edge sides of the metal plate, the central metal plate comprising an upper surface that is structured to comprise a plurality of lead extensions that are elevated from recessed regions of the central metal plate and are routed to the leads, mounting a semiconductor die on the upper surface of the central metal plate, electrically connecting terminals of the semiconductor die to the lead extensions, forming an encapsulant body of electrically insulating mold compound on the central metal plate that encapsulates the semiconductor die and exposes outer ends of the leads, and thinning the central metal plate from a rear surface of the central metal plate that is opposite from the upper surface so as to isolate the lead extensions from one another at a lower surface of the encapsulant body.
Separately or in combination, the method further comprises after thinning the central metal plate, providing a layer of electrically insulating material at the lower surface of the encapsulant body that covers the lead extensions.
Separately or in combination, the semiconductor die is mounted on the plurality of lead extensions, and wherein electrically connecting terminals of the semiconductor die comprises flip-chip mounting the semiconductor die such that the terminals of the semiconductor die face and electrically connect with the lead extensions.
Separately or in combination, the central metal plate is structured to comprise a first mesa that is elevated from the recessed regions of the central metal plate, wherein the semiconductor die is mounted on the first mesa, and wherein electrically connecting the terminals of the semiconductor die to the lead extensions comprises providing electrical interconnect elements between the terminals of the semiconductor die and the lead extensions.
Separately or in combination, the lead frame is provided from a lead frame strip that is used to form a plurality of the semiconductor packages, wherein the central metal plate is part of a continuous structure that is used to form each of the semiconductor packages, wherein forming the encapsulant body comprises a molding process that forms the encapsulant material on the continuous structure, and wherein the method further comprises dicing the continuous structure with the encapsulant to singulate the semiconductor package.
Separately or in combination, forming the encapsulant body comprises a molding process that forms the encapsulant material on the central metal plate such that encapsulant material of the encapsulant body surrounds the central metal plate.
Separately or in combination, the upper surface that is structured to comprise an interconnect track that is elevated from the recessed regions of the central metal plate, wherein the method further comprises mounting a second semiconductor die on the upper surface of the central metal plate, electrically connecting one of the terminals of the semiconductor die to the interconnect track, electrically connecting a terminal of the second semiconductor die to the interconnect track.
Separately or in combination, the central metal plate is structured to comprise first and second mesas that are each elevated from the recessed regions of the central metal plate, wherein the semiconductor die is mounted on the first mesa, wherein the second semiconductor die is mounted on the second mesa, wherein electrically connecting one of the terminals of the semiconductor die to the interconnect track comprises providing a first electrical interconnect element between the one of the terminals of the semiconductor die and the interconnect track, and wherein electrically connecting the terminal of the second semiconductor die to the interconnect track comprises providing a second electrical interconnect element between the terminal of the second semiconductor die and the interconnect track.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
Various embodiments of a method of forming a semiconductor package and a corresponding semiconductor package are described herein. According to the method, a lead frame that comprises a central metal plate and a plurality of package leads is provided. An upper surface of the central metal plate is structured to comprise mesas that are elevated from adjacent recessed regions of the central metal plate. For example, the central metal plate can be structured by a half-etching technique, where the mesas correspond to the non-etched regions and the recess which define the mesas correspond to the half-etched regions. The mesas can be used in a variety of different ways. For example, the mesas can be configured as die pad structures that accommodate the mounting of one or more semiconductor dies thereon. Separately or in combination, the mesas can be configured as conductive tracks that are used to provide electrical connections between the semiconductor dies and package leads and/or between two semiconductor dies. In either case, the central metal plate serves as a temporary carrier structure that accommodates the semiconductor dies and associated electrical interconnect elements during assembly. Because the semiconductor dies and associated electrical interconnect elements are each mounted on a single rigid metal structure, a large number of semiconductor elements can be provided in a single package. Moreover, the provision of conductive tracks can alleviate congestion with other electrical interconnect elements, such as bond wires, clips, ribbons, etc. Once the encapsulant body is formed, the central metal plate can be thinned from its rear side until each of the mesas are released from one another and form electrically isolated islands in the encapsulant material. In this way, an integrated semiconductor package with multiple different types of devices may be obtained with a small package footprint.
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An upper surface 106 of the central metal plate 102 is structured to comprise a plurality of mesas 108. The mesas 108 are projections in the upper surface 106 of the central metal plate 102 that are elevated from recessed regions 110 of the central metal plate 102. To this end, the mesas 108 may each comprise outer sidewalls that extend upward from the recessed regions 110 and a substantially planar upper surface that extends between the outer sidewalls. The outer sidewalls of the mesas 108 may form substantially perpendicular angles with the upper surface 106 of the central metal plate 102 in the recessed regions 110 and/or with the upper surfaces of the mesas 108. Alternatively, the outer sidewalls of the mesas 108 may be disposed at oblique angles and/or form gradual transitions with the upper surface 106 of the central metal plate 102 in the recessed regions 110 and/or with the upper surfaces of the mesas 108.
According to an embodiment, the central metal plate 102 comprises a base section 112 with a substantially uniform thickness. That is, a lower part of the central metal plate 102 that is underneath the mesas 108 has a substantially uniform thickness as measured between the upper surface 106 of the central metal plate 102 in the recessed regions 110 and a rear surface 114 (e.g., as seen in
According to an embodiment, the structured upper surface 106 of the central metal plate 102 is formed by a half-etching technique. According to this technique, a substantially uniform thickness sheet of metal comprising, e.g., copper, aluminum, nickel, and alloys or combinations thereof, is provided. Subsequently, the uniform thickness sheet of metal is selectively etched in the desired pattern, wherein the etching is performed to about half the depth of the sheet of metal. In that case, the mesas 108 may correspond to the non-etched regions, i.e., the masked regions, and the recessed regions 110 may correspond to the half-etched regions. If desired, mesas 108 of different heights may be obtained through multiple etching steps. Moreover, the structural features of the lead frame 100 including the features of the central metal plate 102 and the leads 104 can be created by performing any one or more metal processing techniques including, e.g., etching, grinding, stamping, coining, etc.
According to an embodiment, the upper surface 106 of the central metal plate 102 is structured such that some of the mesas 108 are configured as die pad mesas. These die pad mesas are dimensioned to accommodate the mounting of one or more semiconductor dies 116 thereon, wherein the mounting surface corresponds to the upper surface 105 of the mesa 108. For example, as shown, the upper surface 106 of the central metal plate 102 is structured such that three of the mesas 108 are configured as die pad mesas, each of which accommodates the mounting of a semiconductor die 116 thereon.
According to an embodiment, the upper surface 106 of the central metal plate 102 is structured such that some of the mesas 108 are configured as conductive tracks. The conductive tracks are used to form at least part of electrical interconnections between the semiconductor dies 116 and the leads 108 and/or between two of the semiconductor dies 116. These electrical interconnections may be complete connections, or may be parts of electrical connections that comprise other interconnect elements, such as clips, wires, ribbons, etc. Some of the mesas 108 may be configured as lead extensions 118 that are elevated from recessed regions 110 of the central metal plate 102. The lead extensions 118 are conductive tracks in the lead frame 100 that form an interconnection between one or more of the semiconductor dies 116 and the leads 104. The lead extensions 118 are routed to the leads 104, meaning that the lead extensions 118 extend to an edge side of the central metal plate 102 and intersect the leads, thus forming a continuous connection thereto. Additionally, the conductive tracks comprise interconnect tracks 120 that are elevated from the recessed regions 110 of the central metal plate 102. The interconnect tracks 120 form electrical interconnections between two or more semiconductor dies 116 and/or between one or more of the semiconductor dies 116 and the leads 104. Different to the lead extensions 118, the interconnect tracks 120 do not directly adjoin with the leads 104 at the edge side of the central metal plate 102, and thus form an internally isolated structure within the boundaries of the central metal plate 102.
After providing the lead frame 100, one or more semiconductor dies 116 may be mounted on the upper surface 106 of central metal plate 102 such that a lower surface of the semiconductor die 116 is at least partially disposed on one of the mesas 108. As shown, a semiconductor die 116 is mounted on each one of the mesas 108 that are configured as die pad mesas. In this case, the lower surface of each semiconductor die 116 is completely disposed on one of the mesas 108, meaning no part of the semiconductor die 116 overhangs past an edge of the mesa 118 to which it is mounted on. Generally speaking, the semiconductor dies 116 can be any type of device, e.g., discrete transistor, logic device, passive device, etc. In one particular example, two of the semiconductor dies 116 are each configured as discrete power transistors, e.g., MOSGETs, IGBTs, etc., and the third semiconductor die is a logic die that is configured to control a switching operation of the other two devices. This arrangement can be used to form an integrated half-bridge circuit, for example. An adhesive such as solder, sinter, glue or tape may be provided between a rear surface of the semiconductor die 116 and the upper surface 106 of the mesa to which the semiconductor die 116 is mounted on. In the case of a vertical device configuration, this adhesive may also form an electrically conductive connection between a rear surface terminal of the semiconductor die 116 and the upper surface 106 of the mesa to which the semiconductor die 116 is mounted on.
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After providing the lead frame 100, the semiconductor dies 116 are flip-chip mounted on the semiconductor package. Flip-chip mounting refers to a technique whereby a main surface of the semiconductor die 116 comprising terminals of the semiconductor die is mounted to directly face the chip carrier, and electrical connections to the terminals are effectuated using a conductive intermediary, such as a solder balls. Thus, a plurality of solder balls, stud bumps, etc., may be provided on the conductive tracks at the appropriate location and the semiconductor die 116 may be mounted and secured to the lead frame 100 by these features. The semiconductor dies 116 may be mounted on the mesas 108 that form the lead extensions 118, or the mesas 108 that form the interconnect tracks 120, or both. In a difference to the embodiment of
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The upper surface 106 of the central metal plate 102 is structured to comprise a plurality of tie bar attachment mesas 138. The tie bar attachment mesas 138 refer to the mesas 108 in the upper surface 106 of the central metal plate 102 that are disposed at the outer edge of the central metal plate 102 and are connected to the tie bars 136. The tie bar attachment mesas 138 can be created by the same process which forms the mesas 108 that are configured as die pads or conductive tracks, as previously described. However, the tie bar attachment mesas 138 are not electrically connected to any terminal of the semiconductor die 116, and instead serve as physical support structures for temporarily supporting the central metal plate 102.
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The semiconductor package described herein may comprise one or more semiconductor dies 116 with a variety of different configurations. These semiconductor dies 116 may be singulated from a semiconductor wafer (not shown), e.g. by sawing, prior to being mounting on lead frame 100. In general, the semiconductor wafer and therefore the resulting semiconductor die 116 may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, but are not limited to, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenide phosphide (InGaAsP), etc.
In general, the semiconductor dies 116 provided in the semiconductor package described herein can be configured as any active or passive electronic component. Examples of these devices include power semiconductor devices, such as power MISFETs (Metal Insulator Semiconductor Field Effect Transistors) power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), HEMTs (High Electron Mobility Transistors), power bipolar transistors or power diodes such as, e.g., PIN diodes or Schottky diodes, etc. Other examples of these devices include logic devices, such as microcontrollers, e.g., memory circuits, level shifters, etc. One or more of the semiconductor dies 116 can be configured as a so-called lateral device. In this configuration, the terminals of the semiconductor die 116 are provided on a single main surface and the semiconductor die 116 is configured to conduct in a direction that is parallel to the main surface of the semiconductor die 116. Alternatively, one or more of the semiconductor dies 116 can be configured as a so-called vertical device. In this configuration, the terminals of the semiconductor die 116 are provided on opposite facing main and rear surfaces and the semiconductor die 116 is configured to conduct in a direction that is perpendicular to the main surface of the semiconductor die 116.
The term “electrically connected” as used herein describes a permanent low-ohmic, i.e., low-resistance, connection between electrically connected elements, for example a wire connection between the concerned elements. By contrast, the term “electrically coupled” contemplates a connection in which there is not necessarily a low-resistance connection and/or not necessarily a permanent connection between the coupled elements. For instance, active elements, such as transistors, as well as passive elements, such as inductors, capacitors, diodes, resistors, etc., may electrically couple two elements together.
Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second,” and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
