Patent Application
20240105506
The present disclosure generally relates to semiconductor metal interconnect structures, and more particularly, to forming metal interconnect structures between metal layers for better conductivity.
Today, semiconductor fabrication of integrated circuits (ICs) includes front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. The FEOL relates to the first aspect of IC fabrication and includes individual components, such as transistors, capacitors, resistors, inductors, etc. The FEOL includes gate patterning, spacer, extension, and source/drain implantation, silicide formation, and the like. The back-end-of-line (BEOL) is the second aspect of IC fabrication, where conductive wiring interconnect networks are established to form interconnect structures that electrically couple FEOL devices with one another. Typically, the wiring interconnect networks include two types of interconnect elements (often referred to as interconnects) that serve as electrical conductors, namely, conductive lines, such as lines that traverse a distance across the chip, and conductive vias that connect the conductive lines at different levels (typically referred to as metallization layers). The conductive lines and conductive vias are typically made of conductive material, such as aluminum or copper, and are electrically insulated by interlayer dielectrics (ILD).
According to an embodiment, an interconnect structure includes a first metal layer comprising at least one metal wire with a first segment and a local extension having a width in a first direction that is larger than a width of the first segment. A second metal layer is on top or below the first metal layer, comprising at least one metal wire. A via is connected between the at least one metal wire of the first metal layer and the at least one metal wire of the second metal layer. A width of the via in the first direction is larger than the width of the first segment but smaller than a width of the second segment.
In one embodiment, a width of the local extension in a second direction is wider than a width in the second direction of the via.
In one embodiment, the local extension completely envelops a side surface of the via at the first metal layer.
In one embodiment, the first metal layer is vertically below the second metal layer.
In one embodiment, the at least one metal wire of the first metal layer is part of a plurality of metal wires arranged at a minimum wire pitch capability of the first metal layer.
In one embodiment, the local extension is offset from a center of the at least one metal wire of the first metal layer.
In one embodiment, the at least one metal wire of the first metal layer is created by a subtractive etch.
In one embodiment, the via is a dual damascene via.
In one embodiment, the via is self-aligned to the at least one metal wire of the first metal layer.
In one embodiment, the via is not self-aligned to the at least one metal wire of the first metal layer.
A method of interconnecting metal wires on different metal layers includes depositing a first metal layer. The first metal layer is etched to form at least one metal wire with a first segment and a local extension having a width in a first direction that is larger than a width of the first segment. An interlayer dielectric (ILD) layer is deposited. The ILD is deposited to provide an opening for a via. A second metal layer comprising at least one metal wire and the via is provided on top of the first metal layer. The via provides an electrical connection between the at least one metal wire of the first metal layer and the at least one metal wire of the second metal layer. A width of the via in the first direction is larger than the width of the first segment but smaller than a width of the second segment.
In one embodiment, a width of the local extension in a second direction is wider than a width in the second direction of the via.
In one embodiment, the local extension completely envelops a side surface of the via at the first metal layer.
In one embodiment, the first metal layer is vertically below the second metal layer.
In one embodiment, the at least one metal wire of the first metal layer is part of a plurality of metal wires arranged at a minimum wire pitch capability of the first metal layer.
In one embodiment, the local extension is offset from a center of the at least one metal wire of the first metal layer.
In one embodiment, the at least one metal wire of the first metal layer is created by a subtractive etch.
In one embodiment, the via is a dual damascene via.
In one embodiment, the via is self-aligned to the at least one metal wire of the first metal layer.
In one embodiment, the via is not self-aligned to the at least one metal wire of the first metal layer.
These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The drawings are of illustrative embodiments. They do not illustrate all embodiments.
Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps.
In the following detailed description, numerous specific details are set forth by way of examples to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, to avoid unnecessarily obscuring aspects of the present teachings.
In one aspect, spatially related terminology such as “front,” “back,” “top,” “bottom,” “beneath,” “below,” “lower,” above,” “upper,” “side,” “left,” “right,” and the like, is used with reference to the orientation of the Figures being described. Since components of embodiments of the disclosure can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. Thus, it will be understood that the spatially relative terminology is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
As used herein, the terms “lateral” and “horizontal” describe an orientation parallel to a first surface of a chip.
As used herein, the term “vertical” describes an orientation that is arranged perpendicular to the first surface of a chip, chip carrier, or semiconductor body.
As used herein, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together-intervening elements may be provided between the “coupled” or “electrically coupled” elements. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. The term “electrically connected” refers to a low-ohmic electric connection between the elements electrically connected together.
Although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.
It is to be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.
As used herein, certain terms are used indicating what may be considered an idealized behavior, such as, for example, “lossless,” “superconductor,” or “superconducting,” which are intended to cover functionality that may not be exactly ideal but is within acceptable margins for a given application. For example, a certain level of loss or tolerance may be acceptable such that the resulting materials and structures may still be referred to by these “idealized” terms.
The concepts herein relate to forming metal interconnect structures between metal layers with less resistance, and hence, greater conductance. To better appreciate the teachings herein, it may be helpful to briefly discuss known architectures of vias between metal layers. In this regard,
By way of contrast,
As illustrated, the width of the via 206 in a first direction (e.g., perpendicular to the direction of the metal wire 202C) is larger than the width 220 of the first segment but smaller than a width of the local extension. The local extension 210 completely envelops the side surface of the via 206 at the first metal layer, thereby providing additional contact area and less resistance as comparted to conventional interconnect structures, such as that shown in
In one embodiment, the lower metallization layer (e.g., first metal layer) is created by a subtractive etch. The via 206 can be created by either damascene process or a subtractive etch. In this regard, Applicants have determined that a subtractive etch of the lower metal layer as well as the wire extension provides higher quality metal wires (e.g., a tighter pitch). For example, as the dimensions (e.g., pitch) of interconnects shrink, there is a point at which metals such as ruthenium (Ru) or cobalt (Co) become lower in resistivity than traditional metals like copper (Cu). In this regard, Cu is formed using a damascene process, while Ru and Co can be formed using a subtractive process. Benefits of the subtractive process include: there is no etch-induced damage layer in the surrounding dielectric, line heights can be made very large without relying on deep, high-aspect ratio etching into dielectric, and the presence of liner/barrier materials surrounding the interconnect metals are not required. While an interconnect between a first metal layer and a second metal layer is depicted, it will be understood that interconnects between any metal layers are supported by the teachings herein.
In various embodiments, the via connection 206 between the metal wires of the different metal layers has a width larger than the width of the line below, or the via connection between the metal wires of the different metal layers has a width larger than the width of the line above. In this regard,
Reference now is made to
The structures discussed herein can also be fabricated without a self-aligned process. In this regard,
The teachings herein provide various technical benefits, including, without limitation, improving the performance of the circuit using the via structure discussed herein because a lower via resistance is provided by improving (e.g., maximizing) contact are between lines on different metallization levels and vias. The V1BAR shapes can be used without involving an increase in the width and/or pitch of a wiring level vertically below it, thereby providing more design flexibility (e.g., being able to maintain an aggressive metal wiring pitch to which the via is connected thereto).
With the foregoing description of an example interconnect systems of
At act 610, a first metal is deposited on a foundation. In various embodiment, the foundation may be a substrate or a FEOL that may include transistors, capacitors, resistors, inductors, and the like.
At act 620, one or more etching mask layer(s) may be provided, and the layers that are not protected thereby are removed. For example, as is understood by those of ordinary skill in the art, a mask layer (not shown), sometimes referred to as a photomask, may be provided by forming a layer of photoresist material on the metal layer, exposing the photoresist material to a pattern of light, and developing the exposed photoresist material. An etching process, such as a reactive ion etch (RIE), may be used to form patterns (e.g., openings) by removing portions of the first metal layer. After etching, the mask layer may be removed using a conventional plasma ashing or stripping process. Accordingly, the pattern of the mask layer facilitates the subtractive removal of portions of the first metal layer, thereby leaving behind a metal wire that has a local extension that can later be used as a landing area for an enlarged via, discussed in more detail below. Thus, a subtractive etch can be used to form a metal wire on a first metal layer having a local extension on the first metal layer. In the example of
At act 630, an interlayer dielectric layer (ILD) is deposited on top of the metal wire of the first metal layer using conventional deposition techniques. The dielectric layer acts as an insulator to prevent an electrical short between metal wires. In one embodiment, the ILD is a low-k material (e.g., k less than 4.2) based on silicon dioxide (SiO2).
At act 640, a via opening is etched into the ILD using etching techniques discussed herein. The via length is longer than a lower line masking width. For example, the width of the via is larger than the width of the line (i.e., measured in the same direction), such that the via can “wrap-around” the line below.
At act 650, a via and a second metal layer are deposited. In one embodiment, the via and second metal layer comprise a same material and are deposited in a single deposition step, thereby simplifying processing and reducing fabrication cost.
At act 660, the second metal layer is etched to leave behind a metal wire on the second metal layer. In one embodiment, the width of the metal wire on the second metal layer has a minimum width (and a minimum pitch when a plurality of second metal wires are generated).
While the manufacture of a single interconnected structure is described for the purposes of discussion, it will be understood that other configurations, as well as those having multiple interconnected structures at different and multiple metal layers are supported by the teachings herein.
In one aspect, the method and structures as described above may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip can then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from low-end applications, such as toys, to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
While the foregoing has described what are considered to be the best state and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.
The components, steps, features, objects, benefits and advantages that have been discussed herein are merely illustrative. None of them, nor the discussions relating to them, are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.
Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional, and/or different components, steps, features, objects, benefits and advantages. These also include embodiments in which the components and/or steps are arranged and/or ordered differently.
While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term “exemplary” is merely meant as an example, rather than the best or optimal. Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.
It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “a” or “an” does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.
