BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a schematic view of a substrate with embedded capacitors according to the prior art.
FIGS. 2A-2D illustrate a method for fabricating a substrate with vertically embedded capacitors according the first embodiment of the present invention.
FIG. 3 illustrates a cross-section view of forming at least a wiring layer on the substrate with vertically embedded capacitors according to the first embodiment of the present invention.
FIG. 4 illustrates a cross-section view of forming a plurality of bumps on the wiring layer according to the first embodiment of the present invention.
FIGS. 5A-5E illustrate a method for fabricating a substrate 30 with vertically embedded capacitors according to the second embodiment of the present invention.
FIG. 6 illustrates a cross-section view of forming at least a wiring layer on the substrate with vertically embedded capacitors according to the second embodiment of the present invention.
FIG. 7 illustrates a cross-section view of forming a plurality of bumps on the wiring layer according to the second embodiment of the present invention.
DETAILED DESCRIPTION
Please refer to FIGS. 2A-2C. FIGS. 2A-2C illustrate a method for fabricating a substrate with vertically embedded capacitors according the first embodiment of the present invention. As shown in FIG. 2A, a plurality of conductive layers 21 is provided, in which each of the conductive layers 21 is composed of a first dielectric layer 212 and a leading wire layer 211 formed thereon. In the present embodiment, the leading wire layer 211 is fabricated from a sheet metal layer via a series of photolithography processes. Preferably, the leading wire layer 211 is composed of a plurality of leading wires 21 la, in which the leading wires 21 la are used to replace the conventional through holes of a substrate.
As shown in FIG. 2B, a plurality of composite layers 22 is provided, in which each of the composite layers 22 is composed of a second dielectric layer 222 and a patterned electrode layer 221 formed thereon. Preferably, the patterned electrode layer 221 is also fabricated from a sheet metal layer via a series of photolithography processes (not shown). The patterned electrode layer 221 also includes a plurality of electrodes 221 a for forming a plurality of capacitors C, as shown in FIG. 2C. Depending on the demand of the product, the capacitors C can be electrically connected in parallel or series. According to the preferred embodiment of the present invention, the electrodes 221 a are arranged in an array, and the second dielectric layers 222 and the first dielectric layers 212 are made of such as epoxy resin, FR4, BT resin, high polymer materials, or ceramic materials.
Next, as shown in FIG. 2C, the conductive layers 21 and the composite layers 22 are laminated to form a block B. The block B specifically defines a plurality of substrates 20 having vertically embedded capacitors and a plurality of sawing streets B1 between the substrates 20. Preferably, the size of the substrate 20 with vertically embedded capacitors can be adjusted according to the specification of the product. Thereafter, as shown in FIG. 2D, the block B is being sawed along the sawing streets B1 to singularize the substrates 20. Each of the singularized substrates 20 has a first surface 201 and a second surface 202, in which the first surface 201 and the second surface 202 expose the leading wires 211a and the electrodes 221a. The leading wires 211a and the electrodes 221a can be used to electrically connect at least a chip or a circuit device (not shown).
With reference to FIG. 3, at least a wiring layer 23 can also be formed on the first surface 201 and the second surface 202 of the substrate 20. Preferably, the wiring layer 23 can be utilized to establish a connection between the aforementioned chips, circuit devices and the substrate 20 by electrically connecting the leading wires 211a of the leading wire layer 211 and the electrodes 221a of the patterned electrode layer 221. Alternatively, as shown in FIG. 4, a plurality of bumps 24 can be formed on the wiring layer 23 to establish a connection between the chips and the substrate 20 with vertically embedded capacitors.
Please refer to FIGS. 5A-5E. FIGS. 5A-5E illustrate a method for fabricating a substrate 30 with vertically embedded capacitors according to the second embodiment of the present invention. As shown in FIG. 5A, a plurality of conductive layers 31 is provided, in which each of the conductive layers 31 includes a first dielectric layer 312 and a leading wire layer 311 formed thereon. The leading wire layer 311 is composed of a plurality of leading wires 31 la. As shown in FIG. 5B, a plurality of first composite layers 32 is provided, in which each of the first composite layers 32 includes a second dielectric layer 322 and a patterned electrode layer 321 formed thereon. Preferably, each patterned electrode layer 321 includes a plurality of electrodes 321a and the electrodes 321a are arranged in an array. As shown in FIG. 5C, a plurality of second composite layers 33 is provided, in which each of the second composite layers 33 includes a third dielectric layer 332 and a sheet electrode layer 331 formed on the third dielectric layer 332. The third dielectric layer 332, the second dielectric layer 322, and the first dielectric layer 312 can be made of same or different material. Next, as shown in FIG. 5D, the conductive layers 31, the first composite layers 32, and the second composite layers 33 are laminated to form a block B. The block B specifically defines a plurality of substrates 30 with vertically embedded capacitors and a plurality of sawing streets B1 between the substrates 30. Subsequently, as shown in FIG. 5E, the block B is being sawed along the sawing streets B1 to singularize the substrates 30. Each of the singularized substrates 30 has a first surface 301 and a second surface 302, in which the first surface 301 and the second surface 302 expose the leading wires 31 la, the electrodes 321a, and the sheet electrode layers 331. The leading wires 311a, the electrodes 321a, and the sheet electrode layer 331 can be used to electrically connect at least a chip or a circuit device (not shown).
Referring to FIG. 6, at least a wiring layer 34 can be formed on the first surface 301 and the second surface 302 of the substrate 30 with vertically embedded capacitors. The wiring layer 34 is electrically connected to the leading wires 311a of the leading wires layer 311, the electrodes 321a of the patterned electrode layer 321, and the sheet electrode layer 331, such that the chips or the circuit devices can be electrically connected to substrate 30 through the wiring layer 34. Alternatively, as shown in FIG. 7, a plurality of bumps 35 can be formed on the wiring layer 34, such that the chip or the circuit devices can be electrically connected to the substrate 30 through the bumps 35.
FIGS. 5E and 6 further illustrate the structure of the substrate with vertically embedded capacitors of the present invention. As shown in the figures, the substrate 30 includes a plurality of conductive layers 31 and a plurality of first composite layers 32. Each of the conductive layers 31 includes a first dielectric layer 312 and a leading wire layer 311 formed on the first dielectric layer 312, in which the leading wire layer 311 is composed of a plurality of leading wires 311a. The first composite layers 32 are disposed between the conductive layers 31, in which each of the first composite layers 32 includes a patterned electrode layer 321 and a second dielectric layer 322. The patterned electrode layer 321 is composed of a plurality of electrodes 321a arranged corresponding to an array. In the present embodiment, the substrate 30 also includes a plurality of second composite layers 33 formed between the conductive layers 31, in which each of the second composite layers 33 includes a sheet electrode layer 331 and a third dielectric layer 332. Alternatively, the second composite layers 33 can be formed between the first composite layers 32, which are also within the scope of the present invention. By using the vertically embedded capacitors composed of the patterned electrode layers 321 and the second dielectric layers 322, or the sheet electrode layers 331 and the third dielectric layers 332, the present invention could expand the overall space for designing circuit layout and increase the flexibility of the design significantly. Moreover, this fabricating method also minimizes the need for adding external capacitors via surface mount technology, thereby reducing the overall volume and fabrication cost of the package.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Patent Application
20080053690
