1. Field of the Invention
The invention relates generally to methods for fabricating semiconductor structures. More particularly, the invention relates to methods for fabricating semiconductor structures with enhanced flexibility.
2. Description of the Related Art
Semiconductor structures typically comprise patterned layers that may in turn comprise conductor materials, semiconductor materials and/or dielectric materials. The patterned layers may be formed using generally conventional photolithographic and etch methods. Such generally conventional photolithographic and etch methods typically include forming a blanket photdresist layer located over a blanket target layer in turn located over a substrate The blanket photoresist layer is then photoexposed and developed to form a patterned photoresist layer located over the blanket target layer. In turn, the patterned photoresist layer is used as an etch mask layer for forming a patterned target layer from the blanket target layer.
While conventional photolithographic and etch methods are quite common within the semiconductor structure fabrication art, conventional photolithographic and etch methods are nonetheless not entirely without problems within he semiconductor structure fabrication art. In particular, conventional photolithographic and etch methods may yield undesirable region-specific variations in dimension (i.e., in particular a critical dimension linewidth) of a patterned photoresist layer that is used as an etch mask layer. Such region-specific variations of dimension of the patterned photoresist layer may in turn yield region-specific variations of a corresponding patterned target layer that in turn may provide for compromised performance of a semiconductor device from which is comprised the patterned target layer.
Various methods for modifying or controlling dimensions when fabricating semiconductor structures are known in the semiconductor fabrication art.
Particular examples of methods are disclosed within: (1) Dakshina-Murthy et al., in U.S. Pat. No. 6,500,755 (a plasma ashing method for forming a reduced feature size patterned photoresist layer for use as an etch mask layer); (2)(a) Shields et al., in U.S. Pat. No. 6,630,288; (b) Okoroanyanwu et al., in U.S. Pat. No. 6,653,231; (c) Gabriel et al., in U.S. Pat. No. 6,716,571; and (d) Fisher et al., in U.S. Pat. No. 6,828,259 (a sequential electron beam treatment and plasma ashing method for forming a reduced feature size patterned photoresist layer for use as an etch mask layer); (3) Yang et al., in U.S. Pat. No. 6,790,782 (a plasma ashing method that uses a bottom anti-reflective coating (BARC) for forming a reduced feature size patterned photoresist layer for use as an etch mask layer); and (4)(a) Dalcshina-Murthy et al., in U.S. Pat. No. 6,900,139; and (b) Raebiger et al., in U.S. Pat. No. 7,041,434 (specific optical methods for endpoint detection and control when trimming a patterned photoresist layer for use as an etch mask-layer).
Additional particular examples of methods are disclosed within: (1) Livesay, in U.S. Pat. No. 5,468,595 (an electron beam treatment method for insolubilizing certain portions of a blanket photoresist layer when forming a patterned photoresist layer therefrom); (2) Wilbur et al., in U.S. Pat. No. 6,664,500 (a resistor trimming method that uses a laser having a particular output wavelength); (3) Patel et al., in U.S. Pat. No. 6,808,942 (a scatterometer method for determining a patterned photoresist layer trim time); (4) Mui et al., in U.S. Pat. No. 6,858,361 (a feed forward method for controlling a patterned photoresist layer critical dimension within the context of a photoresist trim process); and (5) Mui et al., in U.S. Pat. No. 6,924,088 (a patterned photoresist layer trim method that uses critical dimension measurements from isolated and dense patterns for purposes of considering microloading effects within the patterned photoresist layer trim method).
Control of semiconductor device and semiconductor structure dimensions is likely to be of considerable continued importance as semiconductor device dimensions and semiconductor structure dimensions continue to decrease. Thus, desirable are methods that provide for enhanced flexibility in fabricating semiconductor devices and semiconductor structures with enhanced dimensional control.
The invention includes a method for forming a mask layer (i.e., typically a photoresist mask layer) that in turn may be used as an etch mask when forming a patterned target layer, such as a gate electrode, within a semiconductor structure. The method uses a charged particle beam, such as an electron beam, exposure of at least one mask layer pattern within the mask layer prior to using the mask layer as the etch mask layer.
A method for forming a patterned layer in accordance with the invention includes providing a substrate having a blanket target layer located thereover and a mask layer located over the blanket target layer. The method also includes treating at least one individual mask layer pattern within the mask layer with a charged particle beam to form at least one dimensionally changed mask layer pattern within a dimensionally changed mask layer. The method also includes etching the blanket target layer to form a patterned target layer while using the dimensionally changed mask layer as an etch mask.
Another method for forming a patterned layer in accordance with the invention includes providing a substrate having a blanket target layer located thereover and a mask layer located over the blanket target layer. This other method also includes treating separately at least two individual mask layer patterns within the mask layer with a focused charged particle beam to form at least two separate and differently dimensionally changed mask layer patterns within a dimensionally changed mask layer. Tis other method also includes etching the blanket target layer to form a patterned target layer while using the dimensionally changed mask layer as an etch mask.
The objects, features and advantages of the invention are understood within the context of the Description of the Preferred Embodiment as set forth below. The Description of the Preferred Embodiment is understood within the context of the accompanying drawings, which form a material part of this disclosure, wherein:
The invention, which includes a method for forming a patterned target layer, is described in further detail below within the context of the drawings described above. Since the drawings are intended for illustrative purposes, the drawings are not necessarily drawn to scale.
Although the preferred embodiment illustrates the invention within the context of a semiconductor substrate 10 having a gate dielectric material layer 12 located thereupon and a gate electrode material layer 14 located thereover, the embodiment and the invention are not intended to be so limited. Rather, the embodiment also contemplates that any of several conductor substrates, semiconductor substrates or dielectric substrates may be substituted and used in place of the semiconductor substrate 10 (which absent the optional buried dielectric layer 11 is intended as a bulk semiconductor substrate and which present the optional buried dielectric layer 11 is intended as a semiconductor-on-insulator (SOI) substrate).
In addition, one of the gate dielectric material layer 12 and the gate electrode material layer 14 may also be optional within the invention. Under such circumstances the remaining one of the gate dielectric material layer 12 and the gate electrode material layer 14 may be generally designated as a blanket target layer. Such a blanket target layer may alternatively generally comprise a material selected from the group including but not limited to conductor materials, semiconductor materials and dielectric materials.
Commonly, the semiconductor substrate 10 comprises a semiconductor material. Non-limiting examples of candidate semiconductor materials include silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy and compound semiconductor materials (i.e., such as gallium arsenide, indium arsenide and indium phosphide semiconductor materials). Typically, the semiconductor substrate 10 has a thickness from about 0.5 to about 1.5 mm. The optional buried dielectric layer 11 will typically comprise an oxide, nitride or oxynitride of the base semiconductor material from which is comprised the semiconductor substrate 10. Other dielectric materials are not excluded. Typically, the optional buried dielectric layer has a thickness from about 1400 to about 1600 angstroms.
Commonly the gate dielectric material layer 12 comprises a gate dielectric material selected from the group including but not limited to generally lower dielectric constant gate dielectric materials (i.e., having a dielectric constant from about 4 to about 20) and generally higher dielectric constant gate dielectric materials (i.e., having a dielectric constant from about 20 to at least about 100). The former typically comprise oxides, nitrides and oxynitrides of silicon, although similar compounds comprising elements other than silicon are not excluded. The latter typically include heavier metal oxides and multiple metal oxides. Typically, the gate dielectric material layer 12 comprises a thermal silicon oxide gate dielectric material that has a thickness from about 10 to about 50 angstroms.
The gate electrode material layer 14 comprises a gate electrode material. Candidate gate electrode materials include certain metals, metal alloys, metal silicides and metal nitrides, as well as doped polysilicon (having a dopant concentration from about 1 e18 to about 1 e22 dopant atoms per cubic centimeter) and polycide (doped polysilicon/metal silicide stack) gate electrode materials. Typically, the gate electrode material layer has a thickness from about 100 to about 300 angstroms.
Finally, the mask layers 16a and 16b typically comprise a photoresist material, although the embodiment is not necessarily so limited. Non-limiting examples of candidate photoresist materials include positive photoresist materials, negative photoresist materials and hybrid photoresist materials. The mask layers 16a and 16b when comprising a photoresist material are formed incident to photoexposure and development of a blanket photoresist material layer. Photoexposure wavelengths for the blanket photoresist material layer may vary, but will typically include 157, 193, 248 and 365 nm photoexposure wavelengths. Typically, each of the mask layers 16a and 16b has a thickness from about 1500 to about 23000 angstroms and a linewidth from about 450 angstroms to about 2 microns.
Such a dimensional decrease of the mask layer 16a to form the mask layer 16a′ when using the electron beam 19a irradiation is typical when the mask layer 16a comprises a photoresist material that is exposed using 157 nm or 193 nm photoexposure radiation. However, the embodiment and the invention also contemplate that the mask layer 16a may also be dimensionally increased to form a mask layer 16a″ that is illustrated in phantom in
The spacers 18 may comprise any of several spacer materials. Non-limiting examples include conductor spacer materials and dielectric spacer materials, with dielectric spacer materials being considerably more common. Typically the spacers 18 are formed using a blanket layer deposition and anisotropic etchback method.
The source/drain regions 20 are formed using a two step ion implantation method. A first step within the two step ion implantation method uses the gate electrodes 14a and 14b absent the spacers 18 as a mask to form extension regions that are located beneath the spacers 18. A second step within the two step method uses the gate electrodes 14a and 14b with the spacers 18 as a mask to form larger contact region portions of the source/drain regions 20 that incorporate extension region portions of the source/drain regions 20.
As is illustrated within the schematic cross-sectional diagram of
The graphs of