Patent Application
20190326416
The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a field-effect transistor and methods of forming a structure for field-effect transistor.
Device structures for a field-effect transistor generally include a body region, a source and a drain defined in the body region, and a gate structure configured to apply a control voltage that switches carrier flow in a channel formed in the body region. When a control voltage that is greater than a designated threshold voltage is applied, carrier flow occurs in the channel between the source and drain to produce a device output current.
Contacts may provide vertical electrical connections to features of semiconductor devices, such as the gate structure and source/drain regions of a field-effect transistor. Self-aligned contacts (SAC) are formed in contact openings that are constrained during etching by the configuration of adjacent structures, e.g., sidewall spacers on adjacent gate structures, as opposed to being constrained by a patterned resist. For example, a self-aligned contact may be formed in a contact opening that is defined by selectively etching one material, e.g., silicon dioxide, of an interlayer dielectric layer relative to other materials, such as silicon nitride caps on adjacent gate structures. The formation of the silicon nitride caps involves the deposition of a layer of silicon nitride over the gate structures and interlayer dielectric layer, followed by a chemical-mechanical polish that removes the deposited silicon nitride from over the interlayer dielectric layer. Due to poor selectivity between silicon dioxide and silicon during the chemical-mechanical polish, gate heights and within-wafer uniformity may exhibit a large variation.
Improved structures for a field-effect transistor and methods of forming a structure for field-effect transistor are needed.
In an embodiment of the invention, a method includes forming a gate electrode arranged in a lower portion of a trench in an interlayer dielectric layer, forming a liner inside an upper portion of the trench and over a top surface of the interlayer dielectric layer, and depositing a dielectric material in an upper portion of the trench and over the liner on the top surface of the interlayer dielectric layer. The dielectric material is polished with a polishing process to remove the dielectric material from the liner on the top surface of the interlayer dielectric layer and to form a cap comprised of the dielectric material in the upper portion of the trench. The liner on the interlayer dielectric layer operates as a polish stop during the polishing process.
In an embodiment of the invention, a structure includes a semiconductor substrate, an interlayer dielectric layer including a trench extending to the semiconductor substrate, and a gate electrode in a lower portion of the trench. The structure further includes a liner in an upper portion of the trench over the gate electrode, and a dielectric cap in the upper portion of the trench over the liner.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
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The interlayer dielectric layer 14 may be deposited over the semiconductor substrate 10. The interlayer dielectric layer 14 may be comprised of a dielectric material, such as silicon dioxide (SiO2). Trenches may be formed in the interlayer dielectric layer 14 using lithography and etching that extend from a top surface 13 of the interlayer dielectric layer 14 to the semiconductor substrate 10. The sidewall spacers 20 are formed inside the trenches by depositing a conformal layer of dielectric material with atomic layer deposition (ALD) and etching the deposited conformal layer with a directional etching process, such as reactive ion etching (RIE). The sidewall spacers 20 may be comprised of a low-k dielectric material, such as silicon oxycarbonitride (SiOCN). Following the formation of the sidewall spacers 20, the gate structures 12 may be formed inside the trenches by depositing a series of layers with optional chamfering and planarizing the deposited layers with chemical-mechanical polishing (CMP). The gate dielectric 16 may be comprised of a dielectric material, such as a high-k dielectric material like hafnium oxide (HfO2) that has a dielectric constant (e.g., permittivity) higher than the dielectric constant of silicon dioxide (SiO2), deposited by atomic layer deposition (ALD). The gate electrode 18 may include one or more conformal barrier metal layers and/or work function metal layers, such as layers comprised of titanium aluminum carbide (TiAlC) and/or titanium nitride (TiN), and a metal gate fill layer comprised of a conductor, such as tungsten (W), deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. The barrier metal layers and/or work function metal layers and metal gate fill layer of the gate electrode 18 may be selected for either an n-type field-effect transistor or a p-type field-effect transistor. In an alternative embodiment, the gate structures 12 may be formed by a replacement metal gate process.
Source/drain regions 22 are also arranged in the gaps between adjacent gate structures 12 and below the sections of the interlayer dielectric layer 14. As used herein, the term “source/drain region” means a doped region of semiconductor material that can function as either a source or a drain of a field-effect transistor. For an n-type field-effect transistor, the semiconductor material of the source/drain regions 22 may be doped with an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P) or arsenic (As)) that is effective to produced n-type conductivity. For a p-type field-effect transistor, the semiconductor material of the source/drain regions 22 may be doped with a p-type dopant selected from Group III of the Periodic Table (e.g., boron (B)) that is effective to produce p-type conductivity. The source/drain regions 22 may be formed by, for example, epitaxial growth of in situ-doped semiconductor material. The source/drain regions 22 are covered by a contact etch stop layer (CESL) 24, which may be constituted by a thin layer of silicon nitride (Si3N4).
The device structure that includes the gate structures 12 and source/drain regions 22 may be fabricated during front-end-of-line (FEOL) processing by complementary metal oxide semiconductor (CMOS) processes. The device structure may be, for example, a planar field-effect transistor or a fin-type field-effect transistor.
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Processing continues by removing the sections of the interlayer dielectric layer 14 from the gaps between the gate structures 12 with self-aligned contact (SAC) etching that forms contact openings extending to the source/drain regions 22, and filling the contact openings with a conductor, such as a metal silicide, to form contacts coupled with the source/drain regions 22. The device structure may be either a long channel device or a short channel device
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The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product.
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the “horizontal”, as just defined. The term “lateral” refers to a direction within the horizontal plane. Terms such as “above” and “below” are used to indicate positioning of elements or structures relative to each other as opposed to relative elevation.
A feature “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
