Magnetic random access memory (MRAM) is one of the leading candidates for next-generation memory technologies that aim to surpass the performance of various existing memories. MRAM offers comparable performance to volatile static random access memory (SRAM) and comparable density with lower power consumption to volatile dynamic random access memory (DRAM). As compared to non-volatile flash memory, MRAM offers much faster access speed and suffers minimal degradation over time. Spin orbit torque MRAM (SOT-MRAM) is a type of MRAM. As compared to spin transfer torque MRAM (STT-MRAM), which is another type of MRAM, SOT-MRAM offers better performance in terms of speed and endurance. Nevertheless, further reducing switching energy of SOT-MRAM is limited.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
According to various embodiments, a magnetic random access memory (MRAM) device includes strings of unit cells. Each string of unit cells includes a spin-orbit torque line and a plurality of magnetic tunnel junctions (MTJs). The MTJs of a string are simultaneously programmed by applying an in-plane charge current to the spin-orbit torque line of the string and also applying a spin transfer current to each MTJ of the string. In this way, the MRAM device is a spin transfer torque-assisted spin-orbit torque MRAM device that has a high switching speed and thus a low write latency. The MTJs are interconnected by metallization patterns with a layout that allows for a high unit cell density.
Each unit cell 102 includes a magnetic tunnel junction (MTJ) 108. The MTJ 108 acts as a storage element. Magnetization orientations of ferromagnetic layers in the MTJ 108 determine an electrical resistance of the MTJ 108. The MTJ 108 has a low-electrical resistance state when the magnetization orientations of its ferromagnetic layers are in a parallel state. The MTJ 108 has a high-electrical resistance state when the magnetization orientations of its ferromagnetic layers are in an anti-parallel state. By altering the magnetization orientations of the ferromagnetic layers in the MTJ 108, the MTJ 108 can be programmed to store complementary logic states (e.g., the high-electrical resistance state indicating a logic high state and the low-electrical resistance state indicating a logic low state).
The MTJs 108 may be perpendicular MTJs, in-plane MTJs, or the like. The MTJs 108 may be programmed by utilizing a spin Hall effect. Each MTJ 108 is formed on a portion of a spin-orbit torque (SOT) line 106, such that the MTJ 108 of each unit cell 102 is coupled to the SOT line 106 for that unit cell 102. The SOT line 106 may be referred to as a spin hall electrode (SHE), a spin hall structure, or an SOT structure, and is used to switch a magnetization orientation and electrical resistance of an MTJ 108. During a programming operation, an in-plane charge current passing through the SOT line 106 is converted to a perpendicular spin current via the spin Hall effect. The perpendicular spin current flows along a ferromagnetic layer of the MTJ 108 and changes the magnetization orientation of the ferromagnetic layer via spin-orbit torque (SOT). In this way, the magnetization orientations of the MTJ 108 (e.g., the electrical resistance of the MTJ 108) can be altered so that a bit data can be programmed into the MTJ 108. More specifically, a perpendicular spin current is flown along a ferromagnetic layer of the MTJ 108 to reset the orientation of the ferromagnetic layer to a neutral state, and a spin transfer current is applied to the MTJ 108 to switch the orientation of the ferromagnetic layer via spin transfer torque (STT). Utilizing both SOT and STT to program the orientation of the ferromagnetic layer can help switch the orientation of the ferromagnetic layer more quickly than utilizing SOT/STT alone. As such, the memory device 100 may be referred to as a STT-assisted spin-orbit torque MRAM (SOT-MRAM) device. During a read operation, the resistance state of an MTJ 108 can be sensed and the bit data stored in the MTJ 108 can be read out.
Each unit cell 102 further includes an access transistor AT. The access transistor AT in each unit cell 102 is coupled to the MTJ 108 and the bit line BL for the unit cell 102. The access transistors AT may be three-terminal devices. A gate terminal of each access transistor AT is coupled to one of the word lines WL. The access transistor AT in each unit cell 102 is coupled to the MTJ 108 through a first source/drain terminal and is coupled to one of the bit lines BL through a second source/drain terminal. A terminal of each MTJ 108 is coupled to an underlying portion of an SOT line 106, and the other terminal of each MTJ 108 is coupled to one of the bit lines BL through an access transistor AT.
The unit cells 102 are grouped into strings. Each string of unit cells 102 includes multiple MTJs 108, the access transistors AT for those MTJs 108, a shared SOT line 106, a string bit line SBL, a string source line SSL. The MTJs 108 of each string are directly coupled to the SOT line 106 of the string. Additionally, each string of the unit cells 102 includes a write transistor WT and (optionally) a source transistor ST. The write transistor WT and the source transistor ST may be coupled to portions of the SOT line 106 at opposite sides of the MTJs 108 on that SOT line 106, such that the MTJs 108 stand on a current path (e.g., the path for the previously described in-plane charge current) between the write transistor WT and the source transistor ST. Specifically, the MTJs 108 are spaced apart along the SOT line 106 between the write transistor WT and the source transistor ST. Accordingly, the MTJ 108 can be programmed by the in-plane charge current. The write transistors WT and the source transistors ST may be three-terminal devices. A gate terminal of each write transistor WT and source transistors ST may be coupled to the word line WL for the string. The write transistor WT of each string of unit cells 102 is coupled to the SOT line 106 for the string through a first source/drain terminal and is coupled to one of the string bit lines SBL through a second source/drain terminal. The source transistor ST of each string of unit cells 102 is coupled to the SOT line 106 for the string through a first source/drain terminal and is coupled to one of the string source lines SSL through a second source/drain terminal. In the illustrated embodiment, each string of unit cells 102 corresponds to a row of unit cells 102. In another embodiment (subsequently described), each row includes multiple strings of unit cells 102.
A word line driver 112 is coupled to the word lines WL. The word line driver 112 includes any acceptable circuit that is configured to control switching of the write transistors WT and the source transistors ST through the word lines WL. A current source 114 is coupled to the string source lines SSL and the string bit lines SBL. The current source 114 includes any acceptable circuit that is configured to provide a current (e.g., the previously described in-plane charge current) for programming the MTJs 108 as well as a read current for sensing the resistance states of the MTJs 108. The current source 114 is used in conjunction with the word line driver 112. A bit line driver 116 is coupled to the bit lines BL. The bit line driver 116 includes any acceptable circuit that is configured to sense the read current passing through the MTJs 108 (in order to identify the resistance states of the MTJs 108) and is further configured to provide a current (e.g., the previously described spin transfer current) for programming the MTJs 108.
The first write current Iwi is provided by setting a voltage difference between the string source line SSL and the string bit line SBL with the current source 114 (see
The second write current IW2 is provided on the bit lines BL by the bit line driver 116 (see
In some embodiments, alternating read currents IR have opposite directions. For example, the read currents IR through a first subset (e.g., even ones) of the MTJs 108 in a string may have a first (e.g., positive) direction, while the read currents IR through a second subset (e.g., odd ones) of the MTJs 108 in the string may have a second (e.g., negative) direction. The direction of the read currents IR may be controlled by selection of the voltage difference between a bit line BL and the string source line SSL. When a bit line BL is set to a lesser voltage than the string source line SSL, the corresponding read current IR may have a first (e.g., positive) direction, and when a bit line BL is set to a greater voltage than the string source line SSL, the corresponding read current IR may have a second (e.g., negative) direction. The magnitude of the voltage drop across the corresponding MTJ 108 indicates whether the MTJ 108 is in the high-resistance state or the low-resistance state. Utilizing alternating read currents IR may help avoid read current accumulation in the SOT line 106.
In some embodiments, each read current IR has a same direction. For example, the read currents IR through each of the MTJs 108 in a string may have a first (e.g., positive) direction or a second (e.g., negative) direction. In such embodiments, voltage difference between the bit lines BL and the string source line SSL is large, so as to avoid read current accumulation in the SOT line 106.
The semiconductor substrate 120 may be silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 120 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multilayered or gradient substrates, may also be used. Devices are at the active surface of the semiconductor substrate 120. The devices may be active devices or passive devices. For example, the devices may be transistors, diodes, capacitors, resistors, or the like. The devices include the write transistor WT, source transistor ST, and access transistors AT (see
The interconnect structure 130 interconnects the devices of the semiconductor substrate 120 to form the memory device 100. The interconnect structure 130 includes multiple metallization layers M1-M3. Although three metallization layers M1-M3 are illustrated, it should be appreciated that more or less metallization layers may be included. Each of the metallization layers M1-M3 includes metallization patterns in dielectric layers (subsequently described). The metallization patterns are electrically coupled to the devices of the semiconductor substrate 120, the MTJs 108, and the SOT lines 106.
The MTJs 108 and the SOT lines 106 are included in the interconnect structure 130. The MTJs 108 can be in any of the metallization layers M1-M3, and are illustrated as being in a second metallization layer M2. The MTJs 108 and the SOT lines 106 are electrically connected to the devices of the semiconductor substrate 120. As will be subsequently described in greater detail, the process utilized to form the memory device 100 allows shared SOT lines 106 to be formed directly on corresponding MTJs 108.
In
A first metallization layer M1 of the interconnect structure 130 is formed over the semiconductor substrate 120. The first metallization layer M1 may be formed using any acceptable back end of line (BEOL) process. For example, an IMD 132 may be formed over the semiconductor substrate 120, and a metallization pattern 134 may be formed in the IMD 132. The IMD 132 may be formed of any suitable dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like, which may be formed by any acceptable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The metallization pattern 134 is formed in the IMD 132. The metallization pattern 134 may be formed of any suitable conductive material, such as copper, aluminum, tungsten, silver, and combinations thereof, or the like. The metallization pattern 134 may formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. After the damascene process, the top surfaces of the metallization pattern 134 are substantially coplanar (within process variations) with the top surface of the IMD 132.
The metallization pattern 134 includes metal pads and metal vias that are electrically connected to the devices of the semiconductor substrate 120. A subset of the metal pads/vias 134M will be subsequently utilized for connecting overlying MTJs to the access transistors AT (see
The metal vias 134M/134B are arranged in rows, with each row of metal vias 134B between two rows of the metal vias 134M. A group G1 of the metal vias 134M/134B is between a group G2 of the metal vias 134SBL/134H and a group G3 of the metal vias 134SSL/134H. Forming the metal vias with such a layout allows the features for each string of unit cells 102 (see
In
The metallization pattern 144 includes metal vias that are electrically connected to the metallization pattern 134. A subset of the metal vias 144M are connected to the metal pads/vias 134M. MTJs will be subsequently formed on the metal vias 144M, which act as bottom electrodes for the subsequently formed MTJs. A subset of the metal vias 144B are connected to the metal pads/vias 134B. A subset of the metal vias 144SBL are connected to the metal pads/vias 134SBL. A subset of the metal vias 144SSL are connected to the metal pads/vias 134SSL. A subset of the metal vias 144H are connected to the metal pads/vias 134H.
The metal vias 144B/144SBL/144SSL/144H may (or may not) have a different shape than the metal vias 144M in a top-down view. In some embodiments, the metal vias 144B/144SBL/144SSL/144H have a first shape (e.g., a rectangular shape) in the top-down view, and the metal vias 144M have a second shape (e.g., a circular shape) in the top-down view.
In
The fixed layer 146A may be formed of a ferromagnetic material with a greater coercivity field than the free layer 146C, such as cobalt iron (CoFe), cobalt iron boron (CoFeB), a combination thereof, or the like. In some embodiments, the fixed layer 146A has a synthetic ferromagnetic (SFM) structure, in which the coupling between magnetic layers is ferromagnetic coupling. In some embodiments, the fixed layer 146A has a synthetic antiferromagnetic (SAF) structure including a plurality of magnetic metal layers separated by a plurality of non-magnetic spacer layers. The magnetic metal layers may be formed of Co, Fe, Ni, or the like. The non-magnetic spacer layers may be formed of Cu, Ru, Ir, Pt, W, Ta, Mg, or the like. For example, the fixed layer 146A may have a Co layer and repeated (Pt/Co)x layers over the Co layer, with x representing a repeating number that can be any integer greater than or equal to 1.
The barrier layer 146B may be formed of a dielectric material, such as MgO, AlO, AlN, a combination thereof, or the like. The barrier layer 146B is thinner than the other layers of the MTJ film stack 146. The barrier layer 146B may have a thickness in the range of 1 nm to 10 nm.
The free layer 146C may be formed of a suitable ferromagnetic material such as CoFe, NiFe, CoFeB, CoFeBW, a combination thereof, or the like. The free layer 146C may also adopt a synthetic ferromagnetic (SFM) structure, with the thickness of the non-magnetic spacer layers adjusted to achieve ferromagnetic coupling between the separated magnetic metals, e.g., causing the magnetic moment to be coupled in the same direction. The magnetic moment of the free layer 146C is programmable, and the resistances of the resulting MTJs is accordingly programmable. Specifically, the resistances of the resulting MTJs can be changed between a high-electrical resistance state and a low-electrical resistance state based on the programmed magnetic moment of the free layer 146C, relative the fixed layer 146A.
Additionally, an electrode seed layer 148 is formed over the MTJ film stack 146. The electrode seed layer 148 is formed of a suitable conductive material for subsequently seeding the deposition of a conductive material with high spin Hall conductivity (subsequently described). In some embodiments, the electrode seed layer 148 is formed of the same material as the subsequently formed conductive material.
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The MTJs 108 (and electrode seed structures 150) are formed on the metal vias 144M (see also
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The metallization pattern 164 includes metal pads and metal vias that are electrically connected to the metallization pattern 144 (see
In
The metallization pattern 174 includes metal lines and metal vias that are electrically connected to the metallization pattern 164 (see
The metallization patterns 134, 144, 164, 174 interconnect the MTJs 108, the SOT lines 106, and the devices of the semiconductor substrate 120 to form the memory device 100. Therefore, an integrated circuit implementing the memory device 100 of
Various metal pads/vias in the metallization layers M1-M3 may be aligned such that their centers are disposed along a same vertical axis. In some embodiments, the bit lines BL are connected to the source/drain regions 122 of the access transistors AT by an aligned set of metal pads/vias. In some embodiments, the MTJs 108 are connected to the source/drain regions 122 of the access transistors AT by an aligned set of metal pads/vias. In some embodiments, the string bit lines SBL are connected to the source/drain regions 122 of the write transistors WT by an aligned set of metal pads/vias. In some embodiments, the string source lines SSL are connected to the source/drain regions 122 of the source transistors ST by an aligned set of metal pads/vias. In some embodiments, the SOT lines 106 are connected to the source/drain regions 122 of the write transistors WT and the source transistors ST by an aligned set of metal pads/vias.
Embodiments may achieve advantages. Forming the SOT lines 106 by initially forming the electrode seed structures 150 on the MTJs 108 and then subsequently forming/patterning the electrode layer 154 on the electrode seed structures 150 may be advantageous. Specifically, the electrode seed structures 150 may be exposed through the IMD 152 with a recessing process, instead of utilizing a CMP process to expose the MTJs 108 through the IMD 152. Risk of damage to the MTJs 108 may thus be reduced even when the resulting SOT lines 106 are disposed directly on the MTJs 108. No intervening layers are between the SOT lines 106 and the MTJs 108, thereby reducing the contact resistance of the MTJs 108. Additionally, forming the metallization patterns 134, 144, 164, 174 with the previously described layout allows the memory device 100 to be formed to a greater density. Specifically, each string of unit cells 102 (see
The MTJs 108 and the SOT lines 106 are included in the interconnect structure 130. The MTJs 108 can be in any of the metallization layers M1-M3, and are illustrated as being in a second metallization layer M2. The MTJs 108 and the SOT lines 106 are electrically connected to the devices of the semiconductor substrate 120. As will be subsequently described in greater detail, the process utilized to form the memory device 100 allows MTJs 108 to be formed directly on corresponding shared SOT lines 106. Additionally, in this embodiment, the structure of the MTJs 108 may be reversed. Accordingly, the free layer 146C may be the bottom layer of the MTJ film stack 146, and the fixed layer 146A may be the top layer of the MTJ film stack 146.
In
A first metallization layer M1 of the interconnect structure 130 is formed over the semiconductor substrate 120. The first metallization layer M1 may be formed using any acceptable back end of line (BEOL) process. For example, an IMD 132 may be formed over the semiconductor substrate 120, and a metallization pattern 134 may be formed in the IMD 132. The IMD 132 and the metallization pattern 134 may be formed in a similar manner as described for
The metallization pattern 134 includes metal pads and metal vias that are electrically connected to the devices of the semiconductor substrate 120. A subset of the metal pads/vias 134M will be subsequently utilized for connecting overlying MTJs to the access transistors AT (see
The metal vias 134M/134B are arranged in rows, with each row of metal vias 134B between two rows of the metal vias 134M. A group G1 of the metal vias 134M/134B is between a group G2 of the metal vias 134SBL/134H and a group G3 of the metal vias 134SSL/134H. Forming the metal vias with such a layout allows the features for each string of unit cells 102 (see
In
An MTJ film stack 146 (including a fixed layer 146A, a barrier layer 146B, and a free layer 146C) is formed on the electrode layer 154. The MTJ film stack 146 may be formed in a similar manner as described for
An electrode layer 182 is formed on the MTJ film stack 146. The electrode layer 182 may be formed of any suitable conductive material, such as copper, aluminum, tungsten, silver, and combinations thereof, or the like, which may be formed by plating (e.g., electroplating or electroless plating), deposition (e.g., PVD), combinations thereof, or the like.
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In some embodiments, the step of
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The metallization pattern 156 includes metal vias that are electrically connected to the metallization pattern 134. A subset of the metal vias 156M are connected to the metal pads/vias 134M. A subset of the metal vias 156B are connected to the metal pads/vias 134B. A subset of the metal vias 156SBL are connected to the metal pads/vias 134SBL. A subset of the metal vias 156SSL are connected to the metal pads/vias 134SSL.
In
A metallization pattern 164 is formed in the IMD 162, thereby completing formation of a second metallization layer M2 of the interconnect structure 130. The metallization pattern 164 may be formed in a similar manner as described for
The metallization pattern 164 includes metal lines that are electrically connected to the metallization pattern 156 and the top electrodes 188. A subset of the metal lines 164M connect the metal vias 156M to the top electrodes 188. A subset of the metal lines 164B are connected to the metal vias 156B. A subset of the metal lines 164SBL are connected to the metal vias 156SBL. A subset of the metal lines 164SSL are connected to the metal vias 156SSL.
In
The metallization pattern 174 includes metal lines and metal vias that are electrically connected to the metallization pattern 164 (see
The metallization patterns 134, 156, 164, 174 interconnect the MTJs 108, the SOT lines 106, and the devices of the semiconductor substrate 120 to form the memory device 100. Therefore, an integrated circuit implementing the memory device 100 of
In the foregoing embodiment, the interconnect structure 130 includes multiple metallization layers M1-M3; the SOT lines 106 and the MTJs 108 are formed the second metallization layer M2; and the bit lines BL, the string bit lines SBL, and the string source lines SSL are formed in the third metallization layer M3. It should be appreciated that the interconnect structure 130 may include other quantities of metallization layers, and that the memory device features may be formed in other layers.
Embodiments may achieve advantages. Forming the SOT lines 106 and then patterning the MTJs 108 directly on the SOT lines 106 may be advantageous. Specifically, manufacturing complexity may be reduced. Additionally, forming the metallization patterns 134, 156, 164, 174 with the previously described layout allows the memory device 100 to be formed to a greater density. Specifically, each string of unit cells 102 (see
In an embodiment, a device includes: a spin-orbit torque line; a write transistor coupling a first end of the spin-orbit torque line to a first source line; a source transistor coupling a second end of the spin-orbit torque line to a second source line; and a plurality of magnetic tunnel junctions coupled to the spin-orbit torque line, the magnetic tunnel junctions being in a current path between the write transistor and the source transistor. In some embodiments, the device further includes: access transistors coupling the magnetic tunnel junctions to bit lines, each of the access transistors coupling a respective one of the magnetic tunnel junctions to a respective one of the bit lines. In some embodiments, the device further includes: a current source coupled to the first source line and the second source line, the current source configured to provide a first write current to the spin-orbit torque line during a programming operation; and a bit line driver coupled to the bit lines, the bit line driver configured to provide second write currents to the bit lines during the programming operation. In some embodiments of the device, the current source provides the first write current to the spin-orbit torque line by setting the first source line to a higher voltage than the second source line. In some embodiments, the device further includes: a bit line driver coupled to the bit lines, the bit line driver configured to provide read currents during a read operation. In some embodiments of the device, the bit line driver provides the read currents to the bit lines by setting a first subset of the bit lines to a greater voltage than the second source line and setting a second subset of the bit lines to a lesser voltage than the second source line. In some embodiments of the device, gates of the access transistors, the write transistor, and the source transistor are coupled to a word line. In some embodiments of the device, the magnetic tunnel junctions are in-plane magnetic tunnel junctions. In some embodiments of the device, the magnetic tunnel junctions are perpendicular magnetic tunnel junctions. In some embodiments of the device, the spin-orbit torque line includes a heavy metal and a light transition metal. In some embodiments of the device, the heavy metal includes platinum, palladium, or tungsten, and where the light transition metal includes scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, or copper.
In an embodiment, a device includes: a first spin-orbit torque line over a semiconductor substrate, the first spin-orbit torque line including an alloy of a heavy metal and a light transition metal; first magnetic tunnel junctions coupled to the first spin-orbit torque line; a first interconnect coupling the first spin-orbit torque line to the semiconductor substrate; and a second interconnect coupling the first spin-orbit torque line to the semiconductor substrate, the first magnetic tunnel junctions spaced apart along the first spin-orbit torque line between the first interconnect and the second interconnect. In some embodiments of the device, the first magnetic tunnel junctions are disposed below the first spin-orbit torque line. In some embodiments, the device further includes: third interconnects beneath the first magnetic tunnel junctions, the third interconnects coupling the first magnetic tunnel junctions to the semiconductor substrate. In some embodiments of the device, the first magnetic tunnel junctions are disposed above the first spin-orbit torque line. In some embodiments, the device further includes: third interconnects above the first magnetic tunnel junctions, the third interconnects coupling the first magnetic tunnel junctions to the semiconductor substrate. In some embodiments, the device further includes: a second spin-orbit torque line over the semiconductor substrate; second magnetic tunnel junctions coupled to the second spin-orbit torque line; bit lines above the first magnetic tunnel junctions and the second magnetic tunnel junctions; and third interconnect between the first spin-orbit torque line and the second spin-orbit torque line, the third interconnect coupling the bit lines to the semiconductor substrate.
In an embodiment, a method includes: forming a first metallization layer of an interconnect structure over a semiconductor substrate, the first metallization layer including first interconnects; forming a second metallization layer of the interconnect structure over the first metallization layer, the second metallization layer including a spin-orbit torque line, magnetic tunnel junctions, and second interconnects, each of the magnetic tunnel junctions contacting a respective portion of the spin-orbit torque line; and forming a third metallization layer of the interconnect structure over the second metallization layer, the third metallization layer including bit lines, the first interconnects and the second interconnects interconnecting the bit lines, the magnetic tunnel junctions, the spin-orbit torque line, and devices of the semiconductor substrate to form a memory device. In some embodiments of the method, the magnetic tunnel junctions are formed below the spin-orbit torque line. In some embodiments of the method, the magnetic tunnel junctions are formed above the spin-orbit torque line.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Application No. 63/268,930, filed on Mar. 7, 2022, which application is hereby incorporated herein by reference.
Number | Date | Country | |
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63268930 | Mar 2022 | US |