The present application claims the benefit of the Singapore patent application No. 10201601973Q filed on 15 Mar. 2016, the entire contents of which are incorporated herein by reference for all purposes.
Embodiments relate generally to memory devices, and in particular, relate to a memory device and a method of forming a memory device.
In recent decades, emerging nonvolatile memories including ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase-change random access memory (PRAM), and resistive random access memory (ReRAM or RRAM) have been intensively studied. Among them, ReRAM which exhibits resistive change under external voltages, holds the advantages in its simple structure, easy fabrication, good scalability, potential high integration density, and good compatibility to the current CMOS technology.
In order to compete with current flash memory, fabrication in three-dimensional (3D) architecture of ReRAM is necessary. In the 3D architecture, current sneak path may lead to read error and high power dissipation during SET or RESET operation of the ReRAM. Besides development of ReRAM memory cells, the selector for selecting memory cells is the other critical element that may help to block the sneak current leakage path to reduce the power consumption as well as the operation error. The integration of selectors into 3D structure is thus critical in reducing power consumption and operation error.
In the existing 3D memory architecture with integration of selectors, sneak paths still exist. Accordingly, it is desired to provide high performance memory device structures to further lower the sneak current.
Various embodiments provide a memory device, including a plurality of insulating layers and a plurality of lateral layer arrangements. The lateral layer arrangements and the insulating layers are arranged alternately on each other such that each lateral layer arrangement is sandwiched between neighboring insulating layers. Each lateral layer arrangement includes a first electrode layer, a second electrode layer, and a memory layer sandwiched between the first electrode layer and the second electrode layer. The memory layer and the second electrode layer are arranged at a lateral side of the first electrode layer. The memory device further include a selecting film arranged at a lateral side of the insulating layers and the lateral layer arrangements and extending in a direction at least substantially perpendicular to a lateral direction of the lateral layer arrangements, wherein the selecting film has a first surface in contact with the second electrode layer of each lateral layer arrangement. The memory device further include a third electrode layer arranged in contact with a second surface of the selecting film, the second surface being opposite to the first surface.
Various embodiments provide a method of forming a memory device. The method may include forming a plurality of insulating layers; forming a plurality of lateral layer arrangements, wherein the lateral layer arrangements and the insulating layers are arranged alternately on each other such that each lateral layer arrangement is sandwiched between neighboring insulating layers. Each lateral layer arrangement may include a first electrode layer; a second electrode layer; and a memory layer sandwiched between the first electrode layer and the second electrode layer, wherein the memory layer and the second electrode layer are arranged at a lateral side of the first electrode layer. The method may further include forming a selecting film at a lateral side of the insulating layers and the lateral layer arrangements. The selecting film is extending in a direction at least substantially perpendicular to a lateral direction of the lateral layer arrangements, and the selecting film has a first surface in contact with the second electrode layer of each lateral layer arrangement. The method may further include forming a third electrode layer in contact with a second surface of the selecting film, the second surface being opposite to the first surface.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, in which:
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural and logical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
Various embodiments provide a 3D (three-dimensional) stacked memory architecture with self-aligned two-terminal selectors for a memory device, which reduces leakage current and leverages fabrication costs.
The memory device 10 includes a plurality of insulating layers 100 and a plurality of lateral layer arrangements 250. The lateral layer arrangements 250 and the insulating layers 100 are arranged alternately on each other such that each lateral layer arrangement 250 is sandwiched between neighboring insulating layers 100. Each lateral layer arrangement 250 includes a first electrode layer 200, a second electrode layer 220, and a memory layer 210 sandwiched between the first electrode layer 200 and the second electrode layer 220. The memory layer 210 and the second electrode layer 220 are arranged at a lateral side of the first electrode layer 200, e.g. at the left side of the first electrode layer 200 as shown in
The memory device 10 further includes a selecting film 310 arranged at a lateral side of the insulating layers 100 and the lateral layer arrangements 250, e.g. at the left side of the insulating layers 100 and the lateral layer arrangements 250 in an example shown in
According to various embodiments, the insulating layers 100 may include an insulating material, such as silicon dioxide, silicon nitride or other dielectrics.
According to various embodiments, the first electrode layer 200 of each lateral layer arrangement 250 may form a wordline of the memory device 10. The wordline 200 lays in a horizontal direction and is connected to a wordline transistor. The first electrode layer 200 may include various conductive materials, such as metals (e.g. Ta, Ti, W, Pt, Ir, Ru, Ag, Cu, TiN, TaN, etc.), conductive oxide (e.g. ITO, Fe3O4, etc.), or polysilicon.
According to various embodiments, the third electrode layer 300 may form a bitline of the memory device 10. The bitline runs in a vertical direction perpendicular to the wordline 200 as well as a wafer substrate supporting the memory device 10. The third electrode layer 300 may include various conductive materials, including different metals, polysilicon, or conductive oxide, etc.
In other embodiments, the first electrode layer 200 of each lateral layer arrangement 250 may form a bitline, and the third electrode layer 300 may form a wordline of the memory device 10.
According to various embodiments, the first electrode layer 200, the memory layer 210 and the second electrode layer 220 of each lateral layer arrangement 250 form a memory cell.
In various embodiments, the memory cell may include at least one of an ion-conducting based resistive random access memory (ReRAM), an anion-conducting based resistive random access memory, or a phase change random access memory (PCRAM).
The memory layer 210 represents the memory film which is the core film of the memory cell. In various embodiments, examples of the material included in the memory layer 210 may include but are not limited to silicon oxide, aluminum oxide, germanium oxide, or transition metal oxide (e.g. HfOx, TaOx, CuOx, FeOx, WOx, ZrOx, TiOx, etc.), so as to form an anion-conducting based ReRAM cell. In various embodiments, the memory film 210 may include semiconductor materials (e.g. GeSe, GeS, CuTe, Si, Ge, etc.), so as to form an ion-conducting based ReRAM cell. In various embodiments, the memory film 210 may include chalcogenide materials (e.g. GST, AIST, etc.) or metal oxides (e.g. NiOx, CoOx, etc.), so as to form a PCRAM cell. The chalcogenide material refers to a material including chalcogen elements, wherein examples of chalcogen elements include oxygen (O), sulfur (S), selenium (Se), and tellurium (Te).
According to various embodiments, the third electrode layer 300, the selecting film 310 and the second electrode layer 220 of each lateral layer arrangement 250 form a selector for selecting a memory cell.
The selecting film 310 is the core film of the selector. In various embodiments, the selector may include at least one of an Ovonic Threshold Switch (OTS) selector or a Mott effect switch based selector. In various embodiments, the selecting film 310 may include chalcogenide materials (e.g. GST, SeTe, AsTeGeSiN, CuGexSey, doped-chalcogenide, etc.) so as to form an OTS selector. In various embodiments, the selecting film 310 may include Mott materials (e.g. NbOx, VOx, MoOx, etc.), so as to form a Mott effect switch based selector.
The second electrode layer 220 may include metals (Ta, Ti, W, Cu, Ag, Pt, Ir, TiN, TaN, etc.), or conductive oxide (ITO, Fe3O4, etc.).
According to various embodiments, the second electrode layer 220 is used as the electrodes of both the memory cell and the selector device, and may be referred to as an intermediate electrode layer. The second electrode layer 220 isolates the two critical films, i.e. the memory film 210 and the selecting film 310, to avoid the interaction of the materials in these two films. Because of the multiple role-play in the architecture, the second electrode layer 220 may include various or several materials, to satisfy different requirements from the memory cell, the selector, and the material isolation. In an exemplary embodiment, the second electrode layer 220 may include a Pt film and a Cu film. The Pt film may act as the electrode of the selector as well as the blocking film for Cu or other materials. The Cu film may act as the active electrode providing the copper ion in the ion-conducting based ReRAM cells. In another exemplary embodiment, the second electrode layer 220 may include TiN only. The TiN layer may act as the electrodes for both the anion-conducting based ReRAM, and OTS or Mott effect based selectors. Further, TiN may also act as a good blocking film to avoid materials intermixing.
According to various embodiments, the selecting film 310 may further include a plurality of lateral protruding portions 312. Each lateral protruding portion 312 is located within the respective lateral layer arrangement 250 and in contact with the second electrode layer 220 of the respective lateral layer arrangement 250, such that the lateral protruding portion 312 of the selecting film 310 is sandwiched between neighboring insulating layers 100 of the respective lateral layer arrangement 250. The lateral protruding portions 312 of the selecting film 310 may be used to clearly break the conducting path between electrodes 220 in different lateral layer arrangements 250. Although
According to various embodiments, the memory device 10 may further include a further memory layer (not shown in
The memory device 10 may further include a further selecting film (not shown in
In other words, a plurality of selectors are formed at the right side of the first electrode layers 200 similar to the selectors formed at the left side of the first electrode layers 200 described above, so that a symmetric structure is formed. An exemplary embodiment of such a symmetric structure is illustrated as a memory stack 1310 or a memory stack 1320 shown in
According to the embodiments as shown in
At 31, a plurality of insulating layers is formed.
At 33, a plurality of lateral layer arrangements is formed, wherein the lateral layer arrangements and the insulating layers are arranged alternately on each other such that each lateral layer arrangement is sandwiched between neighboring insulating layers. Each lateral layer arrangement may include a first electrode layer; a second electrode layer; and a memory layer sandwiched between the first electrode layer and the second electrode layer, wherein the memory layer and the second electrode layer are arranged at a lateral side of the first electrode layer.
At 35, a selecting film is formed at a lateral side of the insulating layers and the lateral layer arrangements. The selecting film is extending in a direction at least substantially perpendicular to a lateral direction of the lateral layer arrangements, and the selecting film has a first surface in contact with the second electrode layer of each lateral layer arrangement.
At 37, a third electrode layer is formed in contact with a second surface of the selecting film, the second surface being opposite to the first surface.
It is understand that the processes or steps 31, 33, 35, 37 may not be carried out in sequence.
According to various embodiments, forming the plurality of lateral layer arrangements at 33 may further include forming the first electrode layers alternately on the insulating layers, such that each first electrode layer is sandwiched between neighboring insulating layers. A portion of each first electrode layer may be selectively etched to form a respective lateral recess. A respective memory layer is formed in the respective lateral recess; and a respective second electrode layer is formed next to the memory layer in the respective lateral recess.
According to various embodiments, forming the second electrode layer next to the memory layer in the respective lateral recess at 33 may further include forming a conductive layer conformally next to the memory layer and the insulating layers; and etching the conductive layer to expose the insulating layers and remove the conductive layer outside the respective lateral recess, thereby forming the second electrode layer next to the memory layer within the respective lateral recess.
According to various embodiments, the portion of each first electrode layer may be selectively etched at 33 from the lateral side (e.g. the left side) and a further lateral side (e.g. the right side) of each first electrode layer to form the respective lateral recess at the lateral side and a respective lateral recess at the further lateral side, wherein the first lateral side is opposite to the second lateral side, for example, as shown in
According to various embodiments, the method 30 may further include forming a further memory layer and a fourth electrode layer at a further lateral side opposite to the lateral side of the first electrode layer in each lateral layer arrangement, wherein the further memory layer is sandwiched between the first electrode layer and the fourth electrode layer. The method 30 may further include forming a further selecting film at a further lateral side opposite to the lateral side of the insulating layers and the lateral layer arrangements. The further selecting film is extending in the direction at least substantially perpendicular to the lateral direction of the lateral layer arrangements, and the further selecting film has a first surface in contact with the fourth electrode layer of each lateral layer arrangement. The method 30 may further include forming a fifth electrode layer arranged in contact with a second surface of the further selecting film opposite to the first surface of the further selecting film.
According to various embodiments, the plurality of insulating layers and the plurality of first electrode layers may be etched at 33 to form a trench extending through the insulating layers and the first electrode layers, such that two stacks of layers separated by the trench are formed, as will be described in
According to various embodiments, after forming the respective second electrode layer next to the memory layer in the respective lateral recess at 33, a portion of the respective second electrode may be etched to form a respective etch back portion, for example, the etch back portion 314 as shown in
According to various embodiments, in forming the lateral layer arrangement at 33, the memory layer may be formed in the respective lateral recess by conformal deposition, such that a lateral groove is formed in each memory layer. The second electrode layer may be formed at 33 next to the memory layer in the respective lateral recess, including forming a lateral protrusion of the second electrode layer fitting into the lateral groove, e.g., the lateral protrusion 222 of the second electrode layer as shown in
According to various embodiments, each first electrode layer forms a wordline of the memory device. The third electrode layer forms a bitline of the memory device.
According to various embodiments, the respective first electrode layer, the respective memory layer and the respective second electrode layer form a respective memory cell. In various embodiments, the memory cell may include at least one of an ion-conducting based resistive random access memory, an anion-conducting based resistive random access memory, or a phase change memory.
According to various embodiments, the third electrode layer, the selecting film and the respective second electrode layer form a respective selector for selecting the respective memory cell.
According to various embodiments, the selecting film may include one of chalcogenide material or Mott material.
According to various embodiments above, a 3D memory architecture of the memory device is provided, including a multi-film stack including conductive layers and insulating layers alternatively arranged on each other. At the edge or lateral side of the stacking films, vertical memory cells (such as ReRAM or PCRAM cells) and vertical selectors are fabricated. The selectors are self-aligned to each memory cell to block the sneak current. Inbetween the memory film and selecting film, electrode materials are inserted to isolate these films.
According to various embodiments above, the neighboring insulating layers form a tunnel therebetween, inside which the memory layer 210 and the second electrode 220 of the selector is formed. This provides a 3D integration architecture that integrates memory cells and selectors together, and realizes 1S1R (one selector one resistor) scheme to eliminate the sneak paths.
The method or process of forming the memory device according to various embodiments are described in more detail below in
In this exemplary embodiment, the insulating layer 100 may include silicon nitride, and the conductive layer 200 may include a tantalum thin film. In an embodiment, an extra mask layer may be optionally deposited on top of the stack layers (not shown in
In other embodiments, other assistant method might be used to assist the wet etching. In an exemplary embodiment, the conductive layers 200 may be tantalum films, and may be oxidized first by thermal anneal under oxygen ambient. Then a selective wet etching may include dilute hydrogen fluorine (DHF) to selectively etch the oxidized tantalum away, while leaving the tantalum metal thin film 200 and the silicon nitride film 100 less etched. This method may provide better control of etch-back uniformity and is also manufacture friendly.
In various embodiments, the non-selective deposition may be carried out via an atomic layer deposition (ALD) method. The memory layer 210 may be formed by conformal deposition, e.g. via ALD, such that the memory layers are confined inside the stack tunnel. After ALD deposition, an etch-back of ALD film may be required under the self-aligned dry etching. The cross-sectional view of the memory stack using ALD deposition and etch-back to form the memory layer 210 is shown in the embodiments of
In an exemplary embodiment, the deposition of the intermediate electrode layer 220 may be achieved by the ALD deposition method in order to achieve the conformal conductive film inside the etch-back tunnel, i.e. the lateral recess 202. In one illustrative example, the conductive film of titanium nitride (TiN) 220 may be deposited using ALD method. The ALD growth of titanium nitride is mature in current semiconductor industry. Titanium tetrachloride (TiC14), tetrakis (dimethylamino) titanium (TDMAT) or other titanium precursor may be used together with N2 or NH3 to deposit TiN in a plasma enhance atomic layer deposition (PEALD) system. In another illustrative example, a conductive film of platinum 220 may be deposited using ALD or PEALD method as well.
In another exemplary embodiment, electroplating process may be used to deposit the metal conductive film 220, which may include copper, silver, platinum and other suitable materials. The electroplating process can also provide good step coverage filling in deep trenches or tunnels.
According to an exemplary embodiment as shown in
In various embodiments a slightly etch-back inside the tunnel or the lateral recess 202 may be carried out to form the respective etch back portion 314, in order to clearly break the conducting path between electrodes in different layers. The selecting film may be subsequently formed to fill in the respective etch back portion 314 as illustrated in
The selecting film 310 may be first deposited by either CVD or PVD method. The selecting film 310 is an insulating film without external stresses, and becomes conductive under an external voltage or thermal heat. The selecting film 310 may include chalcogenide materials (e.g. GST, SeTe, AsTeGeSiN, CuGexSey, doped-chalcogenide, etc.), or Mott materials (e.g. NbOx, VOx, MoOx, etc.). The selecting film 310 may be formed next to the second electrode layers 220 and the insulating layers 100 at either one or both lateral sides of the second electrode layers 220 and the insulating layers 100. The selecting film 310 may also be formed to cover the stack of layers as shown in
After the deposition of the selecting film 310, the outer electrode layer 300, i.e.
the third electrode layer 300, may be deposited next to the selecting film 310 at the lateral side of the selecting film 310, and may be deposited further on top of the selecting film 310 and between the stacks as shown in
After the isolating etching, the memory cell and selectors may be isolated from the neighboring memory cells or selectors in a horizontal direction, and leave the conductive line 200 unbroken. During the etching, different materials including the memory layer 210, the intermediate electrode layer 220, the selecting film 310, the outer electrode layer 300, and part of the insulating film 100 and the conductive film 200 may be etched way at the same time. Thus, a non-selective dry etching may be used which may include a mixture of Argon bombardment etches (Ar) and chemical dry etches for both oxides and metals (CF4/C12).
Accordingly, through the process of
The memory device 10, 20 formed according to the method 30 and the process of
As shown in
In
In
In
In
In
In
In
As shown in
I
leak=((M−1)+(N−1)+(H−1))*I(selector off current)
M represents the number of wordlines, N represents the number of bitlines, and H represents the number of layers. I(selector off current) represents the current when the selector is off.
Table 1 shows the voltage setting when reading the memory cell M1. An equivalent circuit 1550 when reading the memory cell M1 is shown in
The selector may be a selector device described in WO2016/122406A1, wherein the selecting film of the selector device includes at least one metal rich layer and at least one chalcogenide rich layer. This selecting film may be used as the selecting film 310 of the memory device 10, 20 above.
The metal rich layer may include at least one of a metal or a metal compound. The metal rich layer refers to a layer including metal elements, in which the metal content is greater than 50 at. % (atomic percentage) so that the metal elements are the majority elements in the metal rich layer.
The chalcogenide rich layer refers to a layer of chalcogenide, or a layer of mixture including chalcogenide, in which the chalcogenide content is greater than 50 at. % so that the chalcogenides are the majority compounds in the chalcogenide rich layer. In various embodiments, the chalcogenide rich layer may include a mixture of chalcogenide and other dielectric or metal materials, in which the chalcogenide content is greater than 50 at. %, higher than the other dielectric or metal content. Examples of dielectric or metal material that may be included in the chalcogenide rich layer may include but are not limited to Al2O3, SiO2, Si3N4, Ag, Cu, and Zn. A chalcogenide includes chalcogen elements, wherein examples of chalcogen elements include oxygen (O), sulfur (S), selenium (Se), and tellurium (Te). The metal rich layer and the chalcogenide rich layer may have different materials, different element composition, or different atomic percentages of various element components. In other words, the material composition or the element composition of the metal rich layer is different from that of the chalcogenide rich layer 314.
In
The leakage current percentage is calculated according to the following equation:
As shown in the results of
By using the memory device structure (e.g. as in
While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
Number | Date | Country | Kind |
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10201601973Q | Mar 2016 | SG | national |
Filing Document | Filing Date | Country | Kind |
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PCT/SG2017/050125 | 3/14/2017 | WO | 00 |