Modern semiconductor non-volatile memories, such as flash memory, have successfully achieved large capacity memories through improvements in photolithograph technology. However, conventional Flash memory scaling is nearing the technical and physical limits. To avoid this problem, alternate materials and/or structures have been proposed.
Recently, resistance random access memory (ReRAM or RRAM) has been extensively investigated not only because of its electrical performance but also because of its high scalable capability for memory array applications. ReRAM is based on materials such as metal oxides and organic compounds that show a resistive switching phenomenon. A ReRAM memory cell has a capacitor-like structure composed of insulating material or semiconducting material between two metal electrodes. Because of its simple structure and ease of manufacture, ReRAM devices are gaining acceptance for future memory.
The present disclosure relates to memory elements and methods of making the memory elements.
In one particular embodiment, this disclosure provides a method for making a memory element that includes forming a first electrode, forming an electrically conductive current densifying element and a memory cell on the first electrode, with the memory cell and the current densifying element adjacent to each other. A second electrode is formed over the current densifying element and the memory cell.
In another particular embodiment, this disclosure provides a memory element that has a first electrode having a first area, a current densifying element having a second area less than the first area, a memory cell, and a second electrode having a third area greater than the second area. Each of the first electrode, the current densifying element, the memory cell and the second electrode in electrical connection. The memory cell may be a resistance random access memory cell.
These and various other features and advantages will be apparent from a reading of the following detailed description.
The disclosure may be more completely understood in consideration of the following detailed description of various embodiments of the disclosure in connection with the accompanying drawings, in which:
The figures are not necessarily to scale. Like numbers used in the figures refer to like components. However, it will be understood that the use of a number to refer to a component in a given figure is not intended to limit the component in another figure labeled with the same number.
This disclosure is directed to memory elements and methods of making those elements. The memory elements include an electrically conductive current densifying element, which may be formed before or after forming the memory cell.
In the following description, reference is made to the accompanying set of drawings that form a part hereof and in which are shown by way of illustration several specific embodiments. It is to be understood that other embodiments are contemplated and may be made without departing from the scope or spirit of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense. Any definitions provided herein are to facilitate understanding of certain terms used frequently herein and are not meant to limit the scope of the present disclosure.
Unless otherwise indicated, all numbers expressing feature sizes, amounts, and physical properties used in the specification and claims are to be understood as being modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the foregoing specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by those skilled in the art utilizing the teachings disclosed herein.
As used in this specification and the appended claims, the singular forms “a”, “an”, and “the” encompass embodiments having plural referents, unless the content clearly dictates otherwise. As used in this specification and the appended claims, the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.
The present disclosure is directed to methods of making random access memory cells, such as resistance random access memory cells (ReRAM or RRAM). The methods and resulting memory cells provide improved electrical performance of ReRAM devices by minimizing process induced defects, such as chemical and mechanical damage during device fabrication. In addition to defect free fabrication, the methods can also reduce the cost of fabrication by reducing the number of masking steps.
Ferromagnetic layers 12, 14 may be made of any useful ferromagnetic (FM) material such as, for example, Fe, Co or Ni and alloys thereof, such as NiFe and CoFe, and ternary alloys, such as CoFeB. Either or both of free layer 12 and pinned reference layer 14 may be either a single layer or a synthetic antiferromagnetic (SAF) coupled structure, i.e., two ferromagnetic sublayers separated by a metallic spacer, such as Ru or Cr, with the magnetization orientations of the sublayers in opposite directions to provide a net magnetization. Free layer 12 may be a synthetic ferromagnetic coupled structure, i.e., two ferromagnetic sublayers separated by a metallic spacer, such as Ru or Ta, with the magnetization orientations of the sublayers in parallel directions. Either or both layers 12, 14 are often about 0.1-10 nm thick, depending on the material and the desired resistance and switchability of free layer 12.
If magnetic element 10 is a magnetic tunnel junction cell, non-magnetic spacer layer 13 is an insulating barrier layer sufficiently thin to allow tunneling of charge carriers between pinned reference layer 14 and free layer 12. Examples of suitable electrically insulating material include oxides material (e.g., Al2O3, TiOx or MgOx). If magnetic element 10 is a spin-valve cell, non-magnetic spacer layer 13 is a conductive non-magnetic spacer layer. For either a magnetic tunnel junction cell or a spin-valve, non-magnetic spacer layer 13 could optionally be patterned with free layer 12 or with pinned reference layer 14, depending on process feasibility and device reliability.
The resistance across magnetic element 10 is determined by the relative orientation of the magnetization vectors or magnetization orientations of ferromagnetic layers 12, 14. The magnetization direction of ferromagnetic pinned reference layer 14 is pinned in a predetermined direction by pinning layer 15 while the magnetization direction of ferromagnetic free layer 12 is free to rotate under the influence of spin torque. In
Switching the resistance state and hence the data state of magnetic element 10 via spin-transfer occurs when a current, under the influence of a magnetic layer of magnetic element 10, becomes spin polarized and imparts a spin torque on free layer 12 of magnetic element 10. When a sufficient level of polarized current and therefore spin torque is applied to free layer 12, the magnetization orientation of free layer 12 can be changed among different directions and accordingly, magnetic element 10 can be switched between the parallel state, the anti-parallel state, and other states.
Electrically connected to cell 11 are a first or top electrode 16 and a second or bottom electrode 17. It is to be understood that the designations “top” and “bottom” are not to be limiting in their special relationship, but are merely used to facilitate understanding of the figures. In the following discussion, the term “top” is interchangeable with “first” and “bottom” is interchangeable with “second”. First electrode 16 is in electrical contact with ferromagnetic free layer 12 and second electrode 17 is in electrical contact with ferromagnetic pinned reference layer 14 via pinning layer 15. In this embodiment, second electrode 17 has a larger area (e.g., width and/or length) than cell 11. Electrodes 16, 17 electrically connect ferromagnetic layers 12, 14 to a control circuit providing read and write currents through layers 12, 14. Examples of materials for electrodes 16, 17 are conducting metal materials; suitable materials include TiN, TaN and Cu.
The illustrative magnetic element 10 is used to construct a memory device where a data bit is stored in the spin torque memory cell by changing the relative magnetization state of free layer 12 with respect to pinned reference layer 14. The stored data bit can be read out by measuring the resistance of element 10 which changes with the magnetization direction of free layer 12 relative to pinned reference layer 14.
Memory element 20 includes a memory cell 21 with a first metal electrode 26, a second metal electrode 27, and an ion conductor solid electrolyte material 25 therebetween.
In
Reading memory element 20 simply requires a small voltage applied across the cell. If conducting filaments 28 are present in that cell, the resistance will be low and the element will be in the low data state. If there are no conducting filaments 28 present, the resistance is higher, which can be read as the opposite state, as illustrated in
Application of an electric current of opposite polarity (−) to memory element 20 ionizes conducting filaments 28 and moves the ions back to first electrode 26 and gives rise to the high resistance state of memory element 20. The low resistance state and the high resistance state are switchable with an applied electric field and are used to store the memory bit “1” or “0”.
Ion conductor solid electrolyte material 25 can be formed of any useful material that provides for the formation of conducting filaments 28 or superionic clusters within ion conductor solid electrolyte material 25 that extend between metal electrode 26 and metal electrode 27 upon application of an electric current. In some embodiments, ion conductor solid electrolyte material 25 is a chalcogenide-type material such as, for example, GeS2, GeSe2, CuS2, and the like. In other embodiments, ion conductor solid electrolyte material 25 is an oxide-type material such as, for example, NiO, WO3, SiO2, and the like.
First metal electrode 26 and second metal electrode 27 can be formed of any electrically conductive material such as metallic material. In many embodiments, one or both of first metal electrode 26 and second metal electrode 27 are formed of electrically conductive yet electrochemically inert metals such as, for example, Pt, Au, and the like. In some embodiments, first metal electrode 26 and/or second metal electrode 27 have two or more metal layers, where the metal layer closest to ion conductor solid electrolyte material 25 is electrochemically inert while additional layers can be electrochemically active.
Memory element 20 is a programmable metallization cell (PMC), a resistive memory element where the data state of the element depends on the resistance across the element. For element 20, the resistance across cell 21 decreases with the presence of conducting filaments 28. Other resistive memory elements that can be made by the methods of this disclosure include those that function based on carrier movement on the interface (e.g., phase change memory cells (PCM or PCRAM) and those that function based on ion transport in solid electrolyte (e.g., perovskite metal oxide cells (e.g. perovskite manganites, Pr1-xCaxMnO3, or perovskite titanates) (PCMO)).
The above-described memory elements and other memory elements of this disclosure may be made by various methods. Some of the methods of this disclosure include forming a first electrode, forming an electrically conductive current densifying element and a memory cell in electrical contact with the first electrode, and patterning a second electrode over the current densifying element and the memory cell. The current densifying element may be formed before or after forming the memory cell. Other methods of this disclosure include forming a first electrode, providing a hole in an electrically insulating layer, the hole extending to the first electrode; forming an electrically conductive current densifying element in the hole and forming a memory cell in the hole, with the memory cell and the current densifying element adjacent to each other. After filling the hole with the current densifying element and the memory cell, patterning a second electrode over the filled hole. The electrically conductive current densifying element may be formed in the hole before or after forming the memory cell in the hole.
In the “bottom electrode last” method, the bottom electrode is fabricated on the substrate (e.g., silicon wafer) followed by deposition of the memory cell and the top electrode. Patterning and etching of the top electrode and the memory stack are done to form the eventual final top electrode and the memory stack; during this step, the bottom electrode functions as a hard mask, inhibiting of etching past the memory cell. Subsequently, patterning and etching are done to form the eventual bottom electrode. This integration is called “bottom electrode last” because the bottom element is defined at very last step of patterning, after formation of the final memory cell and the top electrode.
Referring to
Substrate 40 may be, for example, a dielectric or an oxide material such as SiO2, Al2O3, FSG (fluorinated silicate glass, a silica based low-k dielectric), CDO (carbon doped oxide), doped SiO2, SiN, or MgOx. In some embodiments, substrate 40 may be multiple layers, such as multiple metallization layers fabricated on an “n” silicon doped substrate. Electrode materials 46, 47 are electrically conductive materials and are usually a metal material. Examples of suitable materials for electrode materials 46, 47 include TiN, TaN, Cu, and W. Electrode materials 46, 47 may have the same or different materials, and may have the same or different thicknesses. In some embodiments, bottom electrode material 47 has a thickness of about 1000 Å and top electrode material 46 has a thickness of about 2000 Å. For embodiments where the eventual memory cell is a magnetic tunnel junction element, such as element 10 of
In
In
Suitable materials for ILD layer 45 include dielectric or oxide materials such as SiO2, Al2O3, FSG, CDO, doped SiO2, and SiN. ILD layer 45 may be the same material or different than substrate 40.
In the “bottom electrode first” method, the bottom electrode is fabricated and patterned on the substrate followed by deposition of the memory cell and the top electrode. This integration is called “bottom electrode first” because the bottom element is defined prior to formation of the final memory cell and the top electrode. “Bottom electrode first” methods have been used to obtain high magnetic and electrical performance by minimizing substrate stress effect on the adjacent memory cell. The various materials and their properties (e.g., layer thicknesses) for a “bottom electrode first” process are generally the same as or similar to those of a “bottom electrode last” process, unless indicated otherwise.
Referring to
Memory cell 51 and a top electrode 56 are formed (e.g., deposited) in
In
The two methods described above, “bottom electrode last” and “bottom electrode first” are particularly suitable integration techniques for spin-toque memory device fabrication (e.g., ST RAM devices) due to their simplicity and compatibility with current CMOS technology. Memory element 10 of
In each of these methods, a current densifying element is formed between the bottom contact or electrode and the memory cell. This element resembles a plug, with a size or diameter of at least 50 nm, in some embodiments at least 75 nm and in other embodiments at least 100 nm. In some embodiments, the current densifying element has a size no greater than about 200 nm, sometimes no greater than about 150 nm. The physical shape and size (e.g., diameter, area, etc.) of the current densifying element is less than the adjacent bottom electrode or top electrode. Due to its physical shape, the current densifying element increases the density of the current passing between the electrodes and enhances any electric field around the memory cell.
Referring to
In
In
Memory cell 61 and a top electrode 66 are formed (e.g., deposited) in
In use, electrical current passes through the element, having a path from bottom electrode 67, through optional barrier layer 64, through plug 62, through memory cell 61, to electrode 66 and optional metal layer 68. In some embodiments, current may pass the other direction, from top electrode 66 through memory cell 61 to bottom electrode 67. Plug 62, having a smaller area (e.g., at least 50 nm, in some embodiments at least 75 nm and in other embodiments at least 100 nm, with a size no greater than about 200 nm, sometimes no greater than about 150 nm) than bottom electrode 67 and/or top electrode 66 (which are often about 200 nm to about 250 nm), concentrates the current from electrode 66 or electrode 67, increasing the current density into memory cell 61.
The resulting memory element made by the method of
Referring to
In
In
A top electrode 76 is formed (e.g., deposited) in
In use, electrical current passes through the element, having a path from bottom electrode 77, through memory cell 71, through optional barrier layer 74, through plug 72, to electrode 76 and optional metal layer 78. In some embodiments, current may pass the other direction, from top electrode 76 through memory cell 71 to bottom electrode 77. Plug 72, having a smaller area (e.g., at least 50 nm, in some embodiments at least 75 nm and in other embodiments at least 100 nm, with a size no greater than about 200 nm, sometimes no greater than about 150 nm) than bottom electrode 77 and/or top electrode 76 (which are often about 200 nm to about 250 nm), concentrates the current from electrode 76 or electrode 77, increasing the current density into memory cell 71.
The resulting memory element made by the method of
In some embodiments, the process of
Various methods for making memory elements have been described above. In some methods, a current densifying element is formed between a contact or electrode and the memory cell. Due to its physical shape, the current densifying element increases the density of the current passing between the electrodes and enhances any electric field around the memory cell. Such a current densifying element is particularly useful for restrictive random access memory (ReRAM or RRAM) elements.
Thus, embodiments of the MEMORY DEVICE DESIGN are disclosed. The implementations described above and other implementations are within the scope of the following claims. One skilled in the art will appreciate that the present disclosure can be practiced with embodiments other than those disclosed. The disclosed embodiments are presented for purposes of illustration and not limitation, and the present invention is limited only by the claims that follow.
This application claims priority to U.S. provisional patent application No. 61/111,353, filed on Nov. 5, 2008 and titled “New Integration Approach for ReRAM Device Fabrication”. The entire disclosure of application No. 61/111,353 is incorporated herein by reference.
Number | Date | Country | |
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61111353 | Nov 2008 | US |