Patent Grant
12112802
The present application claims the benefit of priority to China Application No. 202210864398.8, filed on Jul. 21, 2022, the content of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of semiconductor technology, and in particular, to a memory device, an operation method thereof, and a memory system.
Memory is a memory device used to save information in modern information technology. As a typical non-volatile semiconductor memory device, NAND (Not-And) flash memory device has become a mainstream product in the market due to its high storage density, controllable production cost, suitable programming and erasing speed, and retention characteristics.
With the increasing requirements of memory devices, how to reduce the area of the memory device has become one of the technical problems that need to be solved urgently.
According to the first aspect of the embodiments of the present disclosure, there is provided a memory device comprising a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits; during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits; and during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits respectively to perform voltage selection.
In the above solution, during the program operation, the number of the selected voltages corresponding to the plurality of memory planes is a, and the number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least and during the read operation, the number of the selected voltages corresponding to each memory plane is b, and the number of the selected voltage selection circuits corresponding to each memory plane is at least b; the number of the memory planes is c, and the relationship among a, b, and c is: a≥b*c; wherein, both the a and the b are positive integers greater than 0, and the c is a positive integer greater than 1.
In the above solution, the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one; during the program operation, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; during the read operation, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits.
In the above solution, the peripheral circuit further comprises a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to the plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit; each of the plurality of unselected voltage selection circuits is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits; during the program operation, the plurality of memory planes share the plurality of unselected voltage selection circuits; during the read operation, each memory plane uses a part of the plurality of unselected voltage selection circuits respectively to perform voltage selection.
In the above solution, during the program operation, the number of the unselected voltages corresponding to the plurality of memory planes is d, and the number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least d; during the read operation, the number of the unselected voltages corresponding to each memory plane is e, and the number of the unselected voltage selection circuits corresponding to each memory plane is at least e; the number of the memory planes is c, and the relationship among c, d and e is: d≥e*c; wherein, both the d and the e are positive integers greater than 0, and the c is a positive integer greater than 1.
In the above solution, each of the memory planes comprises a plurality of word lines; the peripheral circuit further includes a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one, and a plurality of local word lines corresponding to the local word line voltage selection circuits one-to-one; wherein, each of the global word lines corresponds to the plurality of local word lines; each local word line corresponds to one global word line, and each local word line corresponds to one word line; the global word line voltage selection circuits output the voltage to the local word line voltage selection circuits through the global word lines; the local word line voltage selection circuits output the voltage to corresponding word lines through the local word lines.
In the above solution, the selected voltage selection circuits, the global word line voltage selection circuits, the local word line voltage selection circuits and the unselected voltage selection circuits all comprise a multiplexer.
According to the second aspect of the embodiments of the present disclosure, there is provided a memory system, and the memory system comprises: one or more memory devices according to any of the above schemes; and a memory controller coupled to and controlling, the memory device.
In the above solution, the memory system comprises a memory card or a solid-state hard disk.
According to the third aspect of the embodiments of the present disclosure, there is provided a method for operating a memory device which comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits; the method includes: receiving a first instruction, the first instruction is configured to simultaneously perform a program operation on the plurality of memory planes; applying a plurality of different voltages output by the plurality of selected voltage selection circuits to each memory plane in response to the first instruction; receiving a second instruction, the second instruction is configured to perform a read operation on the plurality of memory planes; applying a part of the plurality of different voltages output by the plurality of selected voltage selection circuits respectively to different memory planes in response to the second instruction.
In the above solution, during the program operation performed on the plurality of memory planes simultaneously, the number of the selected voltages corresponding to the plurality of memory planes is a, and the number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a; and during the read operation performed on the plurality of memory planes, the number of the selected voltages corresponding to each memory plane is b, and the number of the selected voltage selection circuits corresponding to each memory plane is at least b; the number of the memory planes is c, and the relationship among a, b and c is: a≥b*c; wherein, both the a and the b are positive integers greater than 0, and the c is a positive integer greater than 1.
In the above solution, the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one; during the program operation performed on the plurality of memory planes simultaneously, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; during the read operation performed on the plurality of memory planes, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits.
In the above solution, the peripheral circuit further comprises a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to the plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit; each of the plurality of unselected voltage selection circuits is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits; the method further includes: applying a plurality of different unselected voltages output by the plurality of unselected voltage selection circuits to each memory plane in response to the first instruction, applying a part of the plurality of different voltages output by the plurality of unselected voltage selection circuits respectively to different memory planes in response to the second instruction.
In the above solution, during the program operation, the number of the unselected voltages corresponding to the plurality of memory planes is d, and the number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least d; during the read operation, the number of the unselected voltages corresponding to each memory plane is e, and the number of the unselected voltage selection circuits corresponding to each memory plane is at least e; the number of the memory planes is c, and the relationship among c, d and e is: d≥e*c; wherein, both the d and the e are positive integers greater than 0, and the c is a positive integer greater than 1.
In the above solution, each of the memory planes comprises a plurality of word lines; the peripheral circuit further includes a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one, and a plurality of local word lines corresponding to the local word line voltage selection circuits one-to-one; wherein, each of the global word lines corresponds to the plurality of local word lines; each local word line corresponds to one global word line, and each local word line corresponds to one word line; the global word line voltage selection circuits output the voltage to the local word line voltage selection circuits through the global word lines; the local word line voltage selection circuits output the voltage to corresponding word lines through the local word lines.
In the above solution, an Asynchronous Multi-plane Independent (AMPI) read method is used to perform the read operation on the plurality of memory planes during the read operation performed on the plurality of memory planes.
Embodiments of the present disclosure provide a memory device, an operation method thereof, and a memory system. The memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits; during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits; and during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits to perform voltage selection. In the embodiment of the present disclosure, during the program operation, the plurality of memory planes share the plurality of selected voltage selection circuits, while during the read operation, each memory plane uses a part of the plurality of selected voltage selection circuits used during the program operation to perform voltage selection. That is, in the embodiment of the present disclosure, the program operation and the read operation share the selected voltage selection circuits, so that the selected voltage selection circuits required during the read operation need not to be additionally added. Thus, the total number of the selected voltage selection circuits is small, and the area of the memory device may be reduced, which is beneficial to the miniaturization of the memory device.
Exemplary implementations disclosed in the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited by the detailed description set forth herein. Rather, these implementations are provided so that the present disclosure will be better understood, and will better convey the scope disclosed in the present disclosure to those skilled in the art.
In the following description, many specific details are set forth in order to provide a better understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the present disclosure may be implemented without one or more of these details. In other instances, some technical features that are well known in the art have not been described in order to avoid obscuring the present disclosure: that is, not all features of actual embodiments are described herein, and well-known functions and constructions are not described in detail.
In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.
It will be understood that when an element or a layer is referred to as being “on”, “adjacent to”, “connected to” or “coupled to” other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or intervening elements or layers may be present therebetween, in contrast, when an element is referred to as being “directly on”, “directly adjacent to”, “directly connected to” or “directly coupled to” other elements or layers, there are no intervening elements or layers present therebetween. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another. Thus, the first element, component, region, layer, or section discussed below could be referred as the second element, component, region, layer, or section without departing from the teachings of the present disclosure. The discussion of the second element, component, region, layer, or section does not imply that the first element, component, region, layer, or section is necessarily present in the present disclosure.
Spatial relational terms such as “under”, “below”, “lower”, “beneath”, “above”, “upper”, etc., are used herein for convenience description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is flipped over, the elements or features described as “below” or “beneath” or “under” other elements or features would then be oriented “on” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both orientations of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terms used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a”, “an”, and “said/the” are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms “compose” and/or “include”, when used in this specification, identify the presence of stated features, integers, steps, operations, elements, and/or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups. As used herein, the term “and/or” includes any and all combinations of the associated listed items.
In order to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below in combination with the accompanying drawings, which are for reference only and are not intended to limit the embodiments of the present disclosure.
The memory device in the embodiments of the present disclosure includes, but is not limited to, a three-dimensional NAND memory device. For ease of understanding, a three-dimensional NAND memory device is used as an example for description.
The three-dimensional NAND memory stacks memory cells in the direction perpendicular to the substrate, which can form more memory cells in a smaller area. Compared with the two-dimensional memory device, the three-dimensional NAND memory device has a larger memory capacity and is a main development direction in the current memory field. With the increasing requirements of the three-dimensional NAND memory device, how to reduce the area of the memory device has attracted widespread attention.
In order to solve one or more of the above-mentioned problems, a solution is introduced by the embodiments of the present disclosure that can reduce the area of peripheral circuits, thereby reducing the area of a memory device.
According to some implementations, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. Memory controller 106 can manage the data stored in memory device 104 and communicate with host 108. In some implementations, memory controller 106 is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller 106 is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays.
Memory controller 106 can be configured to control operations of memory device 104, such as read, erase, and program operations. Memory controller 106 can also be configured to manage various functions with respect to the data stored or to be stored in memory device 104 including, but not limited to, bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correction codes (ECCs) with respect to the data read from or written to memory device 104. Any other suitable functions may be performed by memory controller 106 as well, for example, formatting memory device 104. Memory controller 106 can communicate with an external device (e.g., host 108) according to a particular communication protocol. For example, memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.
Memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UES) package or an eMMC package. That is, memory system 102 can be implemented and packaged into different types of end electronic products. In an example as shown in
It should be noted that the number of rows of memory cell rows between the gate isolation structure and the upper select gate isolation structure shown in
In some implementations, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and thus, can store one bit of data. For example, the first memory state “0” can correspond to a first range of voltages, and the second memory state “1” can correspond to a second range of voltages. In some implementations, each memory cell 306 is a multi-level cell (MLC) that is capable of storing more than a single bit of data in more than four memory states. For example, the MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In an example, if each MLC stores two bits of data, then the MLC can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.
As shown in
As shown in
The constituent material of the gate layer 411 may include conductive materials. The conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate layer 411 includes a metal layer, e.g., a tungsten layer. In some implementations, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding the memory cells. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper select gate line, and the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower select gate line. The gate layer 411 extending laterally between the upper select gate line and the lower select gate line may serve as a word line layer.
In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may comprise silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.
In some embodiments, the NAND memory strings 308 include channel structures extending vertically through the stacked structure 410. In some implementations, the channel structure includes channel holes filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a “charge trap/storage layer”) and a blocking layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are radially arranged in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).
Referring back to
Page buffer/sense amplifier 504 can be configured to read and program (write) data from and to memory array 301 according to the control signals from control logic 512. In an example, page buffer/sense amplifier 504 may store one page of program data (write data) to be programmed into one page 320 of memory array 301. In another example, page buffer/sense amplifier 504 may perform program verify operations to ensure that the data has been properly programmed into memory cells 306 coupled to selected word lines 318. In still another example, page buffer/sense amplifier 504 may also sense the low power signals from bit line 316 that represents a data bit stored in memory cell 306 and amplify the small voltage swing to recognizable logic levels in a read operation. Column decoder/bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying bit line voltages generated from voltage generator 510.
Row decoder/word line driver 508 may be configured to be controlled by control logic 512 and to select/deselect blocks 304 of memory array 301 and to select/deselect word lines 318 of blocks 304. Row decoder/word line driver 508 may also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some implementations, row decoder/word line driver 508 may also select/deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, row decoder/word line driver 508 is configured to perform program operations on memory cells 306 coupled to selected word line(s) 318. Voltage generator 510 may be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.) to be supplied to memory array 301, bit line voltages and source line voltages.
In some embodiments, the program operation may include multiple steps. Exemplarily, the program operation may include a bit line setting step, a program execution step, and a program recovery step. A program verification operation also is needed to be performed after the program operation is performed; and a program verification recovery operation also is needed to be performed after the program verification operation is performed. During the bit line setting step of performing the program operation, the voltages may be maintained at the ground voltage GND for the unselected word lines. During the program execution step of performing the program operation, the pass voltage Vpass may be applied to the unselected word lines, and the program voltage Vgm may be applied to the selected word lines. Thus, the memory cells connected to the selected word lines can be programmed. During the program recovery step of performing the program operation, the voltages applied to all word lines may be lowered to the ground voltage GND. During performing program verification operation, the verify voltage Vvrf may be applied to the selected word lines, and the read voltage Vrd may be applied to the unselected word lines. During performing program verification recovery operation, the recovery operation that lowers the voltages to the ground voltage GND may be performed on both the unselected word lines and the selected word lines.
Control logic 512 can be coupled to each peripheral circuit described above and configured to control the operations of each peripheral circuit. Registers 514 can be coupled to control logic 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operations of each peripheral circuit. Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic 512 and status information received from control logic 512 to the host. Interface 516 can also be coupled to column decoder/bit line driver 506 via data bus 518 and act as a data I/O interface and a data buffer to buffer and relay the data to and from memory array 301.
In a three-dimensional NAND memory device, one chip may include multiple dies that can independently perform NAND operations (e.g., read, write, and erase). Each die may include a plurality of memory planes, and each memory plane may include a plurality of memory cells stacked vertically to increase storage capacity per unit area In a multi-plane read operation, the word line addresses of all selected memory planes are required to be the same, and the read operations of multiple planes are required to be synchronized, so that the read operations among the plurality of memory planes restrict each other and the read speed is slow. To support fast read operations, in some embodiments, the peripheral circuits can be configured to support asynchronous multi-plane independent read operations, which means that the word line address, page type, and memory cell type for each memory plane can be independently selected. And, the read operation of each memory plane can be performed in one step, that is, the plurality of memory planes can perform asynchronous independent read operations. In the asynchronous multi-plane independent read operations, if the selected word line addresses and page types are different, each memory plane requires different word line bias conditions, so that each memory plane should have a circuit for selecting different voltages, which will significantly increase the area of peripheral circuits.
A memory device is provided in an embodiment of the disclosure, which comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of first selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of second selected voltage selection circuits respectively corresponding to each memory plane, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the first and second selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the first or second selected voltage selection circuits to output to the local word line voltage selection circuits; during a program operation, the plurality of memory planes share the plurality of first selected voltage selection circuits; and during a read operation, each memory plane uses a part of the plurality of second selected voltage selection circuits to perform voltage selection.
In some examples, the row decoder/WL driver shown in
In some examples, as shown in
It can be understood that, in the solution provided by the above embodiment, during the program operation, the first selected voltage selection circuits are used to provide 10 different selected voltages for the special 10 word lines. The number of the required first selected voltage selection circuits is 10 and the 10 first selected voltage selection circuits are shared by the plurality of memory planes. While during the read operation, in order to realize the asynchronous multi-plane independent read operations, the second selected voltage selection circuits are used to provide voltages for the special word lines on different memory planes. Here, the number of selected voltages is 2, and 2 second selected voltage selection circuits are required for each memory plane. For example, when the number of memory planes is 4, 8 second selected voltage selection circuits are required. That is, different selected voltage selection circuits are used in the read operation and the program operation. In total, at least 18 first selected voltage selection circuits and second selected voltage selection circuits need to be arranged in the peripheral circuits. In doing so, the number of the selected voltage selection circuits is larger, and the area of the peripheral circuits and the area of the memory device are larger.
Based on the above problems, another memory device is provided in an embodiment of the present disclosure. The memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the selected voltage selection circuits to output to the local word line voltage selection circuits; during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits; and during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits respectively to perform voltage selection.
Here, the fact that the plurality of selected voltage selection circuits correspond to the plurality of memory planes can be understood that there are various correspondences between the memory planes and the selected voltage selection circuits. During the program operation, the plurality of selected voltage selection circuits correspond to each memory plane in the plurality of memory planes; while during the read operation, different parts of the plurality of selected voltage selection circuits correspond to each memory plane of the plurality of memory planes respectively.
In some examples, the memory cell array and the peripheral circuits are provided on the same chip. In some other examples, the memory cell array is provided on an array chip, and the peripheral circuits are provided on different chips, which may be chips implemented using complementary metal oxide semiconductor (CMOS) technology and called as CMOS chip. The array chip and the CMOS chip can be electrically coupled together using a bonding process. In some examples, the CMOS chip may be coupled with multiple array chips.
It can be understood that the selected voltages and unselected voltages here can be generated by the voltage generator shown in
It can be understood that, in the above-mentioned embodiments of the present disclosure, during the program operation and the read operation, the selected voltage selection circuits are shared. That is, during the read operation, the selected voltage selection circuits during the program operation are multiplexed, and the selected voltage selection circuits during the read operation are not individually set, so that the number of selected voltage selection circuits is small, the area of the peripheral circuits is smaller, and the area of the memory device is reduced.
In the following, it still takes the situation to make an illustration, in which it is necessary to apply different voltages to 10 special word lines during the program operation. There are a total of 10 selected voltages, 4 memory planes need a total of 10 selected voltage selection circuits, and it is necessary to apply two different voltages to 3 special word lines during the read operation, there are a total of 2 unselected voltages, each memory plane needs 2 selected voltage selection circuits, and 4 memory planes need a total of 8 selected voltage selection circuits.
During the program operation, since 4 memory planes share 10 selected voltage selection circuits, a total of 10 selected voltage selection circuits are required. While during the read operation, if the read operation is performed with the asynchronous multi-plane independent read method, each memory plane needs an individual selected voltage selection circuit to select the voltage. Since each memory plane needs to provide 2 selected voltages, a total of 8 selected voltage selection circuits are required to select the voltage. The selected voltage selection circuits during the program operation are multiplexed for the reading, and it is not necessary to individually set 8 selected voltage selection circuits dedicated to the read operation. Therefore, 8 selected voltage selection circuits may be reduced, thereby reducing the area of peripheral circuits.
In some embodiments, during the program operation, the number of selected voltages corresponding to a plurality of memory planes is a, and the number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a; and during the read operation, the number of selected voltages corresponding to each memory plane is b, and the number of the selected voltage selection circuits corresponding to each memory plane is at least b; the number of the memory planes is c, and the relationship among a, b, and c is: a≥b*c; wherein, both a and b are positive integers greater than 0, and c is a positive integer greater than 1.
Here, during the program operation, the selected voltages corresponding to the plurality of memory planes are the different voltages applied to the target word line and the word lines adjacent to the target word line. The fact that the number of selected voltage selection circuits is at least a can be understood that the number of selected voltage selection circuits may be equal to or greater than the number of selected voltages. When the number of selected voltage selection circuits is equal to the number of selected voltages, each selected voltage selection circuit selects one selected voltage. When the number of selected voltage selection circuits is greater than the number of selected voltages, any a selected voltage selection circuits among the plurality of selected voltage selection circuits are configured to select voltage, and the remaining selected voltage selection circuits can be used for backup. During the read operation, the selected voltages corresponding to each memory plane are different. The understanding for the selected voltages and the selected voltage selection circuits may be referred to the previous explanation of the selected voltages and the selected voltage selection circuits during the program operation, which will not be repeated here.
Here, a≥b*c can be understood as follows. Since the selected voltage selection circuits are shared during the program operation and the read operation, and a total of b*c selected voltage selection circuits are required during the read operation, the number of the selected voltage selection circuits during the program operation is greater than or equal to the total number of the selected voltage selection circuits during the read operation, in order that each memory plane may be assigned with b selected voltage selection circuits for selecting voltage during the read operation.
In some examples, as shown in
In some examples, the local word lines may be divided into multiple groups, and each group includes 20 local word lines (for a memory device in which the number of local word lines corresponding to each memory plane is 232, the number of local word lines included in some groups is less than 20). Only the group including the target local word line and the special local word lines adjacent to the target local word line is supplied with voltages using the global word line voltage selection circuits, while the local word lines of other groups are all supplied with voltages using the unselected voltage selection circuits. In the solutions proposed in
In order to further reduce the area of the peripheral circuits, the following solutions are proposed from the aspect of the unselected voltage selection circuits.
In some embodiments, the peripheral circuit further comprises: a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to a plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit; each unselected voltage selection circuit is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits; during a program operation, the plurality of memory planes share the plurality of unselected voltage selection circuits; during a read operation, each memory plane uses a part of the plurality of unselected voltage selection circuits respectively to perform voltage selection.
Here, for the plurality of unselected voltage selection circuits corresponding to the plurality of memory planes, it can be understood that there are various correspondences between the memory planes and the unselected voltage selection circuits. During the program operation, the plurality of unselected voltage selection circuits corresponds to each of the plurality of memory planes, while during the read operation, the different parts of the plurality of unselected voltage selection circuits correspond to each of the plurality of memory planes respectively.
In some embodiments, during the program operation, the number of unselected voltages corresponding to the plurality of memory planes is d, and the number of unselected voltage selection circuits corresponding to the plurality of memory planes is at least d; during the read operation, the number of unselected voltages corresponding to each memory plane is e, and the number of unselected voltage selection circuits corresponding to each memory plane is at least e; the number of the memory planes is c, and the relationship among c, d, and e is: d≥e*c; wherein, both d and e are positive integers greater than 0, and c is a positive integer greater than 1.
Here, during the program operation, the unselected voltages corresponding to the plurality of memory planes are the voltages applied to the word lines other than the special word lines (including the target word line and the plurality of word lines adjacent to the target word line). The fact that the number of unselected voltage selection circuits is at least d can be understood that the number of unselected voltage selection circuits may be equal to or greater than the number of unselected voltages. When the number of unselected voltage selection circuits is equal to the number of unselected voltages, each unselected voltage selection circuit selects one unselected voltage. When the number of unselected voltage selection circuits is greater than the number of unselected voltages, any d unselected voltage selection circuits among the plurality of selected voltage selection circuits are configured to select voltage, and the remaining unselected voltage selection circuits can be used for backup. During the read operation, the unselected voltages corresponding to each memory plane are different. The understanding for the unselected voltages and the unselected voltage selection circuits may be referred to the previous explanation of the selected voltages and the selected voltage selection circuits during the program operation, which will not be repeated here.
Here, d≥e*c can be understood as follows, since the unselected voltage selection circuits are shared during the program operation and the read operation, and a total of e*c unselected voltage selection circuits are required during the read operation, the number of the unselected voltage selection circuits during the program operation is greater than or equal to the total number of the unselected voltage selection circuits required during the read operation, in order that each memory plane may be assigned with e unselected voltage selection circuits for selecting voltage during the read operation.
In the solutions proposed in the embodiments corresponding to
In some embodiments, the peripheral circuit further comprises: a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one; during a program operation, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and the adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; during a read operation, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of selected voltage selection circuits corresponding to each memory plane is b, and the adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits.
In some embodiments, each of the memory planes comprises a plurality of word lines; the peripheral circuit further includes a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one, and a plurality of local word lines corresponding to the local word line voltage selection circuits one-to-one; wherein, each of the global word lines corresponds to the plurality of local word lines; each of the local word lines corresponds to one global word line, and each of the local word lines corresponds to one word line; the global word line voltage selection circuits output a voltage to the local word line voltage selection circuits through the global word lines; the local word line voltage selection circuits output a voltage to the corresponding word lines through the local word lines.
In some examples, the global word line voltage selection circuits are used to select a voltage from unselected voltages and the voltage output from the selected voltage selection circuits to output to the local word line voltage selection circuits through one global word line; the local word line voltage selection circuits are used to select a voltage from voltages output by the corresponding global word line voltage selection circuits and the voltage output by the unselected voltage selection circuits to output to the corresponding word lines through one local word line.
In some examples, for the 3D NAND in which there are 4 memory planes (Plane0-Plane3), each memory plane in the peripheral circuits corresponds to 232 local word lines, each memory plane corresponds to 20 global word lines, 4 memory planes correspond to 10 selected voltages during the program operation, 4 memory planes correspond to 12 unselected voltages during the program operation, each memory plane corresponds to 2 selected voltages during the read operation, and each memory plane corresponds to 1 unselected voltage during the read operation, Table 1 shows the correspondence of the selected voltage selection circuits (configurable voltage domain 0-configurable voltage domain 7), the global word line voltage selection circuits (gwl0-gwl19), unselected voltage selection circuits (gwlu0-gwlu11), and local word lines (LWL0-LWL231) corresponding to one memory plane in the peripheral circuit provided according to an embodiment of the disclosure. It should be noted that, the correspondence of each pan in Table 1 is just an example, and is not used to limit the correspondence between each part in the memory device in the embodiment of the present disclosure.
In some embodiments, the selected voltage selection circuits, the global word line voltage selection circuits, the local word line voltage selection circuits, and the unselected voltage selection circuits all comprise a multiplexer.
In some examples, the memory device includes a three-dimensional NAND memory device.
However, the memory device the embodiment of the present disclosure is not limited to the three-dimensional NAND memory device. In the embodiment of the present disclosure, the memory device may be a semiconductor memory device, including but not limited to a three-dimensional NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a Dynamic Random Access Memory (DRAM), a Ferroelectric Random Access Memory (FRAM), a Magnetoresistive Random Access Memory (MRAM), a Phase Change Random Access Memory (PCRAM), a Resistive Random Access Memory (RRAM) or a Nano Random Access Memory (NRAM), etc.
An embodiment of the present disclosure provides a memory device, the memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the selected voltage selection circuits to output to the local word line voltage selection circuits; during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits; and during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits to perform voltage selection. In the embodiment of the present disclosure, during the program operation, the plurality of memory planes share the plurality of selected voltage selection circuits, while during the read operation, each memory plane uses a part of the plurality of selected voltage selection circuits used during the program operation to perform voltage selection. That is, in the embodiment of the present disclosure, the program operation and the read operation share the selected voltage selection circuits, so the selected voltage selection circuits required during the read operation need not to be additionally added. Thus, the total number of the selected voltage selection circuits is small, and the area of the memory device may be reduced, which is beneficial to the miniaturization of the memory device.
An embodiment of the present disclosure also provides a memory system, comprising: one or more memory devices as described in any of the above embodiments; and a memory controller coupled to and controlling the memory device.
Here, with respect to the structure and composition of the memory system, reference may be made to the related structure and composition of the memory system 102 in the aforementioned
In some embodiments, the memory system comprises a memory card or a solid-state hard disk.
Based on the above memory device, a method for operating a memory device is also provided in an embodiment of the present disclosure. The memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array; the memory cell array includes a plurality of memory planes; the peripheral circuit includes a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane; the selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the selected voltage selection circuits to output to the local word line voltage selection circuits.
As show in
In some embodiments, during the program operation performed on the plurality of memory planes simultaneously, the number of selected voltages corresponding to the plurality of memory planes is a, and the number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a; and during the read operation performed on the plurality of memory planes, the amber of selected voltages corresponding to each memory plane is b, and the number of the selected voltage selection circuits corresponding to each memory plane is at least b; the number of the memory planes is c, and the relationship among a, b and c is: a≥b*c; wherein, both a and b are positive integers greater than 0, and c is a positive integer greater than 1.
In some embodiments, the peripheral circuit further comprises: a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one; during the program operation performed on the plurality of memory planes simultaneously, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and the adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; during the read operation performed on the plurality of memory planes, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of selected voltage selection circuits corresponding to each memory plane is b, and the adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits.
In some embodiments, the peripheral circuit further comprises: a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to a plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit; each unselected voltage selection circuit is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits; the method further includes: applying a plurality of different voltages output by the plurality of unselected voltage selection circuits to each memory plane in response to the first instruction; applying a part of the plurality of different voltages output by the plurality of unselected voltage selection circuits respectively to different memory planes in response to the second instruction.
In some embodiments, during the program operation, the number of unselected voltages corresponding to the plurality of memory planes is d, and the number of unselected voltage selection circuits corresponding to the plurality of memory planes is at least d; during the read operation, the number of unselected voltages corresponding to each memory plane is e, and the number of unselected voltage selection circuits corresponding to each memory plane is at least e; the number of the memory planes is c, and the relationship among c, d and e is: d≥e*c; wherein, both d and e are positive integers greater than 0, and c is a positive integer greater than 1.
In some embodiments, each of the memory planes comprises a plurality of word lines; the peripheral circuit further includes a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one, and a plurality of local word lines corresponding to the local word line voltage selection circuits one-to-one; wherein, each global word line corresponds to the plurality of local word lines; each local word line corresponds to one global word line, and each local word line corresponds to one word line; the global word line voltage selection circuits output the voltage to the local word line voltage selection circuits through the global word lines; the local word line voltage selection circuits output the voltage to the corresponding word lines through the local word lines.
In some embodiments, an asynchronous multi-plane independent read method is used to perform the read operation on the plurality of memory planes during the read operation performed on the plurality of memory planes.
It is to be understood that reference to “one embodiment” or “an embodiment” throughout the specification means that particular features, structures, or characteristics associated with the embodiment are included in at least an embodiment of the present disclosure. Thus, appearances of “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the orders of the above-mentioned processes does not imply the sequence of execution, and the execution sequence of processes should be determined by its functions and internal logic, without limiting the implemented processes of the embodiments of the present disclosure. The above-mentioned orders of the embodiments of the present disclosure are only for description, and do not represent the advantages or disadvantages of the embodiments.
The methods disclosed in the several method embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments.
The above are only exemplary implementations of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any changes or substitutions will be apparent for the skilled in the art within the technical scope disclosed in the present disclosure, and should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210864398.8 | Jul 2022 | CN | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 11636887 | Kang | Apr 2023 | B2 |
| 11735248 | Lee | Aug 2023 | B2 |
| 11790980 | He | Oct 2023 | B2 |
| 20090109738 | Donze | Apr 2009 | A1 |
| 20140112061 | Jung | Apr 2014 | A1 |
| 20230079077 | Hemati | Mar 2023 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20240029793 A1 | Jan 2024 | US |
