Memory Devices Employing Ferroelectric Layer as Information Storage Elements and Methods of Fabricating the Same

Abstract

A memory device includes one or more layers of parallel strings of ferroelectric gate transistors on a substrate, each layer of parallel strings including a plurality of parallel line-shaped active regions and a plurality of word lines extending in parallel transversely across the active regions and disposed on ferroelectric patterns on the active regions. A string select gate line may extend transversely across the active regions in parallel with the word lines. A ground select gate line may extend transversely across the active regions in parallel with the word lines.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a symbol for a one-transistor type NDRO-FRAM cell.

FIGS. 2A and 2B are cross-sectional views illustrating operations of the one transistor type NDRO-FRAM cell of FIG. 1.

FIG. 3 is a plan view illustrating operations for fabricating a flash memory device in accordance with some exemplary embodiments of the present invention.

FIGS. 4A, 5A, 6A, 7A, 8A, and 9A are cross-sectional views taken along line I-I′ of FIG. 3, and FIGS. 4B, 5B, 6B, 7B, 8B, and 9B are cross-sectional views taken along line II-II′ of FIG. 3.

FIG. 10 is a plan view illustrating operations for fabricating a flash memory device in accordance with other exemplary embodiments of the present invention.

FIGS. 11A, 12A, 13A, and 14A are cross-sectional views taken along line III-III′ of FIG. 10, and FIGS. 11B, 12B, 13B, and 14B are cross-sectional views taken along line IV-IV′ of FIG. 10.

FIG. 15A is a circuit diagram illustrating write operations for a flash memory device in accordance with some exemplary embodiments of the present invention.

FIG. 15B is a circuit diagram illustrating read operations for a flash memory device in accordance with some exemplary embodiments of the present invention.

FIG. 15C is a circuit diagram illustrating read operations for a flash memory device with select gates including a ferroelectric pattern and a gate electrode, which are stacked according to some exemplary embodiments of the present invention.

FIG. 16A is a circuit diagram illustrating write operations for a flash memory device in accordance with further exemplary embodiments of the present invention.

FIG. 16B is a circuit diagram illustrating read operations for a flash memory device in accordance with further exemplary embodiments of the present invention shown.

Claims

1. A memory device comprising: a layer of parallel strings of ferroelectric gate transistors on a substrate, the layer of parallel strings comprising a plurality of parallel line-shaped active regions, a plurality of ferroelectric patterns disposed on the line-shaped active regions, and a plurality of word lines extending in parallel transversely across the active regions and disposed on the ferroelectric patterns.

2. The memory device of claim 1, further comprising a string select gate line extending transversely across the active regions in parallel with the word lines.

3. The memory device of claim 1, further comprising a ground select gate line extending transversely across the active regions in parallel with the word lines.

4. The memory device of claim 1, wherein the layer of parallel strings comprises first and second overlapping layers of parallel strings comprising respective first and second layers of parallel line-shaped active regions and respective first and second pluralities of word lines extending in parallel across respective ones of the first and second layers of active regions and disposed on ferroelectric patterns on the active regions, and wherein the memory device further comprises respective first and second layer select lines extending across respective ones of the first and second layers of active regions in parallel with the respective first and second pluralities of word lines.

5. The memory device of claim 4, further comprising a string select gate line extending transversely across one of the layers of active regions in parallel with the word lines thereon.

6. The memory device of claim 4, further comprising a ground select gate line extending transversely across one of the layers of active regions in parallel with the word lines thereon.

7. A memory device, comprising: a semiconductor substrate;an isolation layer defining a line-shaped active region in the semiconductor substrate;a string select gate and a ground select gate spaced apart on the substrate and extending across the active region;a ferroelectric pattern on the active region between the string select gate and the ground select gate; anda word line on the ferroelectric pattern and extending across the active region between the string select gate and the ground select gate.

8. The memory device of claim 7, further comprising source/drain regions disposed in the active region between adjacent ones of the string select gate, the word line and the ground select gate.

9. The memory device of claim 8, wherein the line-shaped active region comprises a line-shaped well disposed therein having a first conductivity type and wherein the source/drain regions are disposed in the line-shaped well and have a second conductivity type.

10. The memory device of claim 7: wherein the string select gate comprises:a string select gate insulating layer on the active region; anda string select gate electrode on the string gate insulating layer; andwherein the ground select gate comprises:a ground select gate insulating layer on the active region; anda ground select gate electrode on the ground select gate insulating layer.

11. The memory device of claim 10, wherein the string select gate electrode and the ground select gate electrode comprise polysilicon patterns and/or stacks comprising polysilicon pattern and a metal silicide, and wherein the gate insulating layer comprises a silicon oxide layer and/or a high-k dielectric layer.

12. The memory device of claim 10, wherein the string select gate electrode and the ground select gate electrode and the word line include the same material, and wherein the string select gate insulating layer, the ground select gate insulating layer and the ferroelectric pattern include the same material.

13. The memory device of claim 7, wherein the ferroelectric pattern comprises a lead zirconate titanate layer (PbZrxTi1-xO3; PZT), a bismuth lanthanum titanate layer (Bi4-xLaxTi3O12; BLT), a strontium bismuth tantalite layer (SrBi2Ta2O5; SBT) and/or a lead germanium oxide layer (Pb5Ge5O11; PGO).

14. The memory device of claim 7, wherein the word line comprises platinum (Pt), ruthenium (Ru), iridium (Ir) and/or iridium oxide (IrO2).

15. The memory device of claim 7, further comprising an interfacial insulating layer pattern or a stack including an interfacial insulating layer pattern and a lower electrode interposed between the active region and the ferroelectric pattern.

16. The memory device of claim 7, wherein the word line comprises a first word line and wherein the memory device further comprises: a lower interlayer insulating layer on the first word line;a source line extending through the lower interlayer insulating layer to contact the active region on a side of the ground select gate opposite the word line;an upper interlayer insulating layer covering the source line and the lower interlayer insulating layer; anda bit line extending through the upper and lower interlayer insulating layers to contact the active region on a side of the string select gate electrode opposite the word line.

17. The memory device of claim 7, wherein the ferroelectric patterns comprise first ferroelectric patterns, wherein the word line comprises a first word line, and wherein the memory device further comprises: a first layer select gate on the substrate and crossing the active region between the string select gate and the ground select gate;an interlayer insulating layer covering the string select gate, the first word lines, the first layer select gate and the ground select gate;a line-shaped semiconductor body pattern on the interlayer insulating layer and extending parallel to the active region;a first contact plug extending through the line-shaped semiconductor body pattern and the interlayer insulating layer to contact the active region between the ground select gate and the first word line;a second contact plug extending through the line-shaped semiconductor body pattern and the interlayer insulating layer to contact the active region between the string select gate and the first word line;a second layer select gate extending across the line-shaped semiconductor body pattern between the first and second contact plugs;a second ferroelectric pattern on the line-shaped semiconductor body pattern between the first and second contact plugs; anda second word line on the second ferroelectric pattern and extending across the semiconductor body pattern between the first and second contact plugs.

18. The memory device of claim 17, wherein the first and second word lines comprise the same material, and wherein the first and second ferroelectric patterns comprise the same material.

19. The memory device of claim 17, wherein the first and second layer select gates each comprise a ferroelectric pattern and a gate electrode thereon.

20. The memory device of claim 17, further comprising second source/drain regions disposed in the semiconductor body pattern adjacent the second layer select gate and the second word line.

21. The memory device of claim 20, further comprising an impurity well in the semiconductor body pattern and having a first conductivity type, and wherein the second source/drain regions have a second conductivity type.

22. A memory device, comprising: a semiconductor substrate;an isolation region defining a plurality of line-shaped active regions disposed in parallel in the semiconductor substrate;respective ferroelectric patterns on respective ones of the active regions;a word line extending transversely across the active regions and disposed on the ferroelectric patterns;source/drain regions in the active regions on respective first and second sides of the word line;a common source line on the substrate and connected to the source/drain regions on the first side of the word line; andrespective bit lines on the substrate and connected to respective ones of the source/drain regions on the second side of the word line.

23. The memory device of claim 22, further comprising respective line-shaped wells in respective ones of the line-shaped active regions, and wherein the source/drain regions are disposed in the line-shaped wells.

24. The memory device of claim 22, wherein the ferroelectric patterns comprise a lead zirconate titanate layer (PbZrxTi1-xO3; PZT), a bismuth lanthanum titanate layer (Bi4-xLaxTi3O12; BLT), a strontium bismuth tantalite layer (SrBi2Ta2O5; SBT) and/or a lead germanium oxide layer (Pb5Ge5O11; PGO).

25. The memory device of claim 22, wherein the word line comprises platinum (Pt), ruthenium (Ru), iridium (Ir) and/or iridium oxide (IrO2).

26. The memory device of claim 22, further comprising respective interfacial insulating layer patterns or respective stacks including an interfacial insulating layer pattern and a lower electrode interposed between the active regions and the respective ferroelectric patterns.

27. The memory device of claim 22, wherein the ferroelectric patterns comprise first ferroelectric patterns, wherein the word line comprises a first word line, wherein the common source line comprises a first common source line, wherein the bit lines comprise first bit lines, and wherein the memory device further comprises: a layer isolation insulating layer on the first bit lines;a plurality of line-shaped semiconductor body patterns on the layer isolation layer insulating layer and extending parallel to the line-shaped active regions;second ferroelectric patterns on the semiconductor body patterns;a second word line extending transversely across the semiconductor body patterns parallel to the first word line and disposed on the second ferroelectric patterns;second source/drain regions in the semiconductor body patterns on respective first and second sides of the second word line;a second common source line on the substrate and electrically connected to the second source/drain regions on the first side of the second word line; anda second plurality of bit lines on the substrate and electrically connected to the second source/drain regions on the second side of the second word line.

28. The memory device of claim 27, further comprising respective impurity wells in respective ones of the semiconductor body patterns and having a first conductivity type, and wherein the second source/drain regions are disposed in the impurity wells and have a second conductivity type.

29. The memory device of claim 22: wherein the ferroelectric patterns comprises respective pluralities of spaced-apart ferroelectric patterns on respective ones of the active regions;wherein the word line comprises a plurality of parallel word lines extending across the plurality of active regions and disposed on the ferroelectric patterns; andwherein the memory device further comprises:respective string select gates on respective ones of the plurality of active regions on a first side of the word line; andrespective ground select gates on respective ones of the plurality of active regions on a second side of the word line.

30. The memory device of claim 22: wherein the ferroelectric patterns comprises respective pluralities of spaced-apart ferroelectric patterns on respective ones of the active regions;wherein the word line comprises first and second parallel word lines extending across the plurality of active regions and disposed on the ferroelectric patterns; andwherein the common source line is disposed between the first and second word lines and extends parallel thereto.

31. A method of fabricating a memory device, comprising: forming an isolation region defining a line-shaped active region;forming a string select gate structure, a ground select gate structure and a word line structure extending in parallel across the active region, the word line structure disposed between the string select gate structure and the ground select gate structure and comprising a ferroelectric pattern on the active region and a word line on the ferroelectric pattern;

32. The method of claim 31, wherein forming a select gate structure, a ground select gate structure and a word line structure extending in parallel across the active region comprises: forming the word line gate structure on the substrate;forming a protective pattern covering the first cell gate;sequentially forming a gate insulating layer and a gate electrode layer on the substrate; andpatterning the gate electrode layer and the gate insulating layer and forming the string select gate structure and the ground select gate structure.

33. The method of claim 32, wherein the gate insulating layer comprises a silicon oxide layer or a high-k dielectric layer, and the gate electrode layer comprises a polysilicon layer and/or a stack including a polysilicon layer and a metal silicide layer.

34. The method of claim 31, wherein the string select gate structure, the ground select gate structure and the word line structure have the same stacked structure.

35. The method of claim 31, wherein the word line structure comprises an interfacial insulating layer pattern or an interfacial insulating layer pattern and a lower electrode interposed between the active region and the ferroelectric pattern.

36. The method of claim 31, further comprising forming source/drain regions in the active region using the string select gate structure, the ground select gate structure, and the word line structure as ion implantation masks.

37. The method of claim 36: wherein forming a source line comprises:forming a lower interlayer insulating layer covering the string select gate structure, the ground select gate structure, and the word line structure; andforming a source line extending through the lower interlayer insulating layer to contact the active region on a side of the ground select gate structure opposite the word line structure; andwherein forming a bit line comprises:forming an upper interlayer insulating layer on the source line and the lower interlayer insulating layer; andforming a bit line on the upper insulation layer and extending through the upper and lower interlayer insulating layers to contact the active region on a side of string select gate structure opposite the word line.

38. The method of claim 37, further comprising forming a layer select gate structure on the active region between the ground select gate structure and the word line structure concurrent with forming the string select gate structure and the ground select gate structure.

39. The method of claim 38, wherein the word line structure comprises a first word line structure, wherein the layer select gate structure comprises a first layer select gate structure, wherein the source/drain regions comprise first source/drain regions, and wherein the method further comprises: prior to the formation of the upper interlayer insulating layer, forming a line-shaped semiconductor body pattern on the lower interlayer insulating layer and extending parallel to the line-shaped active region;forming a second word line structure and a second layer select gate structure extending across the semiconductor body pattern parallel to the first word line structure;forming second source/drain regions in the semiconductor body pattern using the second word line structure and the second layer select gate structure as ion implantation masks; andforming first and second contact plugs penetrating the lower interlayer insulating layer and electrically connecting the first source/drain regions between the ground select gate structure and the first layer select gate structure and between the string select gate structure and the first world line structure with respective ones of the second source/drain regions, wherein the second layer select gate structure is formed between the first contact plug and the second word line structure.

40. The method of claim 39, wherein the ferroelectric pattern comprises a first ferroelectric pattern, wherein the word line comprises a first word line, and wherein the second word line structure comprises a second ferroelectric pattern and a second word line thereon.

41. The method of claim 39, further comprising, after the formation of the semiconductor body pattern, forming an impurity well having a first conductivity type, and wherein forming second source/drain regions comprises forming the second source/drain regions with a second conductivity type in the semiconductor body pattern.

42. The method of claim 39, wherein forming the line-shaped semiconductor body pattern comprises: forming a contact hole penetrating the lower interlayer insulating layer and exposing the active region between the string select gate and the first word line structure;forming a single crystalline contact plug in the contact holes using a single crystalline growth process;forming a non-single crystalline semiconductor layer covering the single crystalline contact plug on the lower interlayer insulating layer;forming the non-single crystalline semiconductor layer into a single crystalline semiconductor layer using a solid phase epitaxy process; andpatterning the single crystalline semiconductor layer to form the semiconductor body pattern.

43. A method of fabricating a memory device, comprising: forming an isolation layer defining a plurality of line-shaped active regions disposed in parallel in a semiconductor substrate;forming a word line structure on the substrate crossing the active regions, the word line structures comprising respective ferroelectric patterns on the active regions and a word line on the ferroelectric patterns;implanting impurity ions into the active regions using the word line structure as an ion implantation mask to form source/drain regions in the active regions;forming a common source line one the substrate electrically connecting the first source regions on a first side of the word line structure; andforming respective bit lines on the substrate and connected to respective ones of the source/drain regions on the second side of the word line structure.

44. The method of claim 43, comprising: prior to forming the source/drain regions, forming respective line-shaped wells within the line-shaped active regions; andforming the source/drain regions in the line-shaped wells.

45. The method of claim 43, wherein the common source line extends parallel to the word line gate structure or parallel to the active regions.

46. The method of claim 43, wherein the word line structure comprises respective interfacial insulating layer patterns or respective stacks including an interfacial insulating layer pattern and a lower electrode interposed between the active regions and the respective ferroelectric patterns.

47. The method of claim 43, wherein the word line structure comprises a first word line structure, wherein the common source line comprises a first common source line, wherein the bit lines comprise first bit lines, and wherein the method further comprises: forming a layer isolation insulating layer covering the first word line structure;forming a plurality of line-shaped semiconductor body patterns parallel to the line-shaped active regions on the layer isolation insulating layer;forming a second word line structure crossing the semiconductor body patterns parallel to the first word line structure;implanting impurity ions into the semiconductor body patterns using the second word line structure as an ion implantation mask to form second source/drain regions in the semiconductor body patterns on respective first and second sides of the second word line structure;forming a second common source line electrically connecting the second source/drain regions on the first side of the second word line structure;forming an upper interlayer insulating layer covering the second common source line; andforming second bit lines on the upper interlayer insulating layer and extending therethrough to contact respective ones of the second source/drain regions on the second side of the second word line structure.

48. The method of claim 47, wherein the second word line structure comprises respective second ferroelectric patterns on respective ones of the semiconductor body patterns and a second word line on the second ferroelectric patterns.

49. The method of claim 47, further comprising, after the formation of the semiconductor body patterns, forming respective impurity wells having a first conductivity type in respective ones of the semiconductor body patterns, and wherein the second source/drain regions are disposed in the impurity wells.

50. The method of claim 47, wherein forming the line-shaped semiconductor body patterns comprises: forming contact holes exposing the active regions through the layer isolation insulating layer and the lower interlayer insulating layer;forming single crystalline contact plugs within the contact holes using a single crystalline growth process;forming a non-single crystalline semiconductor layer covering the single crystalline contact plugs on the layer isolation insulating layer;forming the non-single crystalline semiconductor layer into a single crystalline semiconductor layer using a solid phase epitaxy process; andpatterning the single crystalline semiconductor layer to form the semiconductor body patterns.

51. A write method for a memory device comprising a plurality of parallel line-shaped semiconductor wells and a plurality of ferroelectric word line structures comprising parallel word lines extending across the line-shaped wells and disposed on respective ferroelectric patterns, the method comprising: simultaneously applying a first voltage to a selected well, floating others of the wells, applying a second voltage to a selected word line, and floating others of the word lines to polarize one of the ferroelectric patterns interposed between the selected word line and the selected well.

52. The write method of claim 51, wherein the memory device comprises source/drain regions in the wells adjacent the word line structures, and wherein simultaneously applying a first voltage to a selected well, floating others of the wells, applying a second voltage to a selected word line, and floating others of the word lines to polarize one of the ferroelectric patterns interposed between the selected word line and the selected well comprises simultaneously applying the first voltage to the selected well, floating the others of the wells, applying the second voltage to the selected word line, floating the others of the word lines and floating or grounding the source/drain regions to polarize the one of the ferroelectric patterns interposed between the selected word line and the selected well.

53. The write method of claim 51, wherein the first voltage is a ground voltage and the second voltage is a voltage greater than the first voltage.

54. The write method of claim 51, wherein the first voltage is a ground voltage and the second voltage is a voltage lower than the first voltage.

55. A read method for a memory device comprising a plurality of parallel line-shaped semiconductor wells, a plurality of ferroelectric word line structures comprising parallel word lines extending across the line-shaped wells and disposed on ferroelectric patterns on the line-shaped wells, and source/drain regions disposed in the wells between the word line structures, the method comprising: while simultaneously grounding a selected well, floating or grounding a selected word line and applying a pass voltage to others of the word lines, determining a current passing through a channel controlled by the selected word line.

56. The read method of claim 55, wherein the memory device comprises first and second stacked layers of parallel line-shaped wells connected such that a respective well from the first layer is paralleled with a respective well from the second layer, respective first and second pluralities of word line structures comprising parallel word lines extending across respective ones of the first and second layers of parallel line-shaped wells and disposed on ferroelectric patterns on the wells, respective string select gates on one of the first and second wells and configured to couple respective paralleled wells from the first and second layers to respective bit lines, respective ground select gates on of the first and second wells and configured to couple respective parallels wells from the first and second layers to a source line, and respective first and second layer select gates extending across respective ones of the first and second layers of wells, and wherein while simultaneously grounding a selected well, floating or grounding a selected word line and applying a pass voltage to others of the word lines, determining a current passing through a channel controlled by the selected word line comprises: while simultaneously grounding a selected well from the first and second layers of wells, applying a turn-on voltage to a string select gate and a ground select gate associated with the selected well, applying a turn-on voltage to a selected one of the first and second layer select gates, and floating or grounding a selected word line and applying the pass voltage to others of the word lines, determining a current passing through a channel in the selected well controlled by the selected word line.

57. A read method of a memory device comprising a plurality of parallel line-shaped semiconductor wells, a plurality of ferroelectric word line structures comprising parallel word lines extending across the line-shaped wells and disposed on ferroelectric patterns on the line-shaped wells, and source/drain regions disposed in the wells adjacent the word line structures, the method comprising: while simultaneously grounding a selected well, floating or grounding a selected word line, applying an off voltage to non-selected word lines and applying a read voltage to a source/drain region adjacent the selected word line, determining a current flowing through a channel controlled by the selected word line.