Patent Application
20070258278
In computer systems, random access memories (RAM) are often organized in memory ranks, a term that was created by JEDEC, the memory industries standards group. The concept of memory ranks applies to all memory module form factors, including desk top DIMMs (dual in-line memory modules), notebook SODIMM (small outline dual in-line memory module), and workstation and server registered DIMMs. A memory rank is a block or area of data that is created using some or all of the memory chips on a memory module.
A rank must be 64-bits of data wide. On memory modules which support error correction code (ECC), the 64-bit wide data area requires an 8-bit wide ECC area for a total width of 72-bits. Depending on how memory modules are engineered, they can contain one, two, or four areas/ranks of 64-bit wide data areas (or 72-bit wide areas/ranks, where 72 bits=64 data bits and 8 ECC bits).
Up to now, modules with memory chips on one side (single-sided modules) of printed circuit (PC) boards have always been single-rank. Double-sided unbuffered DIMMs and SODIMMs could be either single-rank or dual rank. Registered DIMMs, used for servers and workstations, vary from a single-rank to up to four ranks, whereby a double-sided registered DIMM can be:
single-rank, with all the memory chips on one/both sides representing a single 64-bit wide plus 8 bit ECC area;
dual-rank (with one rank per side), or if a stacked DRAM is used, the bottom and top die will be different ranks; or
quad-rank (with two ranks per side for a total of four ranks), or if a stacked DRAM is used, different dies in the stack will be different ranks.
In general, server memory modules are built using ×4 (“by four”) DRAM chips and are more expensive than rank memory modules (which are built using ×8 DRAM chips). Even if both module types have the same number of chips, the ×4 DIMMs (will be two ranks and with twice the memory size) are more expensive than ×8 DIMMs.
For such multiple rank modules, power consumption is very critical and the heat dissipated is very high.
According to an exemplary embodiment of the present invention, a memory module comprises: a PC board, a first rank of memory chips assembled on the PC board, and a second rank of memory chips assembled on the PC board, wherein a first part (some number) of the memory chips of the first rank is assembled on one side of the PC board and the other part of the memory chips of the first rank is assembled on the other side of the PC board, and a first part of the memory chips of the second rank is assembled on the one side of the PC board, and the other part of the memory chips of the second rank is assembled on the other side of the PC board.
The memory chips of first rank can be assembled on one half of the PC board (e.g., the lower half), while the memory chips of the second rank can be assembled on the other half of the PC board (e.g., the upper half). In this way, the Command Address bus to the ranks can be separated, and can be activated (addressed) only when that particular rank access is required. Due to this organization of memory chips, it is possible to reduce the switching power that is necessary for switching the Command Address bus.
In a further embodiment of the present invention, a memory module comprises: a PC board, a first rank of memory chips assembled on the PC board, a second rank of memory chips assembled on the PC board, a first address bus connected to the first rank of memory chips, and a second separate address bus connected to the second rank of memory chips. With this embodiment, the separated ranks can be driven by separate registers or separate command address bus copies within the same register, which can be turned on only when that particular rank is addressed by the memory controller. This reduces the power required for switching the command address (CA)-bus. This method may be used for modules with four ranks as well, where each DRAM is replaced by a stacked DRAM.
In a further embodiment, a method for using a memory module, which comprises a PC board, a first rank of memory chips assembled on the PC board, a second rank of memory chips assembled on the PC board, a first address bus connected to the first rank of memory chips, and a second address bus connected to the second rank of memory chips, is described, wherein only the address bus of the rank which is addressed is activated. In this manner, switching power is saved by not activating the address bus of the other rank, which is not addressed. Since the switching power is less, the module dissipates less power and can be operated without a full DIMM heat spreader.
In a further embodiment, a method for manufacturing a memory module is presented, involving: assembling a first part (some number) of a first rank of memory chips on one side of a PC board, assembling a second part of the first rank of memory chips on the other side of the PC board, assembling a first part of the second rank of memory chips on one side of the PC board, and assembling a second part of the second rank of memory chips on the other side of the PC board. An advantage of this embodiment is the possibility of reducing the power consumption and the heat dissipation due to the fact that switching load is reduced as both the ranks can be split and can be driven separately.
In a further embodiment, a method for manufacturing a memory module is presented, which comprises: assembling a first rank of memory chips on a PC board, assembling a second rank of memory chips on the PC board, and providing a first address bus, which is connected to the first rank of memory chips, and providing a second address bus, which is connected to the second rank of memory chips. An advantage of this separation is that the separated ranks can be driven by a separate register or separate command address bus copy within the same register which can be turned on only when that particular rank is addressed by the memory controller. This reduces the power required for switching CA bus.
A computer system with a memory module as described exhibits the same advantages as described above.
Detailed embodiments of the present invention are now described with reference to the views of the drawing.
In
With this method and memory module, the separated ranks R0 and R1 can be driven by separate registers 4, 7 which can be turned on only in response to the corresponding particular rank R0 or R1 being addressed by the memory controller.
The method may be used for modules with four ranks as well, where each memory chip 3 is replaced by a stacked DRAM.
In
The data is provided via a data bus 22, which in the conventional arrangement has a wiring on one side of the PC board 1 and is contacting a memory chips 3 on the other side of the PC board 1 with the help of via hole (depicted schematically with arrows 33). Accordingly, the data bus of both of the ranks R0, R1 are connected together, which is desired in this connection.
The address bus (CA-bus) normally is 26-28 bits wide. In this conventional scheme, if either of the ranks R0, R1 has to be addressed, then the command address of both the ranks R0, R1 should be addressed/switched, which will result in higher power consumption/heat dissipation.
For example, a conventional memory module 2 with 36 DRAMS (18 DRAMs on each side of the PC board 1) for a 2R×4 (two ranks in a “×4” configuration) and therefore 36 DRAMs to be switched by two or four (two pairs) registers, each DRAM having a capacitance of about 1.5 pF, with 28 CA-BUS lines (command & address bus lines) would result in a DRAM load of 1.5 pF*28*36=1512 pF. With a PC board trace capacitance of about 10 pF and 4 address bus copies (in
A memory module 2 according to an exemplary embodiment of the present invention (
This method can also be implemented in DDR3, where the address bus is “fly by bus” with end termination.
The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appending claims rather than by the foregoing description and all changes which come within the meaning and the range of equivalency of the claims are therefore intended to be embraced therein.
