Claims
- 1. An integrated circuit having(i) a subassembly of solid-state devices (ii) metal wiring formed from conductive metals wherein the metal wiring connects the devices within the subassembly (iii) a porous dielectric layer formed over the conductive metals wherein said porous dielectric layer contains pores (iv) interconnect openings formed in the porous dielectric layer (v) a sealing dielectric layer covering pores of the porous dielectric within the interconnect opening (vi) a metal diffusion barrier within the interconnect opening wherein said sealing dielectric layer is selected from (1) SixCy:Hz where x has a value of 10-50, y has a value of 1-66, z has a value of 0.1-66 and x+y+z≧90 atomic %; (2) SiaObCc:Hd where a has a value of 10 to 33, b has a value of 1 to 40, c has a value of 1 to 66, d has a value of 0.1 to 60, a+b+c+d≧90 atomic % and C/Si<0.5 and H/C>0.5; or (3) SieNfCg:Hh where e has a value of 10 to 33, f has a value of 1 to 50, g has a value of 1 to 66, h has a value of 0.1 to 60, e+f+g+h≧90 atomic %; and C/Si<0.5 and H/C>0.5.
- 2. The integrated circuit as claimed in claim 1 wherein the sealing dielectric layer is SixCy:Hz where x has a value of 10 to 50 atomic percent, y has a value of 1 to 66 atomic percent, z has a value of 0.1 to 66 atomic percent, and x+y+z≧90 atomic %.
- 3. The integrated circuit as claimed in claim 2 wherein the sealing dielectric layer is SixCy:Hz where x has a value of 25 to 35 atomic percent, y has a value of 30 to 40 atomic percent, and z has a value of 25 to 35 atomic %.
- 4. The integrated circuit as claimed in claim 1 wherein the sealing dielectric layer is SiaObCc:Hd where a has a value of 10 to 33 atomic percent, b has a value of 1 to 40 atomic percent, c has a value of 1 to 66 atomic percent, d has a value of 0.1 to 60 atomic percent, a+b+c+d≧90 atomic % and C/Si<0.5 and H/C>0.5.
- 5. The integrated circuit as claimed in claim 4 wherein the sealing dielectric layer is SiaObCc:Hd where a has a value of 18 to 20 atomic percent, b has a value of 18 to 21 atomic percent, c has a value of 31 to 38 atomic percent, d has a value of 25 to 32 atomic percent.
- 6. The integrated circuit as claimed in claim 1 wherein the sealing dielectric layer is SieNfCg:Hh where e has a value of 10 to 33 atomic percent, f has a value of 1 to 50 atomic percent, g has a value of 1 to 66 atomic percent, h has a value of 0.1 to 60 atomic percent, e+f+g+h≧90 atomic %; and C/Si<0.5 and H/C>0.5.
- 7. The integrated circuit as claimed in claim 6 wherein the sealing dielectric layer is SieNfCg:Hh where e has a value of 18 to 20 atomic percent, f has a value of 1 to 50 atomic percent, g has a value of 31 to 38 atomic percent, h has a value of 25 to 32 atomic percent.
- 8. The integrated circuit as claimed in claim 1 wherein the porous dielectric layer has a total porosity of 10 to 60% and the connectivity between the pores is between 0 and 100%.
- 9. The integrated circuit as claimed in claim 1 where in the metal diffusion barrier is selected from Ta, TaN, Ti, TiN, TiSiN, WN, WCN or combinations thereof.
- 10. The integrated circuit as claimed in claim 1 wherein the metal wiring is produced from copper, aluminum, silver, gold, alloys, or superconductors.
- 11. The integrated circuit as claimed in claim 1 wherein the interconnect opening have sidewalls and wherein the sealing dielectric layer is on the sidewalls of the interconnect opening.
Parent Case Info
This application claims the benefit of U.S. Provisional Application No. 60/302,469 filed Jul. 2, 2001.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
5103285 |
Furumura et al. |
Apr 1992 |
A |
5818071 |
Loboda et al. |
Oct 1998 |
A |
6231989 |
Chung et al. |
May 2001 |
B1 |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/302469 |
Jul 2001 |
US |