Patent Application
20210351292
The present disclosure relates to a metal oxide semiconductor field effect transistor, in particular to a metal oxide semiconductor field effect transistor suitable for power supply and a method for manufacturing the same.
With the advancement of electronic technology and the trend of miniaturization of electronic products, increasingly more electronic components are produced by integrated circuit manufacturing process. However, many aspects need to be considered for integrated circuit type electronic components, such as issues of high voltage resistance, mutual interference or anti-noise, especially when being used in power supplies. Since the power supply needs to receive a high voltage input, and the high voltage may cause the integrated circuit type electronic components to burn out, therefore causing the power supply to malfunction, which is the main reason that the size of the power supply cannot be reduced in the application of integrated circuit type electronic components.
Metal oxide semiconductor field effect transistors are also commonly used in power supplies. Since the operation speed of the metal oxide semiconductor field effect transistors is quite fast and the voltage signal processing performance thereof is outstanding, the metal oxide semiconductor field effect transistors can be applied as power converters. In response to the miniaturization trend of the electronic products, the metal oxide semiconductor field effect transistors have also gradually moved towards integrated circuitization. However, when the power supply receives a high voltage input, the integrated circuit type metal oxide semiconductor field effect transistors may be unable to withstand the high voltage and burn out.
In response to the above-referenced technical inadequacies, the present disclosure provides a metal oxide semiconductor field effect transistor and a method for manufacturing the same.
In one aspect, the present disclosure provides a metal oxide semiconductor field effect transistor which includes a substrate structure, a plurality of doped regions, a plurality of trench oxide layers, a plurality of semiconductor layer structures, a dielectric layer structure, and a metal structure. The substrate structure includes a base layer and an epitaxial layer. The epitaxial layer is formed on the base layer, and the epitaxial layer has a plurality of trenches which are respectively recessed from a surface of the epitaxial layer away from the base layer and arranged at intervals from each other; in which a trench depth of each of the trenches is X1 micrometers, and X1 is a real number greater than zero. The plurality of doped regions are respectively formed at bottoms of the plurality of trenches and diffuse toward a portion of the epitaxial layer. The plurality of trench oxide layers are respectively formed on inner walls of the plurality of trenches, in which bottoms of the plurality of trench oxide layers respectively abut on the plurality of doped regions, and each of the trench oxide layers surrounds a groove; in which an oxide layer thickness of each of the trench oxide layers is X2 micrometers, and X2 is a real number greater than zero. In each of the trenches and the corresponding trench oxide layer, X1 and X2 conform to the following relationship: 0.05X1≤X2≤0.25X1. The plurality of semiconductor layer structures are respectively formed and filled in the plurality of grooves, so as to form a plurality of trench-type structures together with the plurality of trench oxide layers. The dielectric layer structure is formed and covered on the plurality of semiconductor layer structures and located above the epitaxial layer. The metal structure is formed on a surface of the dielectric layer structure away from the base layer, and the metal structure is electrically connected to at least one trench-type structure of the plurality of trench-type structures. The metal oxide semiconductor field effect transistor is suitable for receiving a working voltage between 50 volts and 800 volts to pass therethrough.
In another aspect, the present disclosure provides a method for manufacturing a metal oxide semiconductor field effect transistor, which includes: providing a substrate structure which includes a base layer and an epitaxial layer formed on the base layer; forming a plurality of trenches recessed in the epitaxial layer, respectively, according to a preset trench depth, in which the plurality of trenches are respectively recessed from a surface of the epitaxial layer away from the base layer and arranged at intervals from each other, the preset trench depth is defined as X1 micrometers, and X1 is a real number greater than zero; forming a plurality of doped regions at bottoms of the plurality of trenches, respectively, in which the plurality of doped regions are respectively diffused from the bottoms of the plurality of trenches toward a portion of the epitaxial layer; forming a plurality of trench oxide layers on inner walls of the plurality of trenches, respectively, according to a preset oxide layer thickness, in which bottoms of the plurality of trench oxide layers respectively abut on the plurality of doped regions, and each of the trench oxide layers surrounds a groove, in which the preset oxide layer thickness is defined as X2 micrometers, and X2 is a real number greater than zero; in which X1 and X2 conform to the following relationship: 0.05X1≤X2≤0.25X1; forming a plurality of semiconductor layer structures in the plurality of grooves, respectively, so that the plurality of semiconductor layer structures and the plurality of trench oxide layers together form a plurality of trench-type structures, respectively; forming a dielectric layer structure on the plurality of semiconductor layer structures such that the dielectric layer structure covers the plurality of semiconductor layer structures, and the dielectric layer structure is located above the epitaxial layer; and forming a metal structure on a surface of the dielectric layer structure away from the base layer to form the metal oxide semiconductor field effect transistor, in which the metal structure is electrically connected to at least one trench-type structure of the plurality of trench-type structures.
Therefore, an advantage of the present disclosure is that the technical features of “a trench depth of each of the trenches is X1 micrometers, and X1 is a real number greater than zero” and “an oxide layer thickness of each of the trench oxide layers is X2 micrometers, and X2 is a real number greater than zero; in which in each of the trenches and the corresponding trench oxide layer, X1 and X2 conform to the following relationship: 0.05X1≤X2≤0.25X1” can enable the finally produced metal oxide semiconductor field effect transistor to withstand a higher working voltage without burnout, thereby improving the reliability of the device.
Further, another advantage of the present disclosure is that the method for manufacturing the metal oxide semiconductor field effect transistor can adjust the trench depth of the trench and correspondingly adjust the thickness of the trench oxide layer, so that the finally produced metal oxide semiconductor field effect transistor can be adapted to different operating voltage specifications.
These and other aspects of the present disclosure will become apparent from the following description of the embodiment taken in conjunction with the following drawings and their captions, although variations and modifications therein may be affected without departing from the spirit and scope of the novel concepts of the disclosure.
The present disclosure will become more fully understood from the following detailed description and accompanying drawings.
The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Like numbers in the drawings indicate like components throughout the views. As used in the description herein and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of “a”, “an”, and “the” includes plural reference, and the meaning of “in” includes “in” and “on”. Titles or subtitles can be used herein for the convenience of a reader, which shall have no influence on the scope of the present disclosure.
The terms used herein generally have their ordinary meanings in the art. In the case of conflict, the present document, including any definitions given herein, will prevail. The same thing can be expressed in more than one way. Alternative language and synonyms can be used for any term(s) discussed herein, and no special significance is to be placed upon whether a term is elaborated or discussed herein. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms is illustrative only, and in no way limits the scope and meaning of the present disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given herein. Numbering terms such as “first”, “second” or “third” can be used to describe various components, signals or the like, which are for distinguishing one component/signal from another one only, and are not intended to, nor should be construed to impose any substantive limitations on the components, signals or the like.
Referring to
In the present embodiment, the method for manufacturing the metal oxide semiconductor field effect transistor is firstly described below. For ease of understanding, a unit region of the metal oxide semiconductor field effect transistor is taken as an example, and a cross-sectional view of the unit region is used for explanation. The diagram corresponding to each step can be referred to, as can be referred to the diagrams of other steps, if necessary. The specific steps of the method for manufacturing the metal oxide semiconductor field effect transistor are described below.
Referring to
Further, a material of the base layer 11 may be, for example, an N-type doped semiconductor or a P-type doped semiconductor. The epitaxial layer 12 may be formed on the base layer 11 by an epitaxial process, and a conductive type of the epitaxial layer 12 may be the same as a conductive type of the base layer 11 (i.e. N-type doping or P-type doping). In the present embodiment, the base layer 11 is an N-type doped semiconductor, and the epitaxial layer 12 is also an N-type doped semiconductor. In addition, a doping concentration of the base layer 11 is greater than that of the epitaxial layer 12, but the present disclosure is not limited thereto.
Further referring to
The conductive type of the base layer 11 is the same as the conductive type of the first epitaxial layer 121, and is also the same as the conductive type of the second epitaxial layer 122. That is, in the present embodiment, the conductive types of the base layer 11, the first epitaxial layer 121, and the second epitaxial layer 122 are all N-type doping, but the present disclosure is not limited thereto.
The doping concentration of the base layer 11 is greater than that of the first epitaxial layer 121, and is also greater than that of the second epitaxial layer 122.
In an embodiment of the present disclosure, the doping concentration of the base layer 11 is approximately between 1018/cm3 and 1019/cm3, the doping concentration of the first epitaxial layer 121 is approximately between 1014/cm3 and 1016/cm3, and the doping concentration of the second epitaxial layer 122 is also approximately between 1014/cm3 and 1016/cm3. Furthermore, the doping concentration of the first epitaxial layer 121 is different from the doping concentration of the second epitaxial layer 122, and the doping concentration of each of the first epitaxial layer 121 and the second epitaxial layer 122 is uniformly distributed.
Referring to
In addition, the plurality of trenches 13 are respectively recessed from a surface of the epitaxial layer 12 away from the base layer 11 and arranged at intervals from each other. The preset trench depth is defined as X1 micrometers, and X1 is a real number greater than zero. In the present embodiment, X1 is a real number that is not less than 4 and not greater than 16.
Accordingly, each of the trenches 13 has a trench depth of X1 micrometer.
Further, the bottoms of the plurality of trenches 13 are not in contact with the base layer 11 and are spaced apart from the base layer 11 by a distance. In other words, the plurality of trenches 13 are recessed from the top surface of the base structure 1 and not in contact with the base layer 11 of the base structure 1.
More specifically, the first epitaxial layer 121 and the second epitaxial layer 122 have an interface 123 formed therebetween. The interface 123 is substantially located at (or aligned with) the bottoms of the plurality of trenches 13, and the interface 123 is extendingly connected between a plurality of doped regions 2 as shown in
It should be noted that
In addition, it should be noted that the plurality of trenches 13 are described with respect to the trenches 13 at different locations in the epitaxial layer 12 from a sectional view angle. When viewing the MOSFET as a whole, the trenches 13 may be in communication with each other or be separate from each other, and the present disclosure is not limited thereto.
Referring to
That is, the bottom of each of the trenches 13 is formed with a doped region 2. Each of the doped regions 2 diffuses from the bottom of the corresponding trench 13 toward a portion of the epitaxial layer 12. Accordingly, each of the doped regions 2 surrounds the periphery of the bottom of the corresponding trench 13. In addition, in the present embodiment, each of the doped regions 2 only slightly diffuses from the bottom of the corresponding trench 13 toward the epitaxial layer 12 and is presented as a half-moon structure. Each of the doped regions 2 is not in contact with the base layer 11 and is spaced apart from the base layer 11 by a distance. It is worth mentioning that, in the present embodiment, each of the doped regions 2 is partially located in the first epitaxial layer 121 and partially located in the second epitaxial layer 122.
Furthermore, in the present embodiment, the conductive types of the plurality of doped regions 2 are different from the conductive types of the base layer 11 and the epitaxial layer 12. That is, the plurality of doped regions 2 in the present embodiment are P-type doped semiconductors. The implanted ion type of the doped regions 2 may be, for example, boron ions (B+).
In addition, it is worth mentioning that the plurality of doped regions 2 (P-type doped semiconductors) and the epitaxial layer 12 (N-type doped semiconductor) can be formed together as a P-N junction diode.
In an embodiment of the present disclosure, a doping concentration of each of the doped regions 2 is approximately between 1015/cm3 and 1017/cm3.
It is worth mentioning that the doping concentrations of the first epitaxial layer 121, the second epitaxial layer 122, and the plurality of doped regions 2 need to be low doping concentrations (i.e. not greater than 1017/cm3) to reduce the conductivity of the components. Accordingly, the finally produced metal oxide semiconductor field effect transistor 100 can withstand a higher operating voltage. If the doping concentrations of the first epitaxial layer 121, the second epitaxial layer 122, and the plurality of doped regions 2 are high doping concentrations (i.e. greater than 1018/cm3), the finally produced metal oxide semiconductor field effect transistor 100 may be burned out due to excessive working voltage.
Referring to
More specifically, the oxide layer structure 3 includes a plurality of trench oxide layers 31 and a cover oxide layer 32. The plurality of trench oxide layers 31 are respectively formed on the inner walls of the plurality of trenches 13, and the bottoms of the plurality of trench oxide layers 31 respectively abut on the plurality of doped regions 2. Each of the trench oxide layers 31 surrounds a groove 33. Furthermore, the cover oxide layer 32 is formed on the surface of the epitaxial layer 12 away from the base layer 11 (i.e. the top surface of the epitaxial layer 12), and the cover oxide layer 32 is extendingly connected between the plurality of trench oxide layers 31. In addition, the material of the oxide layer structure 3 may be made of, for example, a silicon compound or other dielectric materials. For example, the aforementioned silicon compound may be, for example, silicon dioxide or silicate, and is preferably silicon dioxide, but the present disclosure is not limited thereto.
The preset oxide layer thickness is defined as X2 micrometers, and X2 is a real number greater than zero. In the present embodiment, X2 is a real number that is not less than 0.5 and not greater than 1.5, but the present disclosure is not limited thereto. Accordingly, each of the trench oxide layers 31 has an oxide layer thickness of X2 micrometers.
Furthermore, the preset trench depth X1 and the preset oxide layer thickness X2 conform to the following relationship: 0.05X1≤X2≤0.25X1.
According to the above configuration, since the trench depth X1 of each of the trenches 13 is between 4 micrometers and 16 micrometers, the oxide layer thickness X2 of each of the trench oxide layers 31 is between 0.5 micrometers (5 kÅ) and 1.5 micrometers (15 kÅ), and the material of each of the trench oxide layers 31 is silicon dioxide or silicate with high resistance and low conductivity, the finally produced metal oxide semiconductor field effect transistor 100 of the present embodiment is suitable for receiving a working voltage between 50 volts and 800 volts to pass therethrough, and the working voltage is preferably between 200 volts and 700 volts.
It is worth mentioning that the method for manufacturing the metal oxide semiconductor field effect transistor of the present embodiment can adjust a value range of the preset trench depth X1 according to a predetermined working voltage, and can adjust a value range of the preset oxide layer thickness X2 according to the value range of the preset trench depth X1. Accordingly, the finally produced metal oxide semiconductor field effect transistor 100 will not be burned out due to an excessively high voltage, and the reliability of the finally produced metal oxide semiconductor field effect transistor 100 can be improved.
More specifically, in the present embodiment, the value range of the preset trench depth X1 and the value range of the preset oxide layer thickness X2 meet only one of the following conditions:
i) if the preset trench depth X1 is between 4 micrometers and 7 micrometers, the preset oxide layer thickness X2 is between 0.5 micrometers (5 kÅ) and 0.9 micrometers (9 kÅ), and X1 and X2 conform to the following relationship: 0.071X1≤X2≤0.225X1, so that the finally produced metal oxide semiconductor field effect transistor 100 is suitable for receiving a working voltage between 75 volts and 275 volts to pass therethrough, and the working voltage is preferably between 100 volts and 250 volts.
ii) if the preset trench depth X1 is between 7 micrometers and 16 micrometers, the preset oxide layer thickness X2 is between 1.2 micrometers (12 kÅ) and 1.5 micrometers (15 kÅ), and X1 and X2 conform to the following relationship: 0.075X1≤X2≤0.220X1, so that the finally produced metal oxide semiconductor field effect transistor 100 is suitable for receiving a working voltage between 275 volts and 800 volts to pass therethrough, and the working voltage is preferably between 300 volts and 700 volts.
If the value range of the preset trench depth X1 and the value range of the preset oxide layer thickness X2 do not meet one of the above conditions, the finally produced metal oxide semiconductor field effect transistor 100 will not be suitable for receiving the corresponding working voltage to pass therethrough, which may cause burnout or poor reliability. For example, if the oxide layer thickness X2 of the trench oxide layer 31 is too thin, the finally produced metal oxide semiconductor field effect transistor 100 will not be able to withstand a high voltage due to the reduced resistance value, and the transistor 100 may be burned out.
Referring to
Further, the plurality of semiconductor layer structures 4 are respectively filled in the grooves 33 that are surrounded by the plurality of trench oxide layers 31. The plurality of semiconductor layer structures 4 may be subjected to an etch-back step, so that a height of the exposed outer surfaces of the semiconductor layer structures 4 (i.e. the top surfaces of the semiconductor layer structures 4 in
It is worth mentioning that, in an embodiment of the present disclosure, the plurality of trenches 13 may be defined as deep trenches. The epitaxial layer 12 may further have a plurality of shallow trenches (not shown) formed between the plurality of deep trenches 13. Moreover, the trench depths of the plurality of shallow trenches are all smaller than the trench depths of the plurality of deep trenches. The plurality of shallow trenches may be used to form a plurality of trench-type gate structures, and the plurality of deep trenches may be used to form a plurality of trench-type source structures. In addition, a drain wire can be connected below the substrate structure 1, but the present disclosure is not limited thereto.
Referring to
In addition, the outer surface of the dielectric layer structure 5 may be planarized by a chemical mechanical polishing (CMP) process, but the present disclosure is not limited thereto.
Referring to
Further, the metal structure 6 includes a conductive portion 61 and two contact plugs 62 integrally formed with the conductive portion 61. The conductive portion 61 is formed on a surface of the dielectric layer structure 5 away from the base layer 11. The two contact plugs 62 are disposed at a distance from each other. The two contact plugs 62 respectively penetrate through the dielectric layer structure 5. Accordingly, the conductive portion 61 can be electrically connected to two adjacent trench-type structures T of the plurality of trench-type structures T through the two contact plugs 62, respectively. In addition, a width of each of the contact plugs 62 is less than a width of the corresponding trench-type structure T and a width of the corresponding trench 13.
More specifically, the two contact plugs 62 are respectively formed through the dielectric layer structure 5, and the two contact plugs 62 partially extend into the semiconductor layer structures 4 of the two adjacent trench-type structures T, respectively. Accordingly, the conductive portion 61 can be electrically connected to the semiconductor layer structures 4 of the two adjacent trench-type structures T through the two contact plugs 62 (as shown in
Furthermore, in the present embodiment, the conductive portion 61 covers only a part of the outer surface of the dielectric layer structure 5 and the other part of the outer surface of the dielectric layer structure 5 is exposed to the outside.
It is worth mentioning that before the metal structure 6 is formed, the manufacturing method of the present embodiment further includes: forming two contact grooves (not labeled in the drawings) recessed in the dielectric layer structure 5 by means of etching to provide the two aforementioned contact plugs 62 to be respectively formed therein.
After implementing the above steps S110 to S170, the metal oxide semiconductor field effect transistor 100 (also referred to as a trench-type power element) shown in
Furthermore, it is worth mentioning that the above-mentioned metal structure 6 partially penetrates the dielectric layer structure 5 to be in direct contact and electrically connected to at least one of the plurality of trench-type structures T, but the present disclosure is not limited thereto. For example, the metal structure 6 may not penetrate through the dielectric layer structure 5, and may be electrically connected to at least one of the plurality of trench-type structures T via an external wire. Accordingly, the above-mentioned metal structure 6 may not directly contact any of the trench-type structures T.
The method for manufacturing the metal oxide semiconductor field effect transistor according to the embodiment of the present disclosure has been described above. The specific structure of the metal oxide semiconductor field effect transistor 100 of the present embodiment will be described below. It should be noted that although the metal oxide semiconductor field effect transistor 100 of the present embodiment is manufactured by the above-mentioned manufacturing method, the present disclosure is not limited thereto. That is, the metal oxide semiconductor field effect transistor of the present disclosure may be produced by other methods for manufacturing the transistor.
As shown in
The substrate structure 1 includes a base layer 11 and an epitaxial layer 12. The epitaxial layer 12 is formed on the base layer 11. The epitaxial layer 12 has a plurality of trenches 13, and the plurality of trenches 13 are respectively recessed from a surface of the epitaxial layer 12 away from the base layer 11 and arranged at intervals from each other, in which a trench depth of each of the trenches is X1 micrometers, and X1 is a real number greater than zero.
The plurality of doped regions 2 are respectively formed at bottoms of the plurality of trenches 13, and the plurality of doped regions 2 diffuse toward a portion of the epitaxial layer 12.
The oxide layer structure 3 includes a plurality of trench oxide layers 31 and a cover oxide layer 32. The plurality of trench oxide layers 31 are respectively formed on the inner walls of the plurality of trenches 13, and the bottoms of the plurality of trench oxide layers 31 respectively abut on the plurality of doped regions 2. Each of the trench oxide layers 31 surrounds a groove 33. Furthermore, the cover oxide layer 32 is formed on the surface of the epitaxial layer 12 away from the base layer 11, and the cover oxide layer 32 is extendingly connected between the plurality of trench oxide layers 31. Each of the trench oxide layers 31 has an oxide layer thickness of X2 micrometers, and X2 is a real number greater than zero. In each of the trenches 13 and the corresponding trench oxide layer 31, X1 and X2 conform to the following relationship: 0.05X1≤X2≤0.25X1.
The plurality of semiconductor layer structures 4 are respectively formed and filled in the plurality of grooves 33, and the plurality of semiconductor layer structures 4 and the plurality of trench oxide layers 31 together form a plurality of trench-type structures T.
The dielectric layer structure 5 is formed and covered on the oxide layer structure 3 and the plurality of semiconductor layer structures 4.
The metal structure 6 is formed on a surface of the dielectric layer structure 5 away from the base layer 11. The metal structure 6 partially penetrates through the dielectric layer structure 5, so that the metal structure 6 is electrically connected to at least one of the plurality of trench-type structures T, but the present disclosure is not limited thereto. For example, the metal structure 6 may not penetrate through the dielectric layer structure 5, and may be electrically connected to at least one of the plurality of trench-type structures T via an external wire.
According to the above configuration, the metal oxide semiconductor field effect transistor 100 of the present embodiment is suitable for receiving a working voltage between 50 volts and 800 volts to pass therethrough, and the working voltage is preferably between 200 volts and 700 volts.
It is worth mentioning that the metal oxide semiconductor field effect transistor of the present embodiment has a suitable trench depth X1 according to a required working voltage, and has a suitable oxide layer thickness X2 according to the trench depth X1. Accordingly, the metal oxide semiconductor field effect transistor 100 is suitable for the required working voltage, and the metal oxide semiconductor field effect transistor 100 will not be burned out due to an excessively high voltage.
In an embodiment of the present disclosure, the trench depth X1 of the trench 13 is between 4 micrometers and 6 micrometers, the oxide layer thickness X2 of the trench oxide layer is between 0.5 micrometers and 0.6 micrometers, and X1 and X2 conform to the following relationship: 0.08 X1≤X2≤0.15X1.
Accordingly, the metal oxide semiconductor field effect transistor 100 is suitable for receiving the working voltage between 75 volts and 125 volts to pass therethrough.
In an embodiment of the present disclosure, the trench depth X1 of the trench 13 is between 5 micrometers and 7 micrometers, the oxide layer thickness X2 of the trench oxide layer is between 0.7 micrometers and 0.9 micrometers, and X1 and X2 conform to the following relationship: 0.10X1≤X2≤0.18X1.
Accordingly, the metal oxide semiconductor field effect transistor 100 is suitable for receiving the working voltage between 125 volts and 275 volts to pass therethrough.
In an embodiment of the present disclosure, the trench depth X1 of the trench 13 is between 7 micrometers and 16 micrometers, the oxide layer thickness X2 of the trench oxide layer is between 1.2 micrometers and 1.5 micrometers, and X1 and X2 conform to the following relationship: 0.075X1≤X2≤0.220X1.
Accordingly, the metal oxide semiconductor field effect transistor 100 is suitable for receiving the working voltage between 275 volts and 800 volts to pass therethrough.
It is worth mentioning that, as described in the above embodiment, the number of the plurality of trenches 13 is five, and the number of the plurality of trench-type structures T is also five, but the present disclosure is not limited thereto. The number of the plurality of trenches 13 and the number of the trench-type structures T can be adjusted according to design requirements.
In conclusion, an advantage of the present embodiment is that the technical features of “a trench depth of each of the trenches is X1 micrometers, and X1 is a real number greater than zero” and “an oxide layer thickness of each of the trench oxide layers is X2 micrometers, and X2 is a real number greater than zero; in which in each of the trenches and the corresponding trench oxide layer, X1 and X2 conform to the following relationship: 0.05X1≤X2≤0.25X1” can enable the finally produced metal oxide semiconductor field effect transistor to withstand a higher working voltage without burnout, thereby improving the reliability of the device.
Further, another advantage of the present embodiment is that the method for manufacturing the metal oxide semiconductor field effect transistor can adjust the trench depth of the trench and correspondingly adjust the thickness of the trench oxide layer, so that the finally produced metal oxide semiconductor field effect transistor can be adapted to different operating voltage specifications.
In addition, in terms of wafer design, since the metal oxide semiconductor field effect transistor of the present embodiment can withstand a higher operating voltage without the need to connect other metal oxide semiconductor field effect transistor in series, the area occupied by the metal oxide semiconductor field effect transistor on the wafer can be greatly reduced, and other electronic components can be designed on the wafer to diversify the functions provided by the wafer.
The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.
The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.
