1. Field of the Invention
The present invention relates to a metal-oxide-semiconductor transistor device and a method for making the same, and more particularly, to a metal-oxide-semiconductor transistor device having low drain-source on-state resistance and a method for making the same.
2. Description of the Prior Art
A power metal-oxide-semiconductor field effect transistor (Power MOSFET) is widely used in power electronic applications, such as a power supply, an industrial instrument, a lamp electronic ballast, an electronic ignition system, a computer motherboard, a battery for a portable electronic device, and a communications equipment. The power MOSFET has many different types of structures and one of these types is a vertical double diffused metal-oxide-semiconductor (VDMOS) transistor.
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On the other hand, a parasitic Junction field effect transistor (parasitic JFET) the MOSFET device 10 grows when the depth of the well region 108 is getting larger so that a drain-source on-state resistance (Rdson) in the MOSFET device 10 increases. As a result, the efficiency of the MOSFET device 10 is reduced.
It is therefore a primary objective of the claimed invention to provide a metal-oxide-semiconductor transistor device and method for making the same.
The present invention discloses a metal-oxide-semiconductor (MOS) transistor device comprising a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, an oxide layer formed on the epitaxial layer, a gate structure formed on the oxide layer comprising a conductive layer having a gap on the top of the sidewall of the conductive layer and a spacer formed on the gap, and a shallow junction well region formed on the two lateral sides of the gate structure comprising a source region and a heavy body region.
The present invention further discloses a method for fabricating a metal-oxide-semiconductor (MOS) transistor device comprising providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, forming an oxide layer on the epitaxial layer, forming a conductive layer on the oxide layer, forming a first opening on the conductive layer, performing a first ion implantation process on the first opening for forming a shallow junction well region, depositing an oxide layer and performing an etching back process for forming a spacer on the sidewall of the first opening, performing an etching process with the spacer as a mask for forming a gate structure, forming a source region and a heavy body region in the shallow junction well region on the two lateral sides of the gate structure, and performing a depositing process and an etching process for forming a dielectric layer and a metal layer for forming the MOS transistor device.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
It is known from the prior art that the depth of the well region of a MOSFET device is related to a drain-source on-state resistance (Rdson) in the MOSFET device. The present invention is based on the fact that if the depth of the well region of a MOSFET device is minimized and the channel length of the MOSFET device is fixed at the same time, the MOSFET device shall have a low Rdson.
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Note that, the conductive layer 760 is formed according to a first etching process and a second etching process. At the beginning, the conductive layer 760 is a polysilicon layer formed on the oxide layer 704. The first etching process is utilized for etching a portion of the polysilicon layer for forming a first opening. The first opening is utilized for performing an ion implantation process for forming the well region 708. Note that, the first etching process only etches a portion of the polysilicon layer so that the etching depth does not reach the top of the oxide layer 704 yet. Next, the spacer 762 is formed according to a deposition process and an etching back process. Furthermore, the second etching process is utilized for etching the remaining polysilicon layer to the top of the oxide layer 704 via the spacer 762 as a mask for forming a second opening. The second opening is utilized for performing an ion implantation process for forming the source region and the heavy body region in the well region 708. In addition, the semiconductor substrate 700 is a silicon substrate. The oxide layer 704 is made of silicon oxide and the conductive layer 760 is made of polysilicon.
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Step 800: Provide a semiconductor substrate.
Step 802: Form an epitaxial layer on the semiconductor substrate.
Step 804: Form an oxide layer on the epitaxial layer.
Step 806: Form a conductive layer on the oxide layer.
Step 808: Form a first opening on the conductive layer.
Step 810: Perform a first ion implantation process on the first opening for forming a well region.
Step 812: Deposit an oxide layer and perform an etching back process for forming a spacer on the sidewall of the first opening.
Step 814: Perform an etching process with the spacer as a mask for forming a gate structure.
Step 816: Form a source region and a heavy body region in the well region on the two lateral sides of the gate structure.
Step 818: Perform a deposition process and an etching process for forming a dielectric layer and a metal layer for forming the MOSFET device.
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Note that, the MOSFET device 70 fabricated according to the process 80 is a MOSFET device having low Rdson. Please refer to
Or, if the distance between of the contact window and the gate stays the same in the MOSFET device 10 and 70, the upper opening of the contact window of the MOSFET device 70 is larger than that of the MOSFET device 10 because of the gaps on the gate structure 706. As a result, the step coverage of the MOSFET device 70 is better than that of the MOSFET device 10, so that the MOSFET device 70 can use a smaller contact window. From the above, the distance S′ between two gate structures 706 is smaller than the distance S between two gate structures 106. Therefore, the cell of the MOSFET device 70 can be smaller. In a word, the MOSFET device 70 is fabricated according to 2-step etching processes and particularly, the gate structures 706 is formed via the spacer 762 as the mask so that the channel length H′ can be identical to the channel length H even if the depth D′ of the well region 708 is shallower than the depth D of the well region 108. That is, the well region 708 can be a shallow junction well region so as to save time cost for a drive-in process and save production cost.
From the above, the MOSFET device 70 is fabricated according to 2-step etching processes and the gate structure 706 is formed via the spacer 762 as the mask so that the cell of the MOSFET device 70 can be smaller and the well region 708 can be a shallow junction well region. Therefore, Rdson of a parasitic junction field effect transistor of the MOSFET device 70 is minimized so that Rdson of the MOSFET device 70 is minimized. Compared with the MOSFET device 10, the MOSFET device 70 has lower Rdson so that the efficiency of the MOSFET device 70 is enhanced.
Note that the MOSFET device 70 and the process 80 are embodiments of the present invention, and those skilled in the art can make alterations and modifications accordingly. For example, the present invention further provides a process 160 for improving the problem that it is difficult to control the etching depth of the conductive layer 760 when forming the first opening in the step 808 of the process 80. Please refer to
Step 1600: Provide a semiconductor substrate.
Step 1602: Form an epitaxial layer on the semiconductor substrate.
Step 1604: Form a first oxide layer on the epitaxial layer.
Step 1606: Form a first conductive layer on the first oxide layer.
Step 1608: Form a second oxide layer on the first conductive layer.
Step 1610: Form a first opening on the second oxide layer.
Step 1612: Form a second conductive layer on the second oxide layer.
Step 1614: Form a second opening on the second conductive layer.
Step 1616: Perform an ion implantation process on the second opening for forming a well region.
Step 1618: Deposit an oxide layer and perform an etching back process for forming a spacer on the sidewall of the second opening.
Step 1620: Perform an etching process with the spacer as a mask for forming a gate structure.
Step 1622: Form a source region and a heavy body region in the well region on the two lateral sides of the gate structure.
Step 1624: Perform a deposition process and an etching process for forming a dielectric layer and a metal layer for forming the MOSFET device.
Note that, in the step 1610, forming the first opening on the second oxide layer means etching a portion of the second oxide layer and reserving the remaining second oxide layer for forming the first opening. In the step 1614, forming the second opening on the second conductive layer means etching a portion of the second conductive layer to the top of the remaining second oxide layer and then etching the remaining second oxide layer. Therefore, etching depth is easier to control in the step 1610 to the step 1614 than in the step 808 of the process 80. Those steps after the step 1614 are similar to the process 80. Please refer to
The cross-section diagram of the MOSFET device 90 is shown in
On the other hand, in the present invention, the material of the oxide layer and the conductive layer and an order of corresponding fabrication steps such as a deposition process or an etching process can be modified according to requirements. Please refer to
In conclusion, the MOSFET device of the present invention is fabricated according to 2-step etching processes and the gate structure of the MOSFET device is formed via the spacer as the mask, so that the cell of the MOSFET device can be smaller and the well region can be a shallow junction well region. As a result, the MOSFET device of the present invention has low Rdson so that the efficiency of the MOSFET device is enhanced.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Number | Date | Country | Kind |
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097106097 | Feb 2008 | TW | national |