Claims
- 1. A method for improving step height performance in a CMP process for polishing semiconductor wafers, the method comprising:
mounting a polishing pad onto a semiconductor wafer polisher and moving the polishing surface; reducing a roughness of the polishing surface; scanning a length of a polishing surface of the polishing pad and obtaining polishing surface scan data; determining a polishing surface flatness from the polishing surface scan data; and discontinuing roughness reduction of the polishing surface when the determined polishing surface flatness reaches a desired polishing surface flatness.
- 2. The method of claim 1, wherein reducing the roughness of the polishing surface comprises pressing a pad pre-conditioning member against a portion of the polishing pad surface configured to receive a semiconductor wafer.
- 3. The method of claim 1, wherein reducing the roughness of the polishing surface comprises pressing a pad pre-conditioning member against a portion of the polishing pad surface configured to receive a semiconductor wafer while the polishing surface is moving
- 4. The method of claim 2, wherein the pad pre-conditioning member comprises a semiconductor wafer.
- 5. The method of claim 4, wherein the semiconductor wafer comprises a TEOS oxide layer.
- 6. The method of claim 2, wherein the pad pre-conditioning member comprises a plurality of discrete elements.
- 7. The method of claim 1, wherein the polishing surface scan data comprises data containing peak-to-valley distance measurements for points along the length of polishing surface scanned, and wherein determining the polishing surface flatness from the polishing surface scan data comprises averaging peak-to-valley distance measurements and obtaining a roughness average.
- 8. The method of claim 7, wherein the desired polishing surface flatness comprises a roughness average of less than a roughness average of a polishing surface of an unused polishing pad.
- 9. The method of claim 1, wherein the polishing surface scan data comprises data containing polishing surface height measurements for points along the length of polishing surface scanned, and wherein determining the polishing surface flatness from the polishing surface scan data comprises determining a pad flatness ratio for the polishing surface of the polishing pad, wherein the pad flatness ratio is determined according to the relationship:
- 10. The method of claim 9, wherein the desired polishing surface flatness comprises a pad flatness ratio of less than a pad flatness ratio of an unused polishing pad.
- 11. The method of claim 2, wherein the pad pre-conditioning member comprises a non-abrasive material.
- 12. The method of claim 1, wherein reducing the roughness of the polishing surface comprises:
(a) applying pressure against the polishing surface with a non-abrasive pad pre-conditioning member; (b) moving the polishing surface under the preconditioning member; (c) applying a slurry to the polishing surface; and (d) maintaining steps (a)-(c) while keeping the polishing surface free of any abrasive pad conditioning device.
- 13. A method for pre-conditioning a polishing pad to improve planarity of semiconductor wafers subsequently processed in a CMP process using the polishing pad, the method comprising:
moving a polishing pad free of fixed abrasive particles; and flattening a polishing surface of the polishing pad with a pre-conditioning member.
- 14. The method of claim 13, further comprising applying a fluid to the polishing pad while flattening the polishing surface.
- 15. The method of claim 14, wherein the pre-conditioning member comprises a semiconductor material.
- 16. The method of claim 13, wherein the pre-conditioning member comprises sandpaper.
- 17. The method of claim 13, wherein the polishing pad is dry and no fluid is added to the polishing pad when flattening the polishing surface.
- 18. The method of claim 13, further comprising measuring a flatness criteria of the polishing surface after flattening the polishing pad, polishing a semiconductor wafer with the polishing pad, measuring a planarity of the semiconductor wafer after polishing the semiconductor wafer with the polishing pad, and flattening at least one additional polishing pad until the measured flatness criteria is achieved if the planarity of the semiconductor wafer is a desired planarity.
- 19. The method of claim 13, further comprising measuring a flatness criteria of the polishing pad.
- 20. The method of claim 19, wherein measuring the flatness criteria comprises measuring a temperature of the polishing surface while flattening the polishing surface.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. application Ser. No. 10/039,749, filed Oct. 26, 2001, pending, which is hereby incorporated by reference herein.
Continuations (1)
|
Number |
Date |
Country |
Parent |
10039749 |
Oct 2001 |
US |
Child |
10678727 |
Oct 2003 |
US |