Patent Application
20070102399
The present invention relates to a semiconductor device manufacturing method including a plasma etching process for performing a plasma etching on a substrate to be processed which at least has a silicon nitride film, an antireflection film and a photo resist with openings formed on the substrate in this order from the lower side, to thereby form in the substrate trenches corresponding to the openings of the resist film for device isolation; and also relates to a semiconductor device manufacturing apparatus, a control program, and a computer-readable storage medium storing the control program to be used therefor.
In the field of manufacture of semiconductor devices, a shallow trench isolation (STI) structure is known for device isolation. In a manufacturing process for semiconductor device employing the STI structure, trenches are formed in a silicon substrate by plasma etching.
The plasma etching process for forming the trenches involves the steps of performing main etching for etching, for example, a silicon oxide film and a silicon nitride film formed on a silicon substrate by using a photo resist as a mask and CF4 as an etching gas; performing overetching by using a gaseous mixture of NF3 and NH3 as an etching gas; and subsequently performing etching on the silicon substrate by using a gaseous mixture of HBr and oxygen (See Japanese Patent Laid-open Application No. 2000-299374).
Further, there is also known a technique for forming an antireflection film between the photo resist and the silicon nitride film. In case of using the antireflection film, a step of performing plasma etching on the antireflection film is performed prior to the plasma etching of the silicon nitride film and the like. For the plasma etching of the antireflection film, a gaseous mixture of CF4, CH2F2 and O2 is employed as an etching gas, for example.
As described, when forming trenches in the silicon substrate for device isolation of a STI structure, individual etching gases are used for the respective steps of etching the uppermost antireflection film by using the photo resist as a mask, etching the silicon nitride film and the like through the main etching process and the overetching process, and finally etching the silicon substrate. Thus, etching gases need to be changed for each processing step, which results in an increase of processing time and a reduction of throughput.
It is, therefore, an object of the present invention to provide: a semiconductor device manufacturing method capable of reducing a processing time required to conduct a plasma etching for forming a trench for device isolation, while enhancing throughput and productivity; a semiconductor device manufacturing apparatus; a control program; and a computer-readable storage medium storing the control program.
In accordance with the present invention, there is provided a method for manufacturing a semiconductor device including a plasma etching process for performing a plasma etching on a substrate to be processed at least having a silicon nitride film, an antireflection film and a photo resist with an opening laminated on a silicon substrate in said order from the lower side, to thereby form in the silicon substrate a trench corresponding to the opening, wherein the etchings of the antireflection film, the silicon nitride film and the silicon substrate are successively performed by using an etching gas at least containing an NF3 gas, an SF6 gas or a gaseous mixture of NF3 and SF6.
Preferably, the etching gas further contains an additive gas, the additive gas being a CF4 gas, a rare gas or a gaseous mixture of CF4 and a rare gas.
Preferably, the additive gas further contains an oxygen gas.
Preferably, the ratio of a flow rate of the additive gas to a flow rate of the NF3 gas, the SF6 gas or the gaseous mixture of NF3 and SF6 (a flow rate of the additive gas/a flow rate of the NF3 gas, the SF6 gas or the gaseous mixture of NF3 and SF6) is set to be not smaller than 1.
Preferably, a silicon oxide film is formed between the silicon substrate and the silicon nitride film, and the silicon oxide film is also etched through the plasma etching process.
Preferably, the plasma etching process is performed in a processing chamber having therein a lower electrode for mounting thereon the substrate to be processed and an upper electrode facing the lower electrode by applying high frequency powers between the upper electrode and the lower electrode.
Preferably, the high frequency powers include a first high frequency power applied to the upper electrode and a second high frequency power applied to the lower electrode, and the second high frequency power is of a frequency lower than that of the first high frequency power.
Further, in accordance with the present invention, there is provided an apparatus for manufacturing a semiconductor device including: a processing chamber for accommodating a substrate to be processed; an etching gas supply unit for supplying an etching gas into the processing chamber; a plasma generating unit for converting the etching gas into plasma to thereby plasma-etch the substrate to be processed; and a control unit for controlling the methods described above.
Moreover, in accordance with the present invention, there is provided a control program, executed on a computer for controlling a semiconductor device manufacturing apparatus to perform the methods noted above.
In addition, in accordance with the present invention, there is provided a computer-readable storage medium for storing therein a computer-executable control program, wherein the control program controls, when executed, a plasma processing apparatus to perform the method described above.
In accordance with the preferred embodiment of the present invention, the whole processing time required for performing a plasma etching to form trenches for device isolation can be reduced comparing to the prior art, while enhancing throughput and productivity.
The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
A plasma processing apparatus 1 is configured as a capacitively coupled parallel plate type etching apparatus having an upper and a lower electrode plate placed to face each other in parallel and respectively connected to power supplies for plasma generation.
The plasma processing apparatus 1 has a cylindrical processing chamber (processing vessel) 2 formed of, for example, aluminum whose surface is anodically oxidized, and the chamber 2 is grounded.
Installed on a bottom portion of the processing chamber 2 via an insulating plate 3 such as ceramic is a substantially columnar susceptor support 4 for mounting, for example, a semiconductor wafer W thereon. Further, a susceptor 5 serving as a lower electrode is mounted on the susceptor support, and the susceptor 5 is connected to a high pass filter (HPF) 6.
A coolant chamber 7 is formed within the susceptor support 4, and a coolant is introduced into the coolant chamber 7 via a coolant introducing line 8. By the circulation of the coolant through the coolant chamber 7, heat transfer between the semiconductor wafer W and the coolant is carried out via the susceptor 5, whereby the semiconductor wafer W is maintained at a desired temperature level.
The susceptor 5 has an upper central portion of disk shape, which protrudes higher than its peripheral portion, and an electrostatic chuck 11 that is shaped substantially identical to the semiconductor wafer W is mounted on the upper central portion of the susceptor 5. The electrostatic chuck 11 includes an electrode 12 embedded in an insulating member. The electrostatic chuck 11 electrostatically adsorbs and holds the semiconductor wafer W by, for example, a Coulomb force generated by a DC voltage of, for example, 1.5 kV applied to the electrode 12 from a DC power supply 13 coupled to the electrode 12.
Further, formed through the insulating plate 3, the susceptor support 4, the susceptor 5 and the electrostatic chuck 11 is a gas channel 14 for supplying a heat transfer medium, for example, a helium (He) gas, to the rear surface of the semiconductor wafer W. Thus, heat is transferred between the susceptor 5 and the semiconductor wafer W through the heat transfer medium, so that the wafer W can be maintained at a predetermined temperature.
Moreover, an annular focus ring 15 is disposed on the upper peripheral portion of the susceptor 5 to surround the semiconductor wafer W loaded on the electrostatic chuck 11. The focus ring 15 is formed of a conductive material such as silicon and serves to improve uniformity of etching.
An upper electrode 21 is disposed above the susceptor 5 to face it in parallel and is supported at an upper portion of the processing chamber 2 via an insulating member 22. The upper electrode 21 includes an electrode plate 24 that faces the susceptor 5; and an electrode support 25 that serves to support the electrode 24 and is made of a conductive material. The electrode plate 24 is formed of, for example, aluminum whose surface is anodically oxidized (alumite treated) with a quartz cover attached thereto. Further, the electrode plate 24 is provided with a number of injection openings 23.
A gas inlet port 26 is formed at a center of the electrode support 25 of the upper electrode 21 and coupled to a gas supply line 27. Further, the gas supply line 27 is connected to a processing gas supply source 30 via a valve 28 and a mass flow controller 29.
A gas exhaust pipe 31 is connected to a bottom portion of the chamber 2 and coupled to a gas exhaust unit 35. The gas exhaust unit 35 includes a vacuum pump such as a turbo molecular pump, and serves to reduce the inner pressure of the chamber 2 down to a predetermined vacuum level, e.g., 1 Pa or less. Further, a gate valve 32 is installed on a sidewall of the chamber 2. The wafer W is transferred between the chamber 2 and an adjacent load lock chamber (not shown) while the gate valve 32 is opened.
A first high frequency power supply 40 is connected to the upper electrode 21 via a matching unit 41. Further, a low pass filter (LPF) 42 is coupled to the upper electrode 21. The first high frequency power supply 40 is of a frequency ranging from 50 to 150 MHz. By applying a high frequency power in such a range, a high-density plasma in a desirable dissociated state can be generated within the chamber 2.
Further, a second high frequency power supply 50 is connected to the susceptor 5 serving as the lower electrode via a matching unit 51. The second high frequency power supply 50 has a frequency range lower than that of the first high frequency power supply 40. By applying a power of a frequency in such a range, a proper ionic action can be facilitated without causing any damage on the wafer W. Preferably, the frequency of the second high frequency power supply 50 is determined within a range from about 1 to 20 MHz.
The whole operation of the plasma processing apparatus 1 having the above-described configuration is controlled by a control unit 60. The control unit 60 includes: a process controller 61 with a CPU for controlling each component of the plasma processing apparatus; a user interface 62; and a memory unit 63.
A process manager can operate the plasma processing apparatus 1 by using the user interface 62, wherein the user interface 62 includes a keyboard for inputting a command, a display for showing an operational status of the plasma processing apparatus, and the like.
Moreover, the memory unit 63 stores therein a control program (software) to be used in realizing various processings performed in the plasma processing apparatus under the control of the process controller 61, and/or recipes, each recipe containing processing condition data and the like. When a command is received from the user interface 62, the process controller 61 retrieves a necessary recipe from the memory unit 63 to execute it, so that a desired processing is performed in the plasma processing apparatus 1 under the control of the process controller 61. Further, the control program or the recipe containing processing condition data and the like can be retrieved from a computer-readable storage medium (such as a hard disk, a compact disk, a flexible disk, a semiconductor memory or the like) or retrieved on-line through, for example, a dedicated line from another apparatus available all the time.
Hereinafter, there will be described a sequence for plasma etching a semiconductor wafer W which at least has a silicon nitride film, an antireflection film and a photo resist with openings laminated on a silicon substrate in this order from the lower side, to thereby form in the silicon substrate trenches for device isolation, each trench corresponding to one of the openings of the resist, wherein the plasma etching is performed by the plasma processing apparatus 1 configured as described above. The gate valve 32 is opened first, and the semiconductor wafer W is loaded into the processing chamber 2 via a load lock chamber (not shown) to be finally mounted on the electrostatic chuck 11. Then, the semiconductor wafer W is adsorbed by the electrostatic chuck 11 to be held thereon by a DC voltage applied to the electrostatic chuck 11 from the DC power supply 13. Subsequently, the gate valve 32 is closed, and the processing chamber 2 is evacuated to a predetermined vacuum level by the gas exhaust unit 35.
Thereafter, the valve 28 is opened, and a predetermined etching gas is supplied into the hollow space of the upper electrode 21 via the gas supply line 27 and the gas inlet port 26 while its flow rate is controlled by the mass flow controller 29. Then, the etching gas is discharged uniformly toward the semiconductor wafer W through injection openings 23 of the electrode plate 24, as indicated by arrows in
Then, while the internal pressure of the chamber 2 is maintained at a predetermined pressure level, a high frequency power of a predetermined frequency is applied to the upper electrode 21 from the first high frequency power supply 40, whereby a high frequency electric field is generated between the upper electrode 21 and the susceptor 5 serving as the lower electrode, so that the processing gas is dissociated and converted into plasma.
Meanwhile, another high frequency power of a frequency lower than that from the first high frequency power supply 40 is applied to the susceptor 5 serving as the lower electrode from the second high frequency power supply 50. As a result, ions among the plasma are attracted toward the susceptor 5, so that etching anisotropy is improved by ion assist.
Then, upon the completion of the plasma etching, the supply of the high frequency powers and the etching gas is stopped, and the semiconductor wafer W is retreated out of the processing chamber in the reverse sequence as described above.
Hereafter, a semiconductor device manufacturing method in accordance with the preferred embodiment of the present invention will be described.
At an initial stage of an etching process in the processing chamber 2, the ARC film 103's and the silicon nitride film 102's portions located below openings 105 of the photo resist 104 are etched by using the photo resist 104 as a mask. After the photo resist 104 is completely etched, the ARC film 103 and the silicon nitride film 102 are etched entirely, during which the silicon substrate 101's portions once located below the openings 105, where the etching advances faster, are etched, so that trenches 106 for device isolation (STI) are formed in the silicon substrate 101, as shown in
Preferably, the etching gas containing the NF3 gas, the SF6 gas, or the gaseous mixture of NF3 and SF6 further contains an additive gas, wherein the additive gas is one of, for example, a CF4 gas, a rare gas or a gaseous mixture of CF4 and a rare gas. Further, a gas further containing an oxygen gas in addition to the additive gas can also be appropriately utilized. Moreover, the ratio of a flow rate of the additive gas to a flow rate of the NF3 gas, the SF6 gas or the gaseous mixture of NF3 and SF6 (a flow rate of the additive gas/a flow rate of the NF3 gas, the SF6 gas or the gaseous mixture of NF3 and SF6), is preferably set to be not smaller than a value of 1. By controlling the flow rate of the additive gas, the etching rate of the silicon nitride film 102, which is used as a mask when etching the silicon substrate 101, can be controlled appropriately. That is, by increasing the flow rate of the additive gas, the etching rate of the silicon nitride film 102 can be reduced. Accordingly, by setting the ratio to be not smaller than 1, the etching rate of the portion serving as the mask can be reduced to obtain a trench of a desired depth. For example, a gaseous mixture of a CF4 gas, an NF3 gas, and an O2 gas may be employed as the etching gas.
In a test experiment, a plasma etching as described above was performed on a semiconductor wafer having a structure as illustrated in
Further, the processing recipe for the plasma etching is recorded in the memory unit 63 of the control unit 60 to be read and executed by the process controller 61. The processing controller 61 controls each component of the plasma processing apparatus 1 in compliance with a control program so that an etching process is executed according to the recipe.
The processing recipe is as follows:
etching gas: CF4/NF3/O2=250/70/6 sccm;
pressure: 8.0 Pa (60 mTorr);
power (upper electrode/lower electrode): 550 W (60 MHZ)/500 W (13.56 MHZ); and
etching time: 1 minute.
After completing the plasma etching process, the semiconductor wafer W was observed through an electron microscope, and trenches 106 of desired shapes were found to be formed in a silicon substrate 101, as shown in
(Etching of an ARC Film)
As can be seen from the above recipes, about 3 minutes of etching time was required in the conventional method of performing a plasma etching by changing etching gases for each of the ARC film 103, the silicon nitride film 102 and the silicon substrate 101, whereas just 1 minute was needed in the test experiment in accordance with the preferred embodiment of the present invention. That is, at least about 2 minutes can be reduced in accordance with the present invention. Further, in case of performing the plasma etching by changing etching gases for each of the layers, additional time is required for the changing work of the etching gases, so that the entire processing time would be further increased.
Also, though the preferred embodiment of the present invention has been described for the case of using a gas containing an NF3 gas as an etching gas, a gas containing an SF6 gas in which fluorine dissociates like the NF3 gas or a gas containing an NF3 gas and an SF6 gas can be employed as the etching gas. Further, the substrate to be processed is not limited to a semiconductor wafer W having a structure as described in
In accordance with the preferred embodiment of the present invention, the whole processing time required for performing a plasma etching to form trenches for device isolation can be reduced, while enhancing throughput and productivity. Furthermore, it is to be noted that the present invention is not limited to the preferred embodiment as described above but can be changed in various ways. For example, the plasma processing apparatus used in the present invention is not limited to the parallel plate type apparatus with an upper and a lower electrode to which high frequency powers are applied, as illustrated in
While the invention has been shown and described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-321745 | Nov 2005 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| 60740242 | Nov 2005 | US |
