Claims
- 1. A controller circuit for accessing one or more electronic circuits for testing, debugging, or programmably configuring the circuits, comprising:
a test bus; a first controller connected to the test bus; and a plurality of second controllers connected to the test bus, each second controller being coupleable to a respective electronic circuit to be accessed, wherein the first controller is configured to send at least one first control signal over the test bus to respective second controllers to initiate parallel scan access of the electronic circuits coupleable thereto by the respective second controllers, and wherein each second controller is configured to employ a scan protocol to access the respective electronic circuit coupleable thereto based on the at least one first control signal sent over the test bus by the first controller, each second controller being further configured to send first resultant scan data over the test bus to the first controller in response to accessing the respective electronic circuit.
- 2. The controller circuit of claim 1 wherein each second controller includes a first interface compatible with the IEEE 1149.1 test standard, each second controller being further configured to employ the protocol given in the IEEE 1149.1 test standard to access the respective electronic circuit coupleable thereto.
- 3. The controller circuit of claim 2 wherein each second controller further includes a second interface compatible with the IEEE 1149.4 test standard, each second controller being further configured to employ the protocol given in the IEEE 1149.4 test standard to access the respective electronic circuit coupleable thereto.
- 4. The controller circuit of claim 1 wherein the first controller includes an interface compatible with the IEEE 1149.1 test standard.
- 5. The controller circuit of claim 1 wherein the test bus comprises a multi-drop test access port bus and each electronic circuit to be accessed includes a respective test access port bus.
- 6. The controller circuit of claim 5 wherein each second controller is further configured to link the multi-drop test access port bus to the respective test access port bus included in the electronic circuit coupleable thereto.
- 7. The controller circuit of claim 1 wherein the test bus comprises a digital test bus, and the controller circuit further includes an analog test bus, a third controller, and a communication link configured to couple the third controller to the first controller, the analog test bus being coupled to the third controller and coupleable to the respective electronic circuits to be accessed.
- 8. The controller circuit of claim 7 wherein the third controller is configured to employ a second protocol to access the respective electronic circuits based on at least one second control signal sent over the digital test bus by the first controller, the third controller being further configured to send second resultant scan data over the communication link to the first controller in response to accessing the respective electronic circuits.
- 9. The controller circuit of claim 8 wherein the third controller includes an interface compatible with the IEEE 1149.4 test standard, the third controller being further configured to employ the protocol given in the IEEE 1149.4 test standard to access the respective electronic circuits.
- 10. The controller circuit of claim 1 wherein the first controller is further configured to send at least one expected scan-out data signal to the respective second controllers, the expected scan-out data signal being indicative of scan data expected to be scanned-out of the electronic circuits in response to being accessed by the respective second controllers.
- 11. The controller circuit of claim 10 wherein each second controller is further configured to receive actual scan data scanned-out of the respective electronic circuit in response to being accessed, and compare the actual scan-out data to the expected scan-out data in parallel and send resultant data over the test bus to the first controller in response to the comparison.
- 12. The controller circuit of claim 10 wherein the first controller is further configured to send at least one first mask signal to the respective second controllers, the first mask signal being operative to mask at least a portion of the expected scan-out data.
- 13. The controller circuit of claim 12 wherein each second controller is configured to provide scan-in data to the respective electronic circuit coupleable thereto, and the first controller is further configured to send at least one second mask signal to the second controller, the second mask signal being operative to mask at least a portion of the scan-in data.
- 14. The controller circuit of claim 11 wherein the respective second controllers are further configured to store the resultant data.
- 15. The controller circuit of claim 11 wherein the respective second controllers are further configured to compact the actual scan-out data.
- 16. The controller circuit of claim 1 wherein each second controller includes a digital input/output circuit configured to convey one or more digital signals between the second controller and the respective electronic circuit based on at least one second control signal sent over the test bus by the first controller.
- 17. The controller circuit of claim 16 wherein the first controller is configured to send at least one expected digital signal to the respective second controllers, the at least one expected digital signal being indicative of at least one digital signal expected to be sent to the respective digital input/output circuits by the electronic circuits in response to being accessed by the respective second controllers.
- 18. The controller circuit of claim 17 wherein the respective second controllers are further configured to receive at least one actual digital signal from the electronic circuit coupleable thereto, and compare the actual digital signals to the expected digital signals in parallel and send resultant data over the test bus to the first controller in response to the comparison.
- 19. The controller circuit of claim 17 wherein the first controller is further configured to send at least one first mask signal to the respective second controllers, the first mask signal being operative to mask at least a portion of the expected digital signal.
- 20. The controller circuit of claim 19 wherein each second controller is configured to provide at least one digital signal to the respective electronic circuit coupleable thereto, and the first controller is further configured to send at least one second mask signal to the second controller, the second mask signal being operative to mask at least a portion of the digital signal provided to the respective electronic circuit by the second controller.
- 21. The controller circuit of claim 1 wherein each second controller includes an auto start circuit configured to send a start signal over the test bus from the second controller to the first controller, the start signal being operative to indicate to the first controller that the respective electronic circuits to be accessed are coupled to the second controllers, thereby enabling the first controller to provide the at least one first control signal to initiate parallel scan access of the electronic circuits.
- 22. The controller circuit of claim 1 wherein each second controller includes a communication interface having an associated voltage level coupleable to the respective electronic circuit to be accessed, and a programmable input/output voltage circuit configured to set the voltage level of the communication interface to assure electrical compatibility with the respective electronic circuit.
- 23. The controller circuit of claim 22 wherein the programmable input/output voltage circuit sets the voltage level of the communication interface based on at least one second control signal sent over the test bus by the first controller.
- 24. The controller circuit of claim 1 wherein the test bus comprises a plurality of test buses and respective pluralities of second controllers are connected to the test buses, and further including at least one bus bridge configured for successively interconnecting the test buses.
- 25. The controller circuit of claim 24 wherein each bus bridge interconnects a first test bus and a second test bus, the first test bus being configured as a source bus.
- 26. The controller circuit of claim 25 wherein the first and second test buses are configured to convey at least one test access port signal including a test data input signal and a test data output signal, the bus bridge being configured to link the test data output signal of the source bus to the test data input signal of the second bus.
- 27. A test bus circuit for accessing one or more electronic circuits for testing, debugging, or programmably configuring the circuits, comprising:
a test bus; a first controller connected to the test bus; and a plurality of second controllers connected to the test bus, each second controller being coupleable to a respective electronic circuit to be accessed, wherein the test bus is configured to convey at least one control signal from the first controller to respective second controllers to initiate parallel scan access to respective ports of the electronic circuits by the respective second controllers, and convey resultant scan data from the respective second controllers to the first controller in response to accessing the respective ports of the electronic circuits coupleable thereto.
- 28. The test bus circuit of claim 27 wherein the respective ports of the electronic circuits to be accessed are compatible with IEEE 1149.1 test standard.
- 29. The test bus circuit of claim 27 wherein the test bus comprises a multi-drop test access port bus.
- 30. The test bus circuit of claim 29 wherein the test bus is further configured to convey at least one test access port signal between the first controller and the plurality of second controllers, the at least one test access port signal being selected from the group consisting of a test clock signal, a test mode select signal, a test data input signal, a test data output signal, and a test reset signal.
- 31. The test bus circuit of claim 27 wherein the test bus is further configured to convey expected scan-out data from the first controller to the respective second controllers, the expected scan-out data being indicative of scan data expected to be scanned-out of the electronic circuits coupleable thereto in response to being accessed at the respective second controllers.
- 32. The test bus circuit of claim 31 wherein the test bus is further configured to convey at least one first mask signal from the first controller to the respective second controllers, the first mask signal being operative to mask at least a portion of the expected scan-out data.
- 33. The test bus circuit of claim 27 wherein each second controller is configured to provide scan-in data to the respective electronic circuit coupleable thereto, and the test bus is further configured to convey at least one second mask signal from the first controller to the second controller, the second mask signal being operative to mask at least a portion of the scan-in data.
- 34. The test bus circuit of claim 27 wherein the test bus is further configured to convey a start signal from the respective second controllers to the first controller, the start signal being operative to indicate to the first controller that the respective electronic circuits to be accessed are coupled to the second controllers, thereby enabling the first controller to provide the at least one control signal to initiate parallel scan access to the respective ports of the electronic circuits.
- 35. A test controller for controlling accessing of one or more electronic circuits for testing, debugging, or programmably configuring the circuits, comprising:
a communication interface connectable to a test bus, wherein the test bus is connected to a plurality of second controllers, each second controller being coupleable to a respective electronic circuit to be accessed; at least one memory configured to store at least one application software module for initiating parallel scan access of the respective electronic circuits by the plurality of second controllers; and at least one processor configured to execute the at least one application software module to control the transmission of at least one control signal over the test bus via the communication interface to respective second controllers, wherein the respective second controllers employ a scan protocol to access the electronic circuits coupleable thereto based on the at least one control signal sent over the test bus by the test controller.
- 36. The test controller of claim 35 wherein the communication interface is compatible with the IEEE 1149.1 test standard.
- 37. The test controller of claim 35 wherein the at least one memory is configured to store at least one application software module for initiating scan access of a single electronic circuit by a selected second controller, the at least one processor being configured to execute the at least one application software module to control the transmission of at least one control signal over the test bus via the communication interface to the selected second controller.
- 38. The test controller of claim 35 wherein the at least one memory is configured to store data denoting a plurality of modes for addressing the plurality of second controllers, the at least one processor being configured to execute the at least one application software module to enable the test controller to address at least one of the plurality of second controllers according to one of the addressing modes.
- 39. The test controller of claim 38 wherein each second controller has an associated address value, and in a first addressing mode the test controller addresses a single second controller based on its associated address value.
- 40. The test controller of claim 38 wherein each second controller has an associated identification value, and in a second addressing mode the test controller addresses one or more of the plurality of second controllers based on their associated identification values.
- 41. The test controller of claim 38 wherein each second controller has an associated group address value, and in a third addressing mode the test controller addresses respective second controllers having the same group address value.
- 42. The test controller of claim 38 wherein at least one of the plurality of second controllers has an associated alias address value, and in a fourth addressing mode the test controller addresses at least one second controller based on its associated alias address value.
- 43. A method of accessing one or more electronic circuits for testing, debugging, or programmably configuring the circuits, comprising the steps of:
providing a first test bus; providing a first controller and a plurality of second controllers connected to the first test bus, each second controller being coupleable to a respective electronic circuit to be accessed; sending at least one first control signal over the first test bus to respective second controllers by the first controller to initiate parallel scan access of the electronic circuits by the respective second controllers; employing a scan protocol to access the respective electronic circuits by the respective second controllers based on the at least one first control signal sent over the first test bus by the first controller; and sending resultant scan data over the first test bus to the first controller in response to accessing the respective electronic circuits by the respective second controllers.
- 44. The method of claim 43 further including the steps of providing a second test bus coupleable to the respective electronic circuits to be accessed and respective third controllers connected to the second test bus and the second controllers, and employing a second protocol to access the respective electronic circuits via the respective third controllers by the second controllers based on at least one second control signal sent over the first test bus by the first controller.
- 45. The method of claim 43 further including the step of sending at least one expected scan-out data signal to the respective second controllers by the first controller, the expected scan-out data signal being indicative of scan data expected to be scanned-out of the electronic circuits in response to being accessed by the respective second controllers.
- 46. The method of claim 45 further including the steps of receiving actual scan data scanned-out of the respective electronic circuit in response to being accessed by the second controller, comparing the actual scan-out data to the expected scan-out data in parallel by the second controller, and sending resultant data over the test bus to the first controller in response to the comparison by the second controller.
- 47. The method of claim 45 further including the step of sending at least one first mask signal to the respective second controllers by the first controller, the first mask signal being operative to mask at least a portion of the expected scan-out data.
- 48. The method of claim 47 further including the steps of providing scan-in data to the respective electronic circuit by the second controller, and sending at least one second mask signal to the second controller by the first controller, the second mask signal being operative to mask at least a portion of the scan-in data.
- 49. The method of claim 43 wherein the first providing step includes providing a plurality of test buses, and the second providing step includes providing respective pluralities of second controllers connected to the test buses, and further including the step of successively interconnecting the test buses by at least one bus bridge.
- 50. The method of claim 49 wherein the step of successively interconnecting the test buses includes interconnecting a first test bus and a second test bus by the bus bridge, the first test bus being a source bus.
- 51. The method of claim 50 further including the steps of conveying at least one test access port signal including a test data input signal and a test data output signal by the first and second test buses, and linking the test data output signal of the source bus to the test data input signal of the second bus by the bus bridge.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority of U.S. Provisional Patent Application No. 60/303,052 filed Jul. 5, 2001 entitled METHOD AND APPARATUS FOR OPTIMIZED PARALLEL TESTING AND ACCESS OF ELECTRONIC CIRCUITS.
Provisional Applications (1)
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Number |
Date |
Country |
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60303052 |
Jul 2001 |
US |