Patent Application
20050133728
(1) Field
The disclosed methods and systems relate generally to semiconductor processing, and more particularly to performing an in-situ calibration test of a dose controller in an ion implantation process.
(2) Description of Relevant Art
Some challenges of semiconductor manufacturing include providing a manufacturing process that produces uniform and controlled doses of materials into semiconductor wafers. When implanting ions to the wafers, it is important to implant a uniform and accurate dose to produce devices having proper operating characteristics.
In conventional ion implanters, a dose controller measures the current of the ion beam. Typically, a Faraday cup is used to measure the dose by converting the detected beam current into an electrical current. A dose controller receives and monitors the electrical current signal and monitors and controls the implant dose so that the wafer is implanted with the proper dose. If the dose controller does not receive an accurate measurement, the wafer will be implanted with an improper dose and thereby create an undesirable under-dose or over-dose implantation into the wafer. Such under- and over-dose conditions cause wafers to be scrapped which increases the manufacturing cost. Semiconductor manufacturers require that the ion implantation system delivers a known and accurate implantation.
The calibration of the dose controller is important for achieving a proper dose level. The amount of calibration offset is directly proportional to amount of dose shift. For instance, if the calibration is off by a known percentage variation, then the expected dose will shift by the same percentage variation. Similarly, for sheet rho measurements, a miscalibration of a known percentage variation will cause a dose shift of the same percentage. The dose controller is calibrated before initial installation, typically by a NIST traceable current source. Thereafter, the dose controller is only re-calibrated when the accuracy of the dose is suspect or at set time intervals. However, components of the dose controller may subtly drift over time without detection such that the dose controller falls outside of the desired tolerance values.
Presently, to determine whether the dose controller is within tolerance, a DC current source test is typically performed. In this DC current source test, the accuracy of the dose controller is only checked whenever a system operator determines that a dosing variation outside of the desired tolerances may be occurring. Oftentimes, when a dosing variation concern is raised, the dose controller will be replaced without making a full analysis of whether the dose controller is within tolerance. Therfore, a systematic in-situ analysis is desired for ensuring that a uniform and accurate implantation dose is being realized.
Other objects and advantages will become apparent hereinafter in view of the specification and drawings.
To provide an overall understanding, certain illustrative embodiments will now be described; however, it will be understood by one of ordinary skill in the art that the systems and methods described herein can be adapted and modified to provide systems and methods for other suitable applications and that other additions and modifications can be made without departing from the scope of the systems and methods described herein.
Unless otherwise specified, the illustrated embodiments can be understood as providing exemplary features of varying detail of certain embodiments, and therefore, unless otherwise specified, features, components, modules, and/or aspects of the illustrations can be otherwise combined, separated, interchanged, and/or rearranged without departing from the disclosed systems or methods. Additionally, the shapes and sizes of components are also exemplary and unless otherwise specified, can be altered without affecting the disclosed systems or methods.
A block diagram for a dose controller 1 according to an embodiment of the present invention is illustrated in
In another embodiment of the present invention, a procedure for checking the calibration can also be done using the internal voltage and/or current source. The internal and external sources can be combined and utilized in many ways. In
The real time test is also applicable to other devices and systems in further embodiments of the present invention. For instance, current sources, voltage sources and other tools that perform current and/or voltage measurements may incorporate this test. In one embodiment, this real time test may check the cabling and Faraday detectors or cups of the implant system. This checking method can be done by sending a signal from the dose controller 1 or from the Faraday cup. The command signal can be generated manually from the dose controller 1 or the Faraday cup or automatically from the VCS 70. This check can be performed during routine maintenance or before every setup. The dose controller 1 also creates a scan or Trek amp signal. The dose controller 1 can create this waveform and check its shape for comparison with a commanded waveform in real time. This can be done inside the dose controller 1. Also, the feedback signal (the signal that originates from the dose controller 1 going to the Trek amps and the voltage applied to scan plates of the implanter which returns to the Trek amps and then to the dose controller 1, for example) from the scan plates can be checked by the dose controller 1 (or the VCS 70) check by sending the signal to the Trek amps. This test can be done during setup or during maintenance and the check interval can be adjusted. Reference checks may be added as archivable variable that are added to implant logs so that a quick and easy determination may flag a possible error condition.
Next, one voltage is applied to the dose controller 1 at step S120 during the set up and a gain is selected at step S130. At step S140, the voltage output is read and stored, then the gain is incremented at step S150. Steps S130, S140 and S150 are repeated until all of the gain values are incremented and selected. For instance, x1, x2, x4 and x8 gain values may be incremented for the test in the present embodiment.
After the gain values are incremented and stored, a predetermined voltage and gain are selected at step S160, 5V at x1 gain for example, and an output voltage is read at step S170. At steps S180 and S190, zero is subtracted from all of the voltages and the values are normalized to a 1V reference, respectively. The normalized value is then compared to a predetermined count value at step S200. For instance, when 1V at x1 is selected, the count value is 6400, for 1V at x2, the count value is 12,800, for 1V at x4, the count value is 25,600 and for 1V at x8, the count value is 51,200. If this count value is within a predetermined tolerance, 0.5% for example, the operation passes and implantation may proceed from step S210. However, if the count value is not within the tolerance, the implantation operation is stopped and the calibration verification of the dose controller is performed at step S220.
FIGS. 3(a), 3(b), and 3(c) illustrate a timing diagram for an embodiment of the present invention.
A DC test flow chart 400 is shown in
The external DC test is a semi-automatic test where a user is guided through measurements by the controller. Generally, the user is prompted to a request for a particular range and gain to be set on the external current source and the controller sets up the range and gain settings required and makes an integrated beam current measurement. The user may be prompted to connect cables and adjust external current source settings. The data is recorded and an error percentage is computed from the requested input current for indicating pass/fail status. More particularly, an external DC test initialization is performed at step 420. A first input current of 10 mA is selected and measured when the user has completed the request prompts at step 422. Next, a second input current of 5 mA is selected and measured at step 424 and multiple 5 mA measurements (for example, two measurements are different gains) are performed at step 426. A third input current of 1 mA is selected and measured at step 428 and multiple 1 mA measurements are performed for a plurality of range and gain combinations at step 430.
A fourth input current of 0.5 mA is selected and a single measurement is made at step 432. Next, a fifth input current 0.1 mA is selected and measured at step 434 and then multiple 0.1 mA measurements may be performed at step 436. 50 uA and 10 uA input currents are respectively selected and measured at steps 438 and 440. Multiple 10 uA measurements may be performed at step 442. Next, 5 uA and 1 uA input currents are respectively selected and measured at steps 444 and 446 with multiple 1 uA measurements being performed at step 448. The last input currents of 0.5 uA and 0.1 uA are respectively selected and measured at steps 450 and 452. Thereafter, the dose controller settings are restored at step 454 and the pass/fail status is evaluated at step 456. Finally, the test results are reported at step 458 for the external DC test.
What has thus been described are systems and methods for preventing overdosing of workpieces and wafers during an implantation process. The methods and systems described herein are not limited to a particular hardware or software configuration, and may find applicability in many computing or processing environments. The methods and systems can be implemented in one or more computer programs, where a computer program can be understood to include one or more processor executable instructions. The computer program(s) can execute on one or more programmable processors, and can be stored on one or more storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), one or more input devices, and/or one or more output devices. The processor thus can access one or more input devices to obtain input data, and can access one or more output devices to communicate output data. The input and/or output devices can include one or more of the following: Random Access Memory (RAM), Redundant Array of Independent Disks (RAID), floppy drive, CD, DVD, magnetic disk, internal hard drive, external hard drive, memory stick, or other storage device capable of being accessed by a processor as provided herein, where such aforementioned examples are not exhaustive, and are for illustration and not limitation.
The computer program(s) is preferably implemented using one or more high level procedural or object-oriented programming languages to communicate with a computer system; however, the program(s) can be implemented in assembly or machine language, if desired. The language can be compiled or interpreted.
As provided herein, the processor(s) can thus be embedded in one or more devices that can be operated independently or together in a networked environment, where the network can include, for example, a Local Area Network (LAN), wide area network (WAN), and/or can include an intranet and/or the internet and/or another network. The network(s) can be wired or wireless or a combination thereof and can use one or more communications protocols to facilitate communications between the different processors. The processors can be configured for distributed processing and can utilize, in some embodiments, a client-server model as needed. Accordingly, the methods and systems can utilize multiple processors and/or processor devices, and the processor instructions can be divided amongst such single or multiple processor/devices.
The device(s) or computer systems that integrate with the processor(s) can include, for example, a personal computer(s), workstation (e.g., Sun, HP), personal digital assistant (PDA), handheld device such as cellular telephone, laptop, handheld, or another device capable of being integrated with a processor(s) that can operate as provided herein. Accordingly, the devices provided herein are not exhaustive and are provided for illustration and not limitation.
References to “a processor” or “the processor” can be understood to include one or more processors that can communicate in a stand-alone and/or a distributed environment(s), and can thus can be configured to communicate via wired or wireless communications with other processors, where such one or more processor can be configured to operate on one or more processor-controlled devices that can be similar or different devices. Furthermore, references to memory, unless otherwise specified, can include one or more processor-readable and accessible memory elements and/or components that can be internal to the processor-controlled device, external to the processor-controlled device, and can be accessed via a wired or wireless network using a variety of communications protocols, and unless otherwise specified, can be arranged to include a combination of external and internal memory devices, where such memory can be contiguous and/or partitioned based on the application. Accordingly, references to a database can be understood to include one or more memory associations, where such references can include commercially available database products (e.g., SQL, Informix, Oracle) and also proprietary databases, and may also include other structures for associating memory such as links, queues, graphs, trees, with such structures provided for illustration and not limitation.
References to a network, unless provided otherwise, can include one or more intranets and/or the internet.
Many additional changes in the details, materials, and arrangement of parts, herein described and illustrated, can be made by those skilled in the art. Accordingly, it will be understood that the following claims are not to be limited to the embodiments disclosed herein, can include practices otherwise than specifically described, and are to be interpreted as broadly as allowed under the law.
