Patent Application
20170309623
Generally, the present disclosure relates to the manufacture and use of sophisticated semiconductor devices, and, more specifically, to various methods, structures, and systems for increasing the drive current of FinFET devices.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another. In this manner, integrated circuit chips may be fabricated.
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin field effect transistors (FinFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FinFET process, a fin (rectangular in cross-section) is formed on a surface of the wafer, and a gate is formed over the fin.
One challenge facing FinFETs is that the drive current may be undesirably low for various intended uses. One attempt to solve this challenge has been to increase the top and bottom critical dimensions of a rectangular or straight fin in order to increase the area. However, doing so significantly increases the leakage current of the FinFET with a negligible increase on drive current.
Therefore, it would be desirable to have FinFETs with increased drive current, and especially without a corresponding significant increase in leakage current.
The present disclosure may address and/or at least reduce one or more of the problems identified above regarding the prior art and/or provide one or more of the desirable features listed above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to semiconductor devices, comprising a semiconductor substrate comprising bulk silicon; and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises a lower portion disposed on the semiconductor substrate and having a first width, and an upper portion disposed on the lower portion and having a second width, wherein the second width is greater than the first width, as well as methods, apparatus, and systems for fabricating such semiconductor devices.
Semiconductor devices in accordance with embodiments of the present disclosure may have an increased drive current, e.g., a drive current at least about 10% greater than a drive current of a comparable semiconductor device comprising a plurality of comparable fins, wherein each of the comparable fins has a lower portion having the first width and an upper portion having the first width. Semiconductor devices in accordance with embodiments of the present disclosure may have an increased drive current without a significant increase in leakage current, e.g., a leakage current no more than about 20% greater than a leakage current of the comparable semiconductor device.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Embodiments herein provide for FinFET semiconductor devices which may have increased drive current without a corresponding significant increase in leakage current. For example, embodiments herein provide for a T-shaped fin for a FinFET device, wherein the T-shaped fin may provide for increased drive current without a corresponding significant increase in leakage current.
Turning to
Any substrate material may be used in the semiconductor substrate 110. In one embodiment, the semiconductor substrate 110 comprises bulk silicon.
In the plurality of fins 120a, 120b, 120c, each fin 120 comprises a lower portion 130 disposed on the semiconductor substrate 110 and having a first width W1, and an upper portion 140 disposed on the lower portion 130 and having a second width W2, wherein the second width is greater than the first width (i.e., W2>W1). Such a fin 120 may be referred to herein as a “T-shaped fin.”
Each fin 120 may be formed of any appropriate material(s) known for use in FinFETs. Each fin 120 may comprise one material or a plurality of materials, such as interleaved layers of various materials (e.g., interleaved layers of silicon and silicon-germanium; interleaved layers of silicon-germanium with a first germanium concentration and silicon-germanium with a second germanium concentration, etc.) In one embodiment, the plurality of fins 120a, 120b, 120c may be formed by depositing one or more materials on the semiconductor substrate 110, with subsequent processing of the deposited materials, such as by embodiments to be described below with reference to
Although
In one embodiment, the first width W1 may be about 14 nm and the second width W2 may be from about 20 nm to about 40 nm. Alternatively or in addition, the plurality of fins 120a, 120b, 120c may have a pitch (distance W between corresponding structural features of adjacent fins, e.g., fins 120a, 120b) from about 22 nm to about 48 nm. Independently of the values of W1, W2, and W, each fin 120 may have a height H of about 41 nm.
Turning to
The gate 150 may comprise a plurality of layers, as is known in the art. For example, the gate 150 may comprise (from closest to each fin 120 to furthest from each fin 120) an interlayer dielectric, a high-K layer, and a polysilicon layer (not shown). The gate 150 may comprise alternative and/or additional layers known to the person of ordinary skill in the art.
The semiconductor device 100 of
Though not to be bound by theory,
In summary,
The semiconductor device 100 of
In one embodiment, the semiconductor device 100 of
Turning now to
In one embodiment, to reduce the width of each fin, the instruction set may comprise instructions to form a plurality of fins on a semiconductor substrate, wherein each fin of the plurality of fins has an initial width; deposit a first oxide on at least a top, a left side, and a right side of each fin of the plurality of fins; deposit a first nitride on the first oxide on at least the top, the left side, and the right side of each fin of the plurality of fins; deposit a second oxide on the first nitride on a lower portion of both the left side and the right side of each fin of the plurality of fins; deposit a second nitride on a portion of the first nitride and a portion of the second oxide exposed on each fin of the plurality of fins; remove a portion of the second nitride extending laterally beyond the second oxide on both the left side and the right side of each fin of the plurality of fins; remove the second oxide; remove a portion of the first nitride exposed on the left side and the right side of each fin of the plurality of fins; remove a portion of the first oxide exposed on the left side and the right side of each fin of the plurality of fins; remove a portion of the fin exposed on the left side and the right side of each fin of the plurality of fins, to yield a plurality of fins wherein each fin comprises a lower portion disposed on the semiconductor substrate and having a first width less than the initial width; and remove the second nitride, first nitride, and first oxide from an upper portion of each fin of the plurality of fins, to yield a semiconductor device comprising the semiconductor substrate and a plurality of fins wherein each fin comprises an upper portion disposed on the lower portion and having a second width, wherein the second width is greater than the first width.
In one embodiment, the instructions to form the plurality of fins on a semiconductor substrate may comprise instructions to form the plurality of fins with a pitch from about 22 nm to about 48 nm. Alternatively or in addition, the instruction set may further comprise instructions to form each fin with a height of about 41 nm.
In one embodiment, the instruction set may further comprise instructions to form a gate on each fin of the plurality of fins, wherein the gate physically contacts at least a top, a left side, a right side, a left underside, and a right underside of at least the upper portion.
In one embodiment, the first width may be about 14 nm and the second width may be from about 20 nm to about 40 nm. In one embodiment, the second width may be substantially equal to the initial width.
The semiconductor device manufacturing system 610 may be used to manufacture a semiconductor device 100 having a drive current at least about 10% greater than a drive current of a comparable semiconductor device comprising a plurality of comparable fins, wherein each of the comparable fins has a lower portion having the first width and an upper portion having the first width, and/or having a leakage current no more than about 20% greater than a leakage current of the comparable semiconductor device.
The semiconductor device manufacturing system 610 may comprise various processing stations, such as etch process stations, photolithography process stations, CMP process stations, etc. One or more of the processing steps performed by the semiconductor device manufacturing system 610 may be controlled by the process controller 620. The process controller 620 may be a workstation computer, a desktop computer, a laptop computer, a tablet computer, or any other type of computing device comprising one or more software products that are capable of controlling processes, receiving process feedback, receiving test results data, performing learning cycle adjustments, performing process adjustments, etc.
The semiconductor device manufacturing system 610 may produce semiconductor devices 605 (e.g., integrated circuits) on a medium, such as silicon wafers. The semiconductor device manufacturing system 610 may provide processed semiconductor devices 605 on a transport mechanism 650, such as a conveyor system. In some embodiments, the conveyor system may be sophisticated clean room transport systems that are capable of transporting semiconductor wafers. In one embodiment, the semiconductor device manufacturing system 610 may comprise a plurality of processing steps, e.g., the 1st process step, the 2nd process step, etc.
In some embodiments, the items labeled “605” may represent individual wafers, and in other embodiments, the items 605 may represent a group of semiconductor wafers, e.g., a “lot” of semiconductor wafers.
The system 600 may be capable of manufacturing various products involving various FinFET technologies, e.g., the system 600 may produce devices of CMOS technology, Flash technology, BiCMOS technology, power devices, memory devices (e.g., DRAM devices), NAND memory devices, and/or various other semiconductor technologies.
Generally, a method of forming a FinFET device in accordance with embodiments herein may comprise forming a plurality of fins on a semiconductor substrate, wherein each fin of the plurality of fins has an initial width; and reducing a width of a lower portion of each fin to a first width, to yield a plurality of fins wherein each fin comprises an upper portion having disposed on the lower portion and having a second width, wherein the second width is greater than the first width.
Turning to
Thereafter, the method 700 may involve forming a structure to allow protection of an upper portion of each fin during subsequent processing steps to be performed on a lower portion of each fin. For example, the method 700 may comprise one or more of depositing (at 710) a first oxide on at least a top, a left side, and a right side of each fin of the plurality of fins; depositing (at 715) a first nitride on the first oxide on at least the top, the left side, and the right side of each fin of the plurality of fins; depositing (at 720) a second oxide on the first nitride on a lower portion of both the left side and the right side of each fin of the plurality of fins; and depositing (at 725) a second nitride on a portion of the first nitride and a portion of the second oxide exposed on each fin of the plurality of fins.
The method 700 may involve reducing the width of the lower portion of each fin of the plurality of fins. For example, the method 700 may comprise one or more of removing (at 730) a portion of the second nitride extending laterally beyond the second oxide on both the left side and the right side of each fin of the plurality of fins; removing (at 735) the second oxide from each fin of the plurality of fins; removing (at 740) a portion of the first nitride exposed on the left side and the right side of each fin of the plurality of fins; removing (at 745) a portion of the first oxide exposed on the left side and the right side of each fin of the plurality of fins; and removing (at 750) a portion of the fin exposed on the left side and the right side of each fin of the plurality of fins, to yield a plurality of fins wherein each fin comprises a lower portion disposed on the semiconductor substrate and having a first width less than the initial width.
The method 700 may also involve removing any protecting structures from the upper portion of each fin. For example, the method 700 may comprise removing (at 755) the second nitride, first nitride, and first oxide from an upper portion of each fin of the plurality of fins, to yield a semiconductor device comprising the semiconductor substrate and a plurality of fins wherein each fin comprises an upper portion disposed on the lower portion and having a second width, wherein the second width is greater than the first width.
In one embodiment, the first width is about 14 nm and the second width is from about 20 nm to about 40 nm. Alternatively or in addition, the second width may be substantially equal to the initial width.
The method 700 may further comprise forming (at 760) a gate on each fin of the plurality of fins, wherein the gate physically contacts at least a top, a left side, a right side, a left underside, and a right underside of at least the upper portion.
The method 700 may produce a semiconductor device, wherein the semiconductor device has a drive current at least about 10% greater than a drive current of a comparable semiconductor device comprising a plurality of comparable fins, wherein each of the comparable fins has a lower portion having the first width and an upper portion having the first width, and the semiconductor device has a leakage current no more than about 20% greater than a leakage current of the comparable semiconductor device.
The methods described above may be governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by, e.g., a processor in a computing device. Each of the operations described herein may correspond to instructions stored in a non-transitory computer memory or computer readable storage medium. In various embodiments, the non-transitory computer readable storage medium includes a magnetic or optical disk storage device, solid state storage devices such as flash memory, or other non-volatile memory device or devices. The computer readable instructions stored on the non-transitory computer readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted and/or executable by one or more processors.
Those skilled in the art having the benefit of the present disclosure would appreciate that other geometric shapes developed at the top portion of a fin in a similar manner described herein, may also provide the benefit of increased current drive without significant increase in current leakage. Therefore, a fin that has a lower portion disposed on the semiconductor substrate and having a first width, and an upper portion disposed on the lower portion and having a second width, wherein the second width is greater than the first width, may provide the benefit of increased drive current without significant increase in current leakage.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is, therefore, evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
