Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor

Abstract

A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a semiconductor package which has an adjustment target on design in accordance with a first embodiment of the present invention:

FIG. 2 is a view showing a general model of the semiconductor package of FIG. 1;

FIG. 3 is a view showing a first chip model for power supply voltage fluctuation;

FIG. 4 is a view showing a first chip model for ground voltage fluctuation;

FIG. 5 is a view showing a second chip model for power supply voltage fluctuation;

FIG. 6 is a view showing a second chip model for ground voltage fluctuation;

FIG. 7 is a view showing another first chip model for power supply voltage fluctuation;

FIG. 8 is a view showing another first chip model for ground voltage fluctuation;

FIG. 9 is a view showing another second chip model for power supply voltage fluctuation;

FIG. 10 is a view showing another second chip model for ground voltage fluctuation;

FIG. 11 is a flowchart showing a design method in accordance with the first embodiment;

FIG. 12 is a view for use in describing how to decide impedances of the first and the second chip models;

FIG. 13 is another view for use in describing how to decide impedances of the first and the second chip models;

FIG. 14 is another view for use in describing how to decide impedances of the first and the second chip models;

FIG. 15 is a view for use in describing how to calculate a first current source for power supply voltage fluctuation spectrum calculation;

FIG. 16 is a view for use in describing how to calculate a first current source for ground voltage fluctuation spectrum calculation;

FIG. 17 is a view for use in describing how to calculate a second current source for power supply voltage fluctuation spectrum calculation;

FIG. 18 is a view for use in describing how to calculate a second current source for ground voltage fluctuation spectrum calculation;

FIG. 19 is a view for use in describing how to calculate a power supply voltage fluctuation spectrum in the first transition state;

FIG. 20 is a view for use in describing how to calculate a ground voltage fluctuation spectrum in the first transition state;

FIG. 21 is a view for use in describing how to calculate a power supply voltage fluctuation spectrum in the second transition state;

FIG. 22 is a view for use in describing how to calculate a ground voltage fluctuation spectrum in the second transition state;

FIG. 23 is a flowchart showing a design method in accordance with a second embodiment of the present invention;

FIG. 24 is a view showing a semiconductor system to which an embodiment of the present invention is applicable;

FIG. 25 is a view showing an analysis result of the semiconductor system of FIG. 24; and

FIG. 26 is a block diagram showing a design aid system based on a method of an embodiment of the present invention.

Claims

1. A method for designing a semiconductor package, the semiconductor package comprising a semiconductor chip and an adjustment target, the method comprising: calculating a first target variable on the basis of a first chip model and a target impedance model, the first chip model being created by representing the semiconductor chip in frequency domain in consideration of a first transition state, the first transition state being a state where an output level of the semiconductor chip changes from a low level to a high level, the target impedance model being assumed by representing the adjustment target in frequency domain;calculating a second target variable on the basis of a second chip model and the target impedance model, the second chip model being created by representing the semiconductor chip in frequency domain in consideration of a second transition state, the second transition state being a state where an output level of the semiconductor chip changes from the high level to the low level:in consideration of power integrity for the semiconductor chip, selecting inferior one of the first and the second target variables as a main target variable; andcomparing the main target variable and a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

2. The method according to claim 1, further comprising selecting one of first and second constraints as the predetermined constraint, the first constraint being assumed in consideration of the first transition state, the second constraint being assumed in consideration of the second transition state, the predetermined constraint being the first constraint when the first target variable is selected as the main target variable, the predetermined constraint being the second constraint when the second target variable is selected as the main target variable.

3. The method according to claim 1, wherein; the calculating the first target variable is carried out so that the first target variable is a power-supply/ground voltage spectrum in the first transition state; andthe calculating the second target variable is carried out so that the second target variable is another power-supply/ground voltage spectrum in the second transition state.

4. The method according to claim 1, further comprising: creating the first and the second chip models on the basis of chip information about the semiconductor chip; and assuming the target impedance model on the basis of target information about the adjustment target.

5. The method according to claim 4, wherein: the calculating the first target variable is carried out under a state where the first chip model is connected to the target impedance model; andthe calculating the second target variable is carried out under a state where the second chip model is connected to the target impedance model.

6. The method according to claim 47 the semiconductor chip comprising a power supply pad, a ground pad, an output pad, a pMOS circuitry, an nMOS circuitry and an internal section, the pMOS circuitry being connected between the power supply pad and the output pad, the nMOS circuitry being connected between the output pad and the ground pad, the internal section being connected between the power supply pad and the ground pad, the internal section having an internal impedance, wherein the creating the first and the second chip models comprises: creating the first chip model by connecting a first pMOS circuitry impedance and a first current source in parallel between the power supply pad and the output pad, by connecting a first nMOS circuitry impedance between the output pad and the ground pad, and by connecting the internal impedance between the power supply pad and the ground pad, the first pMOS circuitry impedance being obtained by representing the pMOS circuitry in impedance in consideration of the first transition state, the first nMOS circuitry impedance being obtained by representing the nMOS circuitry in impedance in consideration of the first transition state, the first current source being assumed on the basis of current fluctuation on the power supply pad in the first transition state; andcreating the second chip model by connecting a second pMOS circuitry impedance between the power supply pad and the output pad, by connecting a second nMOS circuitry impedance and a second current source in parallel between the output pad and the ground pad, and by connecting the internal impedance between the power supply pad and the ground pad, the second pMOS circuitry impedance being obtained by representing the pMOS circuitry in impedance in consideration of the second transition state, the second nMOS circuitry impedance being obtained by representing the nMOS circuitry in impedance in consideration of the second transition state, the second current source being assumed on the basis of current fluctuation on the ground pad in the second transition state.

7. The method according to claim 6, wherein: in order to create the first chip model for use in analysis of voltage fluctuation on the power supply pad, the first pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an ON state, and the first nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an OFF state; andin order to create the second chip model for use in analysis of voltage fluctuation on the power supply pad, the second pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an ON state, and the second nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an ON state.

8. The method according to claim 7, wherein: the impedance of the pMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the power supply pad and the output pad;the impedance of the nMOS circuitry of the OFF state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in series between the output pad and the ground pad; andthe impedance of the nMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the output pad and the ground pad.

9. The method according to claim 7, wherein: the first current source is calculated on the basis of assumptions that a predetermined load model is connected between the output pad and the ground pad, that a first power supply current flows through the power supply pad in the first transition state, and that the first power supply current generally flows into the first pMOS circuitry impedance and the predetermined load model; andthe second current source is calculated on the basis of assumptions that the predetermined load model is connected between the output pad and the ground pad, that a second power supply current flows through the power supply pad in the second transition state, and that the second power supply current generally flows into the second pMOS circuitry impedance and the second nMOS circuitry impedance.

10. The “method according to claim 6, wherein: in order to create the first chip model for use in analysis of voltage fluctuation on the ground pad, the first pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an ON state, and the first nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an ON state; andin order to create the second chip model for use in analysis of voltage fluctuation on the ground pad, the second pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an OFF state, and the second nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an ON state.

11. The method according to claim 10, wherein: the impedance of the pMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the power supply pad and the output pad;the impedance of the pMOS circuitry of the OFF state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in series between the power supply pad and the output pad; andthe impedance of the nMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the output pad and the ground pad.

12. The method according to claim 10, wherein: the first current source is calculated on the basis of assumptions that a predetermined load model is connected between the output pad and the ground pad, that a first ground current flows through the ground pad in the first transition state, and that the first ground current generally flows into the first pMOS circuitry impedance and the first nMOS circuitry impedance; andthe second current source is calculated on the basis of assumptions that the predetermined load model is connected between the output pad and the ground pad, that a second ground current flows through the ground pad in the second transition state, and that the second ground current generally flows into the predetermined load model and the second nMOS circuitry impedance.

13. The method according to claim 1, wherein: the calculating the first target variable comprises combining the target impedance model with the first chip model, setting up a first loop equation on the combination of the target impedance model and the first chip model, and solving the first loop equation to obtain the first target variable; andthe calculating the second target variable comprises combining the target impedance model with the second chip model, setting up a second loop equation on the combination of the target impedance model and the second chip model, and solving the second loop equation to obtain the second target variable.

14. The method according to claim 1, wherein the adjustment target is enhanced to includes electrical components formed on a printed circuit board, the semiconductor package being mounted on the printed circuit board.

15. The method according to claim 1, wherein the comparing comprising: identifying a problematic section of the adjustment target, the problematic section corresponding to a frequency region at which the main target variable exceeds the predetermined constraint; anddeciding design guidelines to solve the identified problematic section.

16. A system for aiding to design a semiconductor package, the semiconductor package comprising a semiconductor chip and an adjustment target, the system comprising: a first calculator configured to calculate a first target variable on the basis of a first chip model and a target impedance model, the first chip model being created by representing the semiconductor chip in frequency domain in consideration of a first transition state, the first transition state being a state where an output level of the semiconductor chip changes from a low level to a high level, the target impedance model being assumed by representing the adjustment target in frequency domain;a second calculator configured to calculate a second target variable on the basis of a second chip model and the target impedance model, the second chip model being created by representing the semiconductor chip in frequency domain in consideration of a second transition state, the second transition state being a state where an output level of the semiconductor chip changes from the high level to the low level;a selector configured to select, in consideration of power integrity for the semiconductor chip, inferior one of the first and the second target variables as a main target variable in consideration of power integrity for the semiconductor chip; anda comparator configured to compare the main target variable and a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

17. A system comprising a bus system, a processor connected to the bus system and a memory connected to the bus system, the memory storing a computer program that, when executed by the processor, causes the processor to perform predetermined operations to aid to design a semiconductor package, the semiconductor package comprising a semiconductor chip and an adjustment target, the predetermined operations comprising: calculating a first target variable on the basis of a first chip model and a target impedance model, the first chip model being created by representing the semiconductor chip in frequency domain in consideration of a first transition state, the first transition state being a state where an output level of the semiconductor chip changes from a low level to a high level, the target impedance model being assumed by representing the adjustment target in frequency domain;calculating a second target variable on the basis of a second chip model and the target impedance model, the second chip model being created by representing the semiconductor chip in frequency domain in consideration of a second transition state, the second transition state being a state where an output level of the semiconductor chip changes from the high level to the low level;in consideration of power integrity for the semiconductor chip, selecting inferior one of the first and the second target variables as a main target variable; andcomparing the main target variable and a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

18. The system according to claim 17, wherein the predetermined operations further comprise selecting one of first and second constraints as the predetermined constraint, the first constraint being assumed in consideration of the first transition state, the second constraint being assumed in consideration of the second transition state, the predetermined constraint being the first constraint when the first target variable is selected as the main target variable, the predetermined constraint being the second constraint when the second target variable is selected as the main target variable.

19. The system according to claim 17, wherein: the calculating the first target variable is carried out so that the first target variable is a power-supply/ground voltage spectrum in the first transition state; andthe calculating the second target variable is carried out so that the second target variable is another power-supply/ground voltage spectrum in the second transition state.

20. The system according to claim 17, wherein the predetermined operations further comprise: creating the first and the second chip models on the basis of chip information about the semiconductor chip; and assuming the target impedance model on the basis of target information about the adjustment target.

21. The system according to claim 20, wherein: the calculating the first target variable is carried out under a state where the first chip model is connected to the target impedance model; andthe calculating the second target variable is carried out under a state where the second chip model is connected to the target impedance model.

22. The system according to claim 20, the semiconductor chip comprising a power supply pad, a ground pad, an output pad, a pMOS circuitry, an nMOS circuitry and an internal section, the pMOS circuitry being connected between the power supply pad and the output pad, the nMOS circuitry being connected between the output pad and the ground pad, the internal section being connected between the power supply pad and the ground pad, the internal section having an internal impedance, wherein the creating the first and the second chip models comprises: creating the first chip model by connecting a first pMOS circuitry impedance and a first current source in parallel between the power supply pad and the output pad, by connecting a first nMOS circuitry impedance between the output pad and the ground pad, and by connecting the internal impedance between the power supply pad and the ground pad, the first pMOS circuitry impedance being obtained by representing the pMOS circuitry in impedance in consideration of the first transition state, the first nMOS circuitry impedance being obtained by representing the nMOS circuitry in impedance in consideration of the first transition state, the first current source being assumed on the basis of current fluctuation on the power supply pad in the first transition state; andcreating the second chip model by connecting a second pMOS circuitry impedance between the power supply pad and the output pad, by connecting a second nMOS circuitry impedance and a second current source in parallel between the output pad and the ground pad, and by connecting the internal impedance between the power supply pad and the ground pad, the second pMOS circuitry impedance being obtained by representing the pMOS circuitry in impedance in consideration of the second transition state, the second nMOS circuitry impedance being obtained by representing the nMOS circuitry in impedance in consideration of the second transition state, the second current source being assumed on the basis of current fluctuation on the ground pad in the second transition state.

23. The system according to claim 22, wherein: in order to create the first chip model for use in analysis of voltage fluctuation on the power supply pad, the first pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an ON state, and the first nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an OFF state; andin order to create the second chip model for use in analysis of voltage fluctuation on the power supply pad, the second pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an ON state, and the second nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an ON state.

24. The system” according to claim 23, wherein: the impedance of the pMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the power supply pad and the output pad;the impedance of the nMOS circuitry of the OFF state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in series between the output pad and the ground pad; andthe impedance of the nMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the output pad and the ground pad.

25. The system according to claim 23, wherein: the first current source is calculated on the basis of assumptions that a predetermined load model is connected between the output pad and the ground pad, that a first power supply current flows through the power supply pad in the first transition state, and that the first power supply current generally flows into the first pMOS circuitry impedance and the predetermined load model; andthe second current source is calculated on the basis of assumptions that the predetermined load model is connected between the output pad and the ground pad, that a second power supply current flows through the power supply pad in the second transition state, and that the second power supply current generally flows into the second pMOS circuitry impedance and the second nMOS circuitry impedance.

26. The system according to claim 22, wherein: in order to create the first chip model for use in analysis of voltage fluctuation on the ground pad, the first pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an ON state, and the first nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an ON state; andin order to create the second chip model for use in analysis of voltage fluctuation on the ground pad, the second pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an OFF state, and the second nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an ON state.

27. The system according to claim 26, wherein: the impedance of the pMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the power supply pad and the output pad;the impedance of the pMOS circuitry of the OFF state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in series between the power supply pad and the output pad; andthe impedance of the nMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the output pad and the ground pad.

28. The system according to claim 26, wherein: the first current source is calculated on the basis of assumptions that a predetermined load model is connected between the output pad and the ground pad, that a first ground current flows through the ground pad in the first transition state, and that the first ground current generally flows into the first pMOS circuitry impedance and the first nMOS circuitry impedance; andthe second current source is calculated on the basis of assumptions that the predetermined load model is connected between the output pad and the ground pad, that a second ground current flows through the ground pad in the second transition state, and that the second ground current generally flows into the predetermined load model and the second nMOS circuitry impedance.

29. The system according to claim 17, wherein: the calculating the first target variable comprises combining the target impedance model with the first chip model, setting up a first loop equation on the combination of the target impedance model and the first chip model, and solving the first loop equation to obtain the first target variable; andthe calculating the second target variable comprises combining the target impedance model with the second chip model, setting up a second loop equation on the combination of the target impedance model and the second chip model, and solving the second loop equation to obtain the second target variable.

30. The system according to claim 17, wherein the adjustment target is enhanced to includes electrical components formed on a printed circuit board, the semiconductor package being mounted on the printed circuit board.

31. The system according to claim 17, wherein the comparing comprising: identifying a problematic section of the adjustment target, the problematic section corresponding to a frequency region at which the main target variable exceeds the predetermined constraint; anddeciding design guidelines to solve the identified problematic section.

32. A computer program product in a computer readable medium for use in a system for aiding to design a semiconductor package, the semiconductor package comprising a semiconductor chip and an adjustment target, the computer program product comprising: instructions for calculating a first target variable on the basis of a first chip model and a target impedance model, the first chip model being created by representing the semiconductor chip in frequency domain in consideration of a first transition state, the first transition state being a state where an output level of the semiconductor chip changes from a low level to a high level, the target impedance model being assumed by representing the adjustment target in frequency domain;instructions for calculating a second target variable on the basis of a second chip model and the target impedance model, the second chip model being created by representing the semiconductor chip in frequency domain in consideration of a second transition state, the second transition state being a state where an output level of the semiconductor chip changes from the high level to the low level;instructions for selecting, in consideration of power integrity for the semiconductor chip, inferior one of the first and the second target variables as a main target variable; andinstructions for comparing the main target variable and a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

33. The computer program product according to claim 32, further comprising instructions for selecting one of first and second constraints as the predetermined constraint, the first constraint being assumed in consideration of the first transition state, the second constraint being assumed in consideration of the second transition state, the predetermined constraint being the first constraint when the first target variable is selected as the main target variable, the predetermined constraint being the second constraint when the second target variable is selected as the main target variable.

34. The computer program product according to claim 32, wherein, the instructions for calculating the first target variable is carried out so that the first target variable is a power-supply/ground voltage spectrum in the first transition state; andthe instructions for calculating the second target variable is carried out so that the second target variable is another power-supply/ground voltage spectrum in the second transition state.

35. The computer program product according to claim 32, further comprising: instructions for creating the first and the second chip models on the basis of chip information about the semiconductor chip; and instructions for assuming the target impedance model on the basis of target information about the adjustment target.

36. The computer program product according to claim 35, wherein: the instructions for calculating the first target variable is carried out under a state where the first chip model is connected to the target impedance model; andthe instructions for calculating the second target variable is carried out under a state where the second chip model is connected to the target impedance model.

37. The computer program product according to claim 35, the semiconductor chip comprising a power supply pad, a ground pad, an output pad, a pMOS circuitry, an nMOS circuitry and an internal section, the pMOS circuitry being connected between the power supply pad and the output pad, the nMOS circuitry being connected between the output pad and the ground pad, the internal section being connected between the power supply pad and the ground pad, the internal section having an internal impedance, wherein the instructions for creating the first and the second chip models comprises: instructions for creating the first chip model by connecting a first pMOS circuitry impedance and a first current source in parallel between the power supply pad and the output pad, by connecting a first nMOS circuitry impedance between the output pad and the ground pad, and by connecting the internal impedance between the power supply pad and the ground pad, the first pMOS circuitry impedance being obtained by representing the pMOS circuitry in impedance in consideration of the first transition state, the first nMOS circuitry impedance being obtained by representing the nMOS circuitry in impedance in consideration of the first transition state, the first current source being assumed on the basis of current fluctuation on the power supply pad in the first transition state; andinstructions for creating the second chip model by connecting a second pMOS circuitry impedance between the power supply pad and the output pad, by connecting a second nMOS circuitry impedance and a second current source in parallel between the output pad and the ground pad, and by connecting the internal impedance between the power supply pad and the ground pad, the second pMOS circuitry impedance being obtained by representing the pMOS circuitry in impedance in consideration of the second transition state, the second nMOS circuitry impedance being obtained by representing the nMOS circuitry in impedance in consideration of the second transition state, the second current source being assumed on the basis of current fluctuation on the ground pad in the second transition state.

38. The computer program product according to claim 37, wherein: in order to create the first chip model for use in analysis of voltage fluctuation on the power supply pad, the first pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an ON state, and the first nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an OFF state; andin order to create the second chip model for use in analysis of voltage fluctuation on the power supply pad, the second pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an ON state, and the second nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an ON state.

39. The computer program product according to claim 38, wherein; the impedance of the pMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the power supply pad and the output pad;the impedance of the nMOS circuitry of the OFF state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in series between the output pad and the ground pad; andthe impedance of the nMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the output pad and the ground pad.

40. The computer program product according to claim 38, wherein: the first current source is calculated on the basis of assumptions that a predetermined load model is connected between the output pad and the ground pad, that a first power supply current flows through the power supply pad in the first transition state, and that the first power supply current generally flows into the first pMOS circuitry impedance and the predetermined load model; andthe second current source is calculated on the basis of assumptions that the predetermined load model is connected between the output pad and the ground pad, that a second power supply current flows through the power supply pad in the second transition state, and that the second power supply current generally flows into the second pMOS circuitry impedance and the second nMOS circuitry impedance.

41. The computer program product according to claim 37, wherein: in order to create the first chip model for use in analysis of voltage fluctuation on the power supply pad, the instructions for creating the first chip model comprises instructions for carrying out an transient analysis on a SPICE model for the semiconductor chip in accordance with the first transition state to obtain a first current waveform and instructions for carrying out the Fourier transform for the first current waveform to obtain a spectrum of a current flowing through the power supply pad in the first transition state; andin order to create the second chip model for use in analysis of voltage fluctuation on the power supply pad, instructions for creating the second chip model comprises instructions for carrying out an transient analysis on a SPICE model for the semiconductor chip in accordance with the second transition state to obtain a second current waveform and instructions for carrying out the Fourier transform for the second current waveform to obtain a spectrum of a current flowing through the power supply pad in the second transition state.

42. The computer program product according to claim 36, wherein: in order to create the first chip model for use in analysis of voltage fluctuation on the ground pad, the first pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an ON state, and the first nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an ON state; andin order to create the second chip model for use in analysis of voltage fluctuation on the ground pad, the second pMOS circuitry impedance is assumed as an impedance of the pMOS circuitry being on an OFF state, and the second nMOS circuitry impedance is assumed as an impedance of the nMOS circuitry being on an ON state.

43. The computer program product according to claim 42, wherein: the impedance of the pMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the power supply pad and the output pad;the impedance of the pMOS circuitry of the OFF state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in series between the power supply pad and the output pad; andthe impedance of the nMOS circuitry of the ON state is calculated by using an equivalent circuit model comprising a capacitor and a resistor connected in parallel between the output pad and the ground pad.

44. The computer program product according to claim 42, wherein: the first current source is calculated on the basis of assumptions that a predetermined load model is connected between the output pad and the ground pad, that a first ground current flows through the ground pad in the first transition state, and that the first ground current generally flows into the first pMOS circuitry impedance and the first nMOS circuitry impedance; andthe second current source is calculated on the basis of assumptions that the predetermined load model is connected between the output pad and the ground pad, that a second ground current flows through the ground pad in the second transition state, and that the second ground current generally flows into the predetermined load model and the second nMOS circuitry impedance.

45. The computer program product according to claim 37, wherein: in order to create the first chip model for use in analysis of voltage fluctuation on the ground pad, the instructions for creating the first chip model comprises instructions for carrying out an transient analysis on a SPICE model for the semiconductor chip in accordance with the first transition state to obtain a first current waveform and instructions for carrying out the Fourier transform for the first current waveform to obtain a spectrum of a current flowing through the ground pad in the first transition state; andin order to create the second chip model for use in analysis of voltage fluctuation on the ground pad, instructions for creating the second chip model comprises instructions for carrying out an transient analysis on a SPICE model for the semiconductor chip in accordance with the second transition state to obtain a second current waveform and instructions for carrying out the Fourier transform for the second current waveform to obtain a spectrum of a current flowing through the ground pad in the second transition state.

46. The computer program product according to claim 32, wherein, the instructions for calculating the first target variable comprises combining the target impedance model with the first chip model, setting up a first loop equation on the combination of the target impedance model and the first chip model, and solving the first loop equation to obtain the first target variable; andthe instructions for calculating the second target variable comprises combining the target impedance model with the second chip model, setting up a second loop equation on the combination of the target impedance model and the second chip model, and solving the second loop equation to obtain the second target variable.

47. The computer program product according to claim 32, wherein the adjustment target is enhanced to includes electrical components formed on a printed circuit board, the semiconductor package being mounted on the printed circuit board.

48. The computer program product according to claim 32, wherein the instructions for comparing comprising; instructions for identifying a problematic section of the adjustment target, the problematic section corresponding to a frequency region at which the main target variable exceeds the predetermined constraint; andinstructions for deciding design guidelines to solve the identified problematic section.