Patent Application
20100047985
The present disclosure generally relates to semiconductor devices and methods for fabricating semiconductor devices, and more particularly, embodiments of the subject matter relate to methods for fabricating transistors having extension implants that are self-aligned with embedded stressor regions.
The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs) realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode that is formed on a semiconductor substrate and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductor substrate between the source and drain regions beneath the gate electrode. The MOS transistor is accessed via conductive contacts formed on the source and drain regions.
ICs are usually formed using both P-channel FETs (PMOS transistors) and N-channel FETs (NMOS transistors), referred to as a complementary MOS or CMOS integrated circuit. In sub-90 nm CMOS technologies, selective epitaxy is often used to increase the mobility of carriers in the channels of the MOS transistors. This is accomplished by etching a recess or cavity into the semiconductor substrate at the ends of the channel. The cavity may then be filled by the process of selective epitaxial growth with a crystalline material that has a different lattice constant than the host semiconductor substrate. For example, in a PMOS transistor formed on a silicon substrate, the cavity may be filled with silicon germanium (SiGe) to form stressor regions (e.g., embedded SiGe stressors), which apply a compressive longitudinal stress to the channel and increases the mobility of holes in the channel.
As the distance between the stressor regions to the channel decreases, the stress transferred to the channel increases, leading to improved performance at closer proximities. Often, a disposable deposited spacer (DDS) is formed about the sidewalls of the gate electrode and used to control the proximity of the stressor regions to the channel during the selective growth process. The spacer is usually removed following the selective epitaxy, and a second spacer (e.g., an offset spacer) is formed afterwards to define the placement of subsequent extension implanted regions.
Variations in the offset spacer boundary relative to the boundary of the stressor regions can have negative effects on device characteristics. For example, in a PMOS transistor, the diffusion rate of boron in silicon germanium is different than the diffusion rate of boron in silicon. Thus, any variation in the offset spacer boundary relative to the boundary of the stressor regions will affect the amount of lateral P-extension diffusion and the ensuing PMOS transistor source/drain extension overlap, caused by a combination of the as-implanted P-extension dopant profile (influenced by the offset spacer boundary), and the effective P-extension dopant diffusion into the channel (influenced by the extent of diffusion through the material under the offset spacer). Additionally, variations in the thickness of the stressor regions at different locations across the chip and/or wafer also influence the step coverage or etched profile of the offset spacer, and result in further variation in the offset spacer boundary across the chip and/or wafer. These variations affect transistor parameters, such as threshold voltage, drive current, and Miller capacitance. Non-uniformity across the chip and/or wafer can potentially affect the yield, performance, and minimum operating voltage characteristics of the chip and/or wafer.
As the stressor regions are formed closer to the channel, it becomes difficult to align the offset spacer with the boundary of the stressor regions. For example, in 45 nm or 32 nm technologies, the proximity of the stressor regions to the channel (alternatively, the thickness of the DDS) is often 10 nm or less. Because the DDS and the offset spacer are formed using separate deposition and etch processes, it is difficult to align the offset spacer with the boundary of the stressor regions. Additionally, in CMOS devices, the offset spacer is often used as an ion implantation mask during creation of extension implants for both the PMOS and NMOS transistor devices, which limits the ability to resize the offset spacer thickness for purposes of aligning the source/drain extensions for only one of the transistors. Some methods attempt to control the process uniformity of the deposition and etch processes for creating the spacers. However, these approaches add complexity and cost and still provide an imperfect solution.
A method is provided for fabricating a MOS transistor. The method comprises forming a gate stack overlying a layer of semiconductor material and forming a spacer about sidewalls of the gate stack. The method further comprises forming cavities in the layer of semiconductor material, wherein the cavities are substantially aligned with the spacer. The method further comprises forming a stress-inducing semiconductor material in the cavities, and implanting ions of a conductivity-determining impurity type into the stress-inducing semiconductor material using the gate stack and the spacer as an implantation mask.
Another method is provided for fabricating a semiconductor device having stressor regions that are self-aligned with an ion implantation mask. The method comprises forming a gate stack overlying a layer of semiconductor material and forming a layer of an insulating material on the gate stack and the layer of semiconductor material. The method further comprises etching the layer of the insulating material and the layer of semiconductor material to form a spacer about sidewalls of the gate stack and cavities in the layer of semiconductor material, wherein the cavities are self-aligned with the spacer. The method further comprise forming a stress-inducing semiconductor material in the cavities, resulting in stressor regions that are self-aligned with the spacer, and implanting ions of a conductivity-determining impurity type into the stressor regions using the gate stack and the spacer as an implantation mask.
In another embodiment, a method for fabricating a CMOS device is provided. The method comprises providing a semiconductor device structure having a first region of semiconductor material and a second region of semiconductor material, a first gate stack overlying the first region of semiconductor material, and a second gate stack overlying the second region of semiconductor material. The method further comprises masking the second region of semiconductor material. While the second region of semiconductor material is masked, the method further comprises forming a spacer about sidewalls of the first gate stack, and forming cavities in the first region of semiconductor material, wherein the cavities are substantially aligned with the spacer. The method further comprises at least partially filling the cavities with a stress-inducing semiconductor material, and implanting P-type ions into the stress-inducing semiconductor material using the first gate stack and the spacer as an implantation mask.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
A more complete understanding of the subject matter may be derived by referring to the detailed description and claims when considered in conjunction with the following figures, wherein like reference numbers refer to similar elements throughout the figures.
The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or the following detailed description.
Referring to
As shown in
In a preferred embodiment, the isolated regions 106, 108 are implanted with ions to achieve a desired dopant profile. For example, a layer of photoresist may be applied and patterned to mask the first region 106, and a P-well may be formed in the second region 108 by implanting the second region 108 with boron ions. The layer of photoresist masking the first region 106 may be removed, and another layer of photoresist applied and patterned to mask the second region 108. An N-well may be formed in the first region 106 by implanting arsenic and/or phosphorus ions into the first region 106. The layer of photoresist masking the second region 108 is removed and the semiconductor substrate is heated to activate the implants. These ion implantation steps may include several different, separate implantations at different energies and different doses to achieve a desired doping profile, as will be appreciated in the art.
Referring to
Referring to
Although one or more additional process steps may be performed next, in a preferred embodiment, the fabrication of the CMOS semiconductor device continues by forming a PMOS transistor structure on the first region 106 of the semiconductor substrate, as shown in
In an exemplary embodiment, the second region 108 and gate stack 114 are masked by depositing and patterning photoresist material to leave a layer of photoresist 130 that protects the second region 108 and gate stack 114 as illustrated in
In an exemplary embodiment, the fabrication process continues by forming cavities 134 in the layer of semiconductor material of first region 106. Notably, the cavities 134 are formed in the first region 106 by anisotropically etching the layer of semiconductor material using the gate stack 112, photoresist layer 130, and spacer 132 as an etch mask. In this manner, the cavities 134 are self-aligned with the spacer 132. As used herein, self-aligned should be understood to mean that the inward facing sides of the cavities 134 are naturally formed such that they are aligned with the outward facing sides of the spacers 132. This self-aligned characteristic is evident in
In an exemplary embodiment, the spacer 132 and cavities 134 are preferably formed as part of the same overall etch process sequence, but using two distinct steps within that sequence for formation of the spacers 132, followed by formation of the cavities 134. For example, the cavities 134 in the silicon material of region 106 may be created using plasma-based RIE (reactive ion etching), using commonly known etchant chemistries such as, for example, Cl2+HBr, HBr+O2, or Cl2+HBr+O2, which have the advantage of etching silicon with good selectivity to the spacers 132, the gate cap 124, as well as the exposed field oxide region 110. In an exemplary embodiment, the cavities 134 are formed having a depth relative to the surface of the semiconductor material less than the thickness of the semiconductor material 102 such that the underlying insulating material 104 is not exposed. In a preferred embodiment, the cavities 134 are used to define the lateral boundaries of subsequently formed stressor regions. After forming the cavities 134, the second region 108 and gate stack 114 may be unmasked by removing the photoresist layer 130 in a conventional manner.
One or more intermediate process steps may be performed after formation of cavities 134. However, referring now to
Referring now to
In a preferred embodiment, the gate stack 112, spacer 132, photoresist layer 137, and field oxide 110 are also used as an ion implantation mask to form halo implants 142 by appropriately impurity doping the first region 106 in known manner. The halo implants 142 are preferably formed by implanting ions of the same conductivity-determining impurity type as the channel for the first region 106. For a PMOS transistor, the halo implants 142 are formed by implanting N-type ions, preferably arsenic ions, although phosphorus ions could also be used. The halo implants 142 are formed at an angle relative to the surface of the semiconductor device, for example, by ion implantation of dopant ions at an angle, illustrated by arrows 144, and subsequent thermal annealing. Preferably, the angle of implantation is between 20° and 50° relative to the surface normal of the semiconductor device. After forming the source and drain extensions 138 and halo implants 142, the second region 108 and gate stack 114 may be unmasked by removing the photoresist layer 137 in a conventional manner. In a preferred embodiment, after removing the photoresist layer 137, the spacer 132 and gate cap 124 are removed using a single hot phosphoric acid (H3PO4) etchant process. Since the entire wafer is exposed to the etchant chemical, this also results in simultaneous removal of the remaining insulating layer 128 and gate cap 126, eventually leading to the structure as shown in
Referring now to
In accordance with one embodiment, the fabrication process continues by forming spaced-apart source and drain extensions 154 by appropriately impurity doping the second regions 108 in a known manner, for example, by ion implantation of dopant ions, illustrated by arrows 156, and subsequent thermal annealing. Preferably, the source and drain extensions 154 are formed by implanting ions of a conductivity-determining impurity type into the second region 108 using the gate stack 114, offset spacer 150, photoresist layer 152, and field oxide 110 as an implantation mask. The source and drain extensions 154 are formed in the second region 108 by implanting N-type ions (e.g., arsenic ions or phosphorus ions) into the second region 108 using the photoresist layer 152, the gate electrode 122, and offset spacer 150 as an implantation mask. In this regard, the width of the offset spacers 148, 150 (or the thickness of insulating layer 146) may be tuned as desired for the NMOS source and drain extensions 154 without impacting the source and drain extensions 138 of the PMOS transistor, which are formed without the use of offset spacer 148 in the manner described above. Thus, variation in the offset spacer 148 boundary relative to the boundary of the stressor regions 136 does not affect the amount of P-extension diffusion or lead to corresponding variations in the ensuing PFET source/drain extension overlap, since the cavities 134 and source/drain extensions 140 are defined using spacers 132 and thereby ensuring that the PFET source/drain extension implants are self-aligned to the stressor region, as described above.
In a preferred embodiment, the gate stack 114, spacer 150, photoresist layer 152, and field oxide 110 are also used as an ion implantation mask to form halo implants 158 by appropriately impurity doping the second region 108 in known manner. The halo implants 158 are preferably formed by implanting ions of the same conductivity-determining impurity type as the channel for the second region 108. The halo implants 158 are formed at an angle relative to the surface of the semiconductor device, for example, by ion implantation of dopant ions at an angle, illustrated by arrows 160, and subsequent thermal annealing. The layer of photoresist 152 may be subsequently removed, and the semiconductor device may undergo additional processes, such as deep ion implantation, in a conventional manner. For example, although not illustrated, the second region 108 and gate electrode 122 may be masked with a layer of the photoresist, and deep ion implants may be formed in the first region 106 by implanting P-type ions into the source and drain extensions 138 using the gate stack 112 and offset spacer 148 (or another spacer subsequently formed about sidewalls of gate stack 112) as an implantation mask.
In accordance with one embodiment, contact regions 162 are formed on the gate electrodes 120, 122 and on the isolated regions 106, 108 overlying at least part of the source and drain regions of the respective devices (e.g., source and drain extensions 138, 154), as illustrated in
After formation of the contacts, fabrication of the CMOS device can be completed using any number of known process steps, modules, and techniques. These additional steps are well known and, therefore, will not be described here.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the described embodiment or embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope defined by the claims, which includes known equivalents and foreseeable equivalents at the time of filing this patent application.
