1. Field of the invention
The present invention relates to semiconductor packaging technology generally and, more specifically, to a process for forming copper pillars, and a solder layer thereon, on semiconductor devices for flip-chip bonding to it substrate.
2. Description of the Related Art
Copper pillars are a widely used technique for electrically interconnecting a flip-chip semiconductor device or “chip” to conductors on an organic-based substrate, such as a thin (less than one millimeter thick) glass-epoxy board, because copper pillar interconnects have superior geometric control, higher density, and electrical performance relative to solder bump interconnects. The copper pillars on the device's die pads, formed by selectively plating copper onto the die pads, connect to the substrate's substrate pads by using a solder layer between each pillar and the respective substrate pad to join the copper pillars to the substrate pads. Plating is usually used to form the solder layer onto the ends of the copper pillars.
To bond a flip-chip device to a substrate, the device and substrate are brought together and heated until the solder on the ends of the copper pillars melts and wets the substrate pads on the substrate, each pillar and solder combination forming a “joint”. Then the device-substrate combination is cooled down and the solder solidifies to bond the device to the substrate, forming a bonded device-substrate structure or “package”.
In order to insure all substrate-to-die joints are formed during bonding, all of the copper pillars and solder layers on the die before heating are to have the same nominal height. In addition it is generally desirable for all of the joints to have substantially the same diameter. However, having joints with the same diameter might not be desirable in all instances. For example, for carrying a large number of high-speed signals between the chip and the substrate, it might be desirable to use thinner than “normal” diameter joints spaced to provide a high density of signal paths while at the same time providing a desired transmission line characteristic impedance between the joints, e.g., 50 or 100Ω. In other instances where a large current is to be carried by a joint, e.g., a power supply connection, electromigration might with time cause failure of a joint with a normal diameter. To address the high current problem, multiple joints with a normal diameter are placed in parallel or one or more of the joints are formed with a larger or wider diameter than a “normal” joint so that the current density in each joint is less than a maximum amount that would otherwise cause the joint to fail from electromigration. However, using a conventional plating process to make joints with different diameters with substantially uniform height has been problematic. For a given electrochemical plating process and plating bath solution, the mass or volume per unit of time of the plated material is essentially a constant except for any local variations in the bath current density or concentration of all of the plating species in a particular plating bath. As a result, using a conventional electroplating process to form different diameter joints will result in a device with smaller diameter joints that are taller than adjacent larger diameter joints. The uneven joint height might not allow the shorter joints on the device to be completely attached, if at all, to their respective substrate pads, while all of the taller joints will be completely attached, thus causing the completed package to be inoperable or prone to high rates of failure in the field. Further, any warpage of the substrate might exacerbate this situation, possibly increasing the number of partial or incomplete joints.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
Described embodiments include method comprising the steps of providing a wafer having a plurality of flip-chip devices, each flip-chip device having a plurality of die pads thereon; depositing a first layer of photoresist on the wafer; patterning the first layer of photoresist to form a first plurality of openings therein, each of the first openings having a first diameter and exposing a first set of die pads; plating metal into the first openings to form a first metal pillar in each of the first openings for a first time period; patterning the first layer of photoresist to form a second plurality of openings therein, each of the second openings having a second diameter and exposing a second set of die pads; and plating, metal into the first and second openings for a second time period to add to each of the metal pillars in the first openings and form a metal pillar in each of the second openings. The first diameter is greater than the second diameter, and the first set of die pads is different from the second set of die pads. The first and second time periods and plating conditions are chosen such that, after plating metal into the first and second openings for a second time period, each of the pillars in the second openings has substantially the same height as a pillars in each of the first openings.
Other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. The drawings are not to scale.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation”.
As used in this application, the word “exemplary” is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word exemplary is intended to present concepts in a concrete fashion.
The term “or” should be interpreted as inclusive unless stated otherwise. Further, elements in a figure having subscripted reference numbers, e.g., 1001, 1002, . . . 100K, or 100A, 100B, etc. might be collectively referred to herein using a single reference number, e,g 100.
It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps might be included in such methods, and certain steps might be omitted or combined, in methods consistent with various embodiments of the present invention.
Also for purposes of this description, the terms “couple”, “coupling”, “coupled”, “connect”, “connecting”, or “connected” refer to any manner known in the art or later developed in which energy or a signal is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled”, “directly connected”, etc., imply the absence of such additional elements.
The present invention will be described herein in the context of illustrative embodiments of a process to form metal pillars on a flip-chip device that will be bonded to a substrate by joining die pads on the flip-chip device to substrate pads on the substrate using joints of metallic pillars, such as copper pillars, and solder. The pillars and the solder on them are formed by electroplating a metal onto the die pads. According to Faraday's Law, the total amount of metal deposited on a workpiece by electroplating is proportional to the current passed through the workpiece in an electroplating bath the device is immersed in, and the amount of time the current is applied, i.e., the amount of charge (in coulombs) applied to the workpiece. However, the rate at which each pillar is formed is inversely proportional to the surface area of the pillar. Thus, the wider pillars grow more slowly than narrow pillars. To form narrow and wide pillars having approximately the same height, the wide pillars are first partially formed before forming the narrow pillars by using a photoresist layer with two different diameter openings. First, a photoresist layer is deposited on a device and the photoresist is patterned to form a first plurality of openings therein, each of the first openings having a first diameter and exposing a first set of die pads on the device. Next, pillar metal (e.g., copper) is plated into the first openings to form a first metal pillar in each of the first openings for a first time period. Then the photoresist is patterned to form a second plurality of openings therein, each of the second openings having a diameter smaller than the first diameter and exposing a second set of die pads. Then pillar metal is plated into the first and second openings for a second time period to add metal to each of the metal pillars in the first openings and form a metal pillar in each of the second openings. The first and second time periods and plating conditions are chosen such that, after plating metal into the first and second openings for the second time period, each of the pillars in the second openings has substantially the same height as the pillars in each of the first openings. As described below, the solder layers might also be formed by plating solder into the openings and in conjunction with the formation of the pillars.
In this example, the joints 106 are arranged with narrow joints 106N on the right side of the package 100 and wide joints 106W on the left side of the package 100. Generally, power and ground are supplied to the device 100 using the wide joints 106W on the left side of the device 102 and high-speed signals are carded by the narrow joints 106N on the right side of the device 102. It is understood that in various instances, the wide joints carry the high-speed signals and the narrow joints supply power and ground to the device 102. Further, the positions of the wide and narrow joints are greatly simplified for illustrative purposes; typically hundreds of joints are present and power/ground interconnections are generally made in the center of the device 102 while high-speed signals are generally carried by joints near the periphery of the device 102.
Each joint is formed from a metallic pillar 108, such as copper, and a layer of solder 110. For the proper bonding of all the joints between the device 102 and substrate 104, the height of all of the pillars 108 and solder layers 110 prior to bonding should be of uniform height, otherwise when the device 102 is bonded to substrate 104, a gap between some of the solder layers 110 and the respective substrate pad 114 might be so large that during reflow when the device and substrate are heated sufficiently for the solder to melt, balling-up by the solder on the end of the pillar (caused by surface tension of the molten solder) is insufficient to bridge the gap so that the solder does not wet the substrate pad and no electrical/mechanical joint is made.
Referring to
On substrate 104 is a respective one of the substrate pads 114, also typically made of copper, shown aligned with the die pad 212. The substrate copper pad might be coated with another metal such as tin, silver, a nickel-gold eutectic, or solder.
The copper pillar 108 has a height of HP and the solder layer 110 has a height of HS (before melting), and both have an approximate diameter D. The height of the joint is HP+HS so that the total height of the pillar and solder is H. In various embodiments, the height of the joint prior to melting ranges from 5 μm to 130 μm. In one embodiment, the copper pillars have a diameter ranging from approximately 20 μm to approximately 80 μm, a height HP of 20-70 μm, and the solder layers, prior to melting, have a height HS of 10-60 μm so that the total height is approximately 80 μm and might range from 5 μm to 130 μm. However, it is understood that the ratio of the height of the copper pillar to the height of the solder layer before melting can range from 1:10 to 100:1 and the pillar diameter can range from 5-150 μm.
Assuming a possible pillar diameter accuracy of +/−1 μm for openings less than 10 μm, +/−2 μm for openings less than 30 μm, +/−5 for openings less than 50 μm, and +/−7 μm for openings less than 100 μm, and +/−8 μm for openings less than 150 μm, then for the following exemplary ranges in opening diameters, it might be desirable to perform two separate pillar plating steps in accordance with the disclosed embodiments when the exemplary percentage difference between the narrow and wide openings is at least that in the following table:
indicates data missing or illegible when filed
However, it is understood that while the above percentage differences and ranges in opening diameters are merely exemplary, two separate plating steps might still be used were the percentage difference between the narrow and wide openings is less than the above-described amounts.
Next step 304, the barrier/glue layer 216 and the strike layer 218 are deposited over the device 102. These two steps are illustrated in
Returning to
In step 308 of
Next, in step 310, the first photoresist is again patterned but this time forming narrow openings in the first photoresist to expose the narrow die pads while leaving the wide openings intact and the metal layers in the wide openings exposed. Then, in step 312, the wafer is returned to the plating bath and the deposition of the pillar metal into the wide and narrow openings occurs for a second time period until the wide pillars formed in the wide openings and narrow pillars formed in the narrow openings have approximately the same height. Thus, the narrow pillars are formed solely during the second plating step (step 312) while the wide pillars are formed during both the first plating step (step 308) and the second plating step. Because the metal being plated will be deposited more quickly in the narrow openings than in the wide openings, the first time period and the second time period are chosen so that the narrow pillars will reach a second or desired height at approximately the same time the wide pillars reach the desired height during the second plating step. This is illustrated in
As mentioned above, the rate at which a pillar is formed (e.g., in microns per minute) is inversely proportional to the surface area of the pillar. To determine the first and second time periods for steps 308 and 312, respectively, the second time period (t2) is chosen so that the narrow pillars have a second or desired height after the second plating step 312. Assuming that the plating conditions (e.g., plating current) are substantially the same during the first and second plating steps, the first time period, t1, might be calculated as a function of the pillar areas and the second time period:
t1≅t2(AW/AS−1);
where t1 and t2 are the first and second time periods, respectively, AW is the area of each of the wide pillars or that of the wide openings, and AN is the area of the narrow pillars or that of the narrow openings.
It is understood that if the plating conditions are different during the first plating step 308 from that in the second plating step 312, the first time period might be adjusted accordingly. Further, more than two different diameter metal pillars might be made by the above process where the number of plating steps is the same as the number of different diameter metal pillars to be formed and the plating times for the different plating steps are determined substantially in accordance with the above equation.
After the narrow and wide pillars 108W, 108N are formed, then optional solder layers might be formed on the ends of the pillars. Similar the above-described process to form the pillars, in step 314 the wafer is placed in a solder plating bath for a third time period and solder is plated into the narrow and the wide openings in the first photoresist until the solder layer in the narrow openings reaches a desired height above the narrow pillars and then the wafer is removed from the plating bath. As illustrated in
As shown in
Like the above calculation to determine the first time period, the third time period (t3) is chosen so that the narrow solder layers 110N have a desired height HS after the first solder plating step 314. Then, assuming the plating conditions (e.g., plating current) are substantially the same during the first and second solder plating steps, the fourth time period, t4, is determined
t4≅t3(AW/AS−1);
where t3 and t4 are the third and fourth time periods, respectively, AW is the area of each of the wide pillars or that of the wide openings, and AN is the area of the narrow pillars or that of the narrow openings.
Alternatively and assuming the plating conditions (e.g., plating current) are substantially the same during the first and second solder plating steps, t4 can be calculated based on the amount of time T needed to plate the solder layers in the wide openings to the same height as the solder layers in the narrow openings plated in time period t3. Thus t4 is approximately T−t3. However, it is understood that if the plating conditions are different during the first solder plating step 314 from that in the second solder plating step 320, the fourth time period might be adjusted accordingly.
As stated above, the height of the pillars and the solder layer is proportional to the plating current and time used to form them. Knowing the diameter of the opening 502 allows the relatively precise control of the height of the pillars and solder layer during formation with an accuracy of approximately 10% or better.
Next, in step 322 the photoresist layers 504, 704 are removed by ashing using an oxygen plasma or by dipping the device 102 into a chemical stripping bath. Then the conductive layer 216, 218 exposed by the removed photoresist is removed in step 324 by plasma etching or by wet etching. The result is shown in
In step 326, the wafer (not shown) is singulated into multiple devices 102. Then in step 328, each flip-chip device is bonded to a substrate using a conventional flip-chip bonding technique to form the package 100 shown in
Next, in step 330, the final steps to complete the packaging of the bonded device and substrate are done, such as forming an underfill layer between the device and the substrate, adding a heat spreader lid, forming an overmold of epoxy to the device and substrate for environmental protection, testing, package marking, etc.
In an alternative embodiment, instead of applying the solder to the ends of the copper pillars, a layer of solder is deposited on each of the substrate pads 114 by using a patterned solder mask (not shown) on the substrate 104 with the substrate pads exposed and the solder plated onto the exposed pads, using either conventional electroplating, or electroless plating. In this example, the solder layers 110 are not formed and steps 314 through 320 are not performed.
While the embodiments described above entail the formation of wide pillars before narrow pillars, three or more different pillar widths might be formed on a device using the concepts described above.
Although the elements in the following method claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.
It is understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention might be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims.
This application claims the benefit of the filing date of U.S. provisional patent application No. 61/952,963 filed 14 Mar. 2014 as attorney docket no. L14-0124US1, the teachings of which are incorporated herein by reference, and the subject matter of this application is related to U.S. patent application Ser. No. ______, filed concurrently herewith as attorney docket no. L14-0124US1, titled “Method for Fabricating Equal Height Metal Pillars of Different Diameters”, the teachings of which are incorporated herein by reference.
Number | Date | Country | |
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61952963 | Mar 2014 | US |