Patent Application
20250079427
The present application claims the benefit of priority under the Paris Convention to Chinese Patent Application No. 202311115225.7, filed on Aug. 30, 2023, Chinese Patent Application No. 202311110768.X, filed on Aug. 30, 2023, and Chinese Patent Application No. 202311115241.6, filed on Aug. 30, 2023, each of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating fan-out package.
With the rapid development of the semiconductor industry, chip sizes are getting smaller and smaller, while the number and density of signal connections on a chip keep increasing. Conventional packages cannot meet the requirements of the ever-decreasing chip sizes and the ever-increasing number of signal connections. Wafer Level fan-out Packaging (fan-out Wafer Level Package, FOWLP) technology is a chip embedded packaging method for Wafer Level assembly processes, which has been widely applied to the semiconductor assembly industry, as it can bring a lot of advantages for the package with large number of connections and provide flexibility for both design and production.
In the Wafer Level fan-out package process, due to mismatch of Thermal Expansion Coefficients (Coefficient of Thermal Expansion, CTE) between different package materials, wafer warpage often occurs, which adversely impacts packaging efficiency and yield.
To solving the technical problems, the present disclosure provides a method to fabricate fan-out package, which reduces package warpage through a dual side assembly process, thereby reducing the effects caused by warpage.
The present disclosure provides a fabrication method for fan-out package. The method comprises forming packaging layers on opposite sides of a carrier board, the packaging layers including one or more first packaging layers on a first side of the carrier board and one or more second package layers on a second side of the carrier board. The second side is opposite to the first side, the one or more first packaging layers include a first molded package layer, the one or more second packaging layers include a second molded package layer, and at least the first molded package layer embeds one or more semiconductor devices.
In some embodiments, forming packaging layers on opposite sides of a carrier board includes the following steps and processes:
In some embodiments, forming the first bonding layer on the first surface and forming the second bonding layer on the second surface includes:
In some embodiments, forming the molding layer includes:
In some embodiments, forming the molding layer includes:
In some embodiments, attaching the mentioned passive surface of the semiconductor device onto the side surface of the first bonding layer facing away from the supporting carrier and/or onto the side surface of the second bonding layer facing away from the supporting carrier includes:
In some embodiments, the mentioned redistribution layer includes of at least one metal layer and at least one insulator layer, wherein the metal layer corresponds to the insulator layer one by one; the redistribution layer is formed on the side surface of the molding layer facing away from the first bonding layer and the side surface of the molding layer facing away from the second bonding layer, includes:
In some embodiments, after the redistribution layers are formed on both the side surface of the molding layer facing away from the first bonding layer and the side surface of the molding layer facing away from the second bonding layer, the fabrication method further includes:
In some embodiments, the method for removing the supporting carrier includes one of thermal debonding, laser debonding and mechanical debonding.
In some embodiments, after removing the supporting carrier, the fabrication method of fan-out packages further includes:
dicing (or segmenting) at least the first packaging layers to obtain fan-out packages; wherein the saw process includes at least one of dicing saw, laser grooving, and plasma cutting.
In some embodiments, forming packaging layers on opposite sides of a carrier board includes the following steps and processes:
In some embodiments, forming a first bonding layer on the first surface and forming a second bonding layer on the second surface includes:
In some embodiments, after the attaching the active surface of the semiconductor devices to the surface of the side of the first bonding layer facing away from the supporting carrier, the fabrication method further includes:
Attaching a stress balancing device to the surface of the side of the second bonding layer away from the supporting carrier; and the projection of the semiconductor devices are overlapped with the projection of the stresses balance device along the thickness direction of the supporting carrier.
In some embodiments, forming the molding layer includes:
Forming the molding layer by using a compression molding or a transfer molding process.
In some embodiments, after forming of the molding layer, the fabrication method further includes:
Forming a groove on the surface of the side of the molding layer, which is away from the first bonding layer; the grooves are used for releasing stresses.
In some embodiments, forming a groove on a surface of the molding layer facing away from the first bonding layer includes:
And forming the groove on the surface of the side of the molding layer, which is away from the first bonding layer, between two adjacent semiconductor devices.
In some embodiments, the forming the groove on a surface of a side, facing away from the first bonding layer, of the molding layer between two adjacent semiconductor devices includes:
And along the thickness direction of the molding layer, the depth of the groove is smaller than or equal to ½ of the thickness of the molding layer.
In some embodiments, after forming of the molding layer, the method for removing the supporting carrier includes one of thermal debonding, laser debonding and mechanical debonding to expose the active surface of the semiconductor devices.
In some embodiments, the fabrication method further comprises:
In some embodiments, forming packaging layers on opposite sides of a carrier board includes the following steps and processes:
In some embodiments, a first redistribution layer includes at least one metal layer and at least one insulator layer; a second redistribution layer comprises at least one metal layer and at least one insulator layer; the first redistribution layer is formed on one side of the first bonding layer, which is away from the supporting carrier, and the second redistribution layer is formed on one side of the second bonding layer, which is away from the supporting carrier, and the redistribution layer comprises:
In some embodiments, forming a first bonding layer on the first surface and forming a second bonding layer on the second surface includes: forming the bonding layer by adopting a taping process; or, forming the bonding layer by adopting a coating process; and further includes curing the bonding layer formed by the coating process.
In some embodiments, attaching an active face of the semiconductor devices to the first redistribution layer and/or the second redistribution layer includes:
In some embodiments, attaching an active face of the semiconductor devices to the first redistribution layer and/or the second redistribution layer includes:
In some embodiments, forming the molding layer includes:
In some embodiments, the fabrication method further comprises:
In some embodiments, forming a groove on a surface of the molding layer facing away from the supporting carrier includes:
In some embodiments, forming a groove on a surface of a side, facing away from the supporting carrier, of the molding layer between two adjacent semiconductor devices includes:
Along the thickness direction of the molding layer, the depth of the groove is smaller than or equal to ½ of the thickness of the molding layer.
In some embodiments, after forming of the molding layer, the fabrication method further includes:
Removing the supporting carrier and the bonding layer by adopting one of thermal debonding, laser debonding and mechanical debonding.
Compared with the current technology, the technical scheme provided by the disclosure has the following advantages.
In some embodiments, the fabrication method of fan-out packages provided by the disclosure comprises the following steps: providing a supporting carrier; the supporting carrier comprises a first surface and a second surface which are at opposite sides of the supporting carrier; forming a first bonding layer on the first surface and forming a second bonding layer on the second surface; providing a semiconductor device, and attaching a passive surface of the semiconductor device onto a side surface of the first bonding layer facing away from the supporting carrier and/or a side surface of the second bonding layer facing away from the supporting carrier; forming a molding layer; the molding layer wraps the semiconductor device and exposes the active surface of the semiconductor device, the molding layer also covers the surface of the first bonding layer facing away from the supporting carrier and the surface of the second bonding layer facing away from the supporting carrier which are not covered by the semiconductor device; a redistribution layer is formed on both the side surface of the molding layer facing away from the first bonding layer and the side surface of the molding layer facing away from the second bonding layer; the redistribution layer is electrically connected to the active surface of the semiconductor device. Therefore, the fabrication method for fan-out packages, in which the same packaging material layer (including a bonding layer, a molding layer and a redistribution layer) is formed on both the upper and lower sides of the supporting carrier by using a Dual-sided Carrier packaging method, and the stress generated by the packaging material layer on the upper surface is opposite to the stress generated by the packaging material layer on the lower surface, and the two stresses are similar or equal in size, and can offset each other, reducing the degree of warpage or even eliminating warpage, which is beneficial to improve packaging efficiency and yield.
In some embodiments, the fabrication method of fan-out packages provided by the disclosure comprises the following steps: providing a supporting carrier; the supporting carrier comprises a first surface and a second surface which are at opposite sides of the supporting carrier; forming a first bonding layer on the first surface and forming a second bonding layer on the second surface; providing the semiconductor devices, and attaching a passive surface of the semiconductor devices onto a side surface of the first bonding layer facing away from the supporting carrier; forming a molding layer; the molding layer covers the semiconductor devices and the surface of the first bonding layer facing away from the supporting carrier that is not covered by the semiconductor devices and the second bonding layer facing away from the supporting carrier. Therefore, the fabrication method for fan-out packages, in which the same packaging material layer is formed on both the upper and lower sides of the supporting carrier by using a Dual-sided Carrier packaging method, and the stresses generated by the packaging material layer on the upper surface are opposite to the stresses generated by the packaging material layer on the lower surface, and the two stresses are similar or equal in size, and can offset each other, reducing the warpage degree or even eliminating warpage, which is beneficial to improve packaging efficiency and yield.
In some embodiments, the fabrication method of the fan-out package provided by the disclosure comprises the following steps: providing a supporting carrier; the supporting carrier comprises a first surface and a second surface which are oppositely arranged; forming a first bonding layer on the first surface and forming a second bonding layer on the second surface; forming a first redistribution layer on one side of the first bonding layer, which is away from the supporting carrier, and forming a second redistribution layer on one side of the second bonding layer, which is away from the supporting carrier; providing a semiconductor devices and attaching an active face of the semiconductor devices to the first and/or second redistribution layers; forming a molding layer; the molding layer embeds the semiconductor devices and also covers the surface, which is not covered by the semiconductor devices, of the side surface of the first redistribution layer, which is away from the first bonding layer, and the side surface of the second redistribution layer, which is away from the second bonding layer. Therefore, the fabrication method for fan-out packages, in which the same packaging material layer (including a bonding layer, a redistribution layer and a molding layer) is formed on both the upper and lower sides of the supporting carrier by using a Dual-sided Carrier packaging method, and the stress generated by the packaging material layer on the upper surface is opposite to the stress generated by the packaging material layer on the lower surface, and the two stresses are similar or equal in size, and can offset each other, reducing the degree of warpage or even eliminating warpage, which is beneficial to improve the packaging efficiency and yield.
The fabrication method of the fan-out package provided by the disclosure comprises the following steps: providing a supporting carrier; the supporting carrier comprises a first surface and a second surface which are oppositely arranged; forming a first bonding layer on the first surface and forming a second bonding layer on the second surface; forming a first redistribution layer on one side of the first bonding layer, which is away from the supporting carrier, and forming a second redistribution layer on one side of the second bonding layer, which is away from the supporting carrier; providing a semiconductor devices and attaching an active face of the semiconductor devices to the first and/or second redistribution layers; forming a molding layer; the molding layer embeds the semiconductor devices and also covers the surface, which is not covered by the semiconductor devices, of the side surface of the first redistribution layer, which is away from the first bonding layer, and the side surface of the second redistribution layer, which is away from the second bonding layer. Therefore, the fabrication method for fan-out packages, in which the same packaging material layer (including a bonding layer, a redistribution layer and a molding layer) is formed on both the upper and lower sides of the supporting carrier by using a Dual-sided Carrier packaging method, and the stress generated by the packaging material layer on the upper surface is opposite to the stress generated by the packaging material layer on the lower surface, and the two stresses are similar or equal in size, and can offset each other, reducing the degree of warpage or even eliminating warpage, which is beneficial to improve the packaging efficiency and yield.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments includeent with the disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior technologies, the drawings that are required for the description of the embodiments or the prior technologies will be briefly described below, and it will be obvious to those skilled in the technologies that other drawings can be obtained from these drawings without inventive efforts.
According to some embodiments, the following reference numerals are used to denote certain components/layers in the drawings:
In order that more clearly understand the above-mentioned objects, features and advantages of the present disclosure, a further description of the solutions of the present disclosure will be discussed below. It should be noted that, if there is no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, however, the present disclosure may also be implemented in other ways than described herein; it will be obvious that the embodiments in the description are only part of the embodiments of the present disclosure, and not all examples.
The following describes an exemplary fabrication method for manufacturing a fan-out package according to an embodiment of the present disclosure with reference to the accompanying drawings.
S110A, providing a supporting carrier.
In some embodiments, the supporting carrier 1 is used for fixing and supporting the package; the supporting carrier 1 can be selected from all types of carriers known to those skilled in the technologies, such as a glass carrier or a stainless steel carrier and so on, which is not limited herein. The supporting carrier 1 comprises a first surface 11 and a second surface 12 which are oppositely arranged, and the first surface 11 and the second surface 12 are both flat surfaces.
S120A, forming a first bonding layer on the first surface and forming a second bonding layer on the second surface. In this step, as shown in
It should be noted that the thickness of the first bonding layer 21 is equal to the thickness of the second bonding layer 22, or the difference between the thickness of the layer 21 and the thickness of the second bonding layer 22 is less than the preset threshold. which is not limited herein.
In some embodiments, “forming a first bonding layer on a first surface and a second bonding layer on a second surface” includes the steps of:
And forming a first bonding layer and a second bonding layer by adopting taping process.
In some embodiments, adhesive films (e.g., Dual-sided tape) are adhered to the first surface 11 and the second surface 12 of the supporting carrier 1, i.e., the first bonding layer 21 and the second bonding layer 22 are formed; the bonding surface is exposed by removing the backing paper, and the attachment of the semiconductor device 3 and the supporting carrier 1 can be completed by connecting the passive surface of the semiconductor device 3 with the bonding surface, which is easy to operate.
In some embodiments, forming a first bonding layer on a first surface of a supporting carrier and a second bonding layer on a second surface of the supporting carrier includes the steps of:
In this embodiment, the raw material for preparing the first bonding layer 21 and the second bonding layer 22 is underfill epoxy, which is in a viscous fluid state and has certain fluidity. Firstly, coating underfill epoxy layers with a preset thickness on the first surface 11 and the second surface 12 of the supporting carrier 1, that is a first bonding layer 21 and a second bonding layer 22; and then the first bonding layer 21 and the second bonding layer 22 are baked to optimize the adhesion of the first bonding layer 21 and the second bonding layer 22, both to ensure that the semiconductor device 3 is not disconnected to the supporting carrier during the packaging process and to ensure that the semiconductor device 3 and the packaging material layer in connect to the supporting carrier 1 are not damaged when the supporting carrier 1 is subsequently removed.
And S130A, providing the semiconductor device, and attaching the passive surface of the semiconductor device to the one side surface of the first bonding layer, which faces away from the supporting carrier, and/or the one side surface of the second bonding layer, which faces away from the supporting carrier. Wherein, the semiconductor device 3 includes, but is not limited to, a die, a chip, and a wafer. The semiconductor device 3 includes a passive surface and an active surface that are disposed opposite to each other, and the active surface is provided with bonding sites and is electrically connected to the redistribution layer 5 prepared in the subsequent step S140A.
In this embodiment, the packaging method adopted by Face-up, the passive surface of the semiconductor device 3 faces the bonding layer 2, and the active surface of the semiconductor device 3 faces away from the bonding layer 2, that is the active surface of the semiconductor device 3 faces outside. The semiconductor device 3 can be attached only on the side surface of the first bonding layer 21 facing away from the supporting carrier 1, the semiconductor device 3 can also be attached only on the side surface of the second bonding layer 22 facing away from the supporting carrier 1, alternatively, the semiconductor device 3 can be attached to both the first bonding layer 21 and the second bonding layer 22 on the side surfaces facing away from the supporting carrier 1.
S140, forming a molding layer.
In this embodiment, the molding layer 4 wraps the semiconductor device 3 and exposes the active surface of the semiconductor device 3, and the molding layer 4 also covers the surface of the first bonding layer 21 and the second bonding layer 22 on the side facing away from the supporting carrier 1 that is not covered by the semiconductor device 3. The molding layer 4 can be made of materials such as Molding Compound (MC) or liquid or powder epoxy resin and other materials.
In other embodiments, the molding layer 4 can also be made of a half-cure material, which includes one or a combination of one or more of epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, etc.
S150A, forming a redistribution layer on one side surface of the molding layer faces away from the first bonding layer, and one side surface of the molding layer faces away from the second bonding layer.
In some embodiments, the redistribution layer 5 comprises at least one patterned metal layer and at least one isolating layer, and is made of a metal material with good conductivity, including but not limited to copper, titanium, gold, silver, aluminum and tin; the redistribution layer 5 is electrically connected to the active surface of the semiconductor device 3.
According to the different warpage directions, the type of warpage can be classified into “smiling face warpage” (as shown in
It should be noted that during the packaging process, the semiconductor device 3 has very little impact on warpage, and therefore, the semiconductor device can be selectively attached to one side surface or both side surfaces of the supporting carrier 1 according to the need. The bonding layer 2, the molding layer 4 and the redistribution layer 5 are limited by the fabrication process and the materials used, the influence on the wafer warpage is very large, and the bonding layer, the molding layer 4 and the redistribution layer 5 are required to be arranged on the upper surface and the lower surface of the supporting carrier 1.
In some embodiments, as shown in
In some embodiments, as shown in
The fabrication method of the fan-out package provided by the embodiment of the disclosure comprises the following steps: providing a supporting carrier 1; wherein, the supporting carrier 1 comprises a first surface 11 and a second surface 12 which are oppositely arranged; forming a first bonding layer 21 on the first surface 11 and a second bonding layer 22 on the second surface 12; providing a semiconductor device 3 and attaching the passive face of the semiconductor device 3 to a side surface of the first bonding layer 21 facing away from the supporting carrier 1 and/or a side surface of the second bonding layer 22 facing away from the supporting carrier 1; forming a molding layer 4; the molding layer 4 wraps the semiconductor device 3 and exposes the active surface of the semiconductor device 3, and the molding layer 4 also covers the surface of the first bonding layer 21, which faces away from the supporting carrier 1, and the surface of the second bonding layer 22, which faces away from the supporting carrier 1 and is not covered by the semiconductor device 3; a redistribution layer 5 is formed on the surface of one side of the molding layer 4, which faces away from the first bonding layer 21, and the surface of one side of the molding layer 4, which faces away from the second bonding layer 22; the redistribution layer 5 is electrically connected to the active surface of the semiconductor device 3. Therefore, the same packaging material layers (comprising the bonding layer 2, the redistribution layer 4 and the redistribution layer 5) are formed on the upper surface and the lower surface of the supporting carrier 1 simultaneously in a Dual-sided packaging mode, the stress generated by the packaging material layers on the upper surface is opposite to the stress generated by the packaging material layers on the lower surface, the sizes of the stress and the stress are similar or equal, the stress and the stress are mutually offset, the warpage degree is reduced, even the warpage is eliminated, and further the packaging efficiency and the yield are improved.
In some embodiments, as shown in
S231, forming a molding layer on the surface of one side of the first bonding layer, which is away from the supporting carrier, and the surface of one side of the second bonding layer, which is away from the supporting carrier.
In combination with the third step of
S232, back grinding the molding layer to expose the active surface of the semiconductor device.
In combination with the fourth step of
In some embodiments, “forming a molding layer” includes the steps of:
Forming the molding layer by using a compression molding or a transfer molding process.
Wherein, the material of the molding layer can be one or a combination of more of packaging molding material (Molding Compound, MC), epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane and ceramic. The molding layer is prepared by adopting compression molding and transfer molding processes, the molding material is pressurized and heated, the molding material is plasticized and flows to fill the die cavity, the molding material is cured after undergoing a crosslinking reaction, and the temperature, the pressure and the time are strictly controlled in the process.
In other embodiments, the molding layer may also be prepared using all processes known to those skilled in the technologies, such as injection molding, transfer molding and compression molding, which are not limited here.
In some embodiments, “attaching the passive face of the semiconductor device to a side surface of the first bonding layer facing away from the supporting carrier and/or a side surface of the second bonding layer facing away from the supporting carrier” comprises the steps of:
In some embodiments, along the thickness direction of the molding layer, the projection of the semiconductor device attached to the first bonding layer overlaps with the projection of the semiconductor device attached to the second bonding layer.
In the present embodiment, as shown in
In other embodiments, the semiconductor device 3 may be attached to one side of the supporting carrier 1, and the stress balance device may be attached to the other side, where the semiconductor device 3 and the stress balance device are symmetrically distributed on the upper and lower surfaces of the supporting carrier; wherein the dimensions and materials of the stress balance device and the semiconductor device 3 are the same.
In some embodiments, the redistribution layer includes at least one metal layer and at least one isolating layer, where the metal layer and the isolating layer are in one-to-one correspondence; the step of forming a redistribution layer on both the side surface of the molding layer, which faces away from the first bonding layer, and the side surface of the molding layer, which faces away from the second bonding layer, comprises the following steps:
And forming a metal layer and an isolating layer alternately in sequence on one side surface of the molding layer, which is away from the first bonding layer, and one side surface of the molding layer, which is away from the second bonding layer, until all metal layers and all isolating layers of the redistribution layer are formed on one side surface of the molding layer, which is away from the first bonding layer, and all metal layers and all isolating layers of the redistribution layer are formed on one side surface of the molding layer, which is away from the second bonding layer.
In some embodiments, as shown in
It should be noted that, all processes known to those skilled in the technologies are used to prepare the patterned metal layer, such as photolithography+sputtering+electroplating processes, which are not described herein.
In some embodiments, after forming the redistribution layer on both the side surface of the molding layer facing away from the first bonding layer and the side surface of the molding layer facing away from the second bonding layer, the method further includes the steps of:
Forming a connection structure on the surface of one side of the redistribution layer, which is away from the semiconductor device;
In some embodiments, connection structure is connected to the redistribution layer electricity, and connection structure is used for connecting external device.
In some embodiments, as shown in
It should be noted that
It should be noted that
In some embodiments, the method of making further comprises:
And the method for removing the supporting carrier includes one of thermal debonding, laser debonding and mechanical debonding.
In some embodiments, the mode of removing the supporting carrier can be selected according to the type of the supporting carrier. For example, if the supporting carrier is a glass carrier or other light-transmitting carrier, the composite carrier may be removed by any one of thermal debonding, mechanical debonding and laser debonding; if the supporting carrier is a stainless steel carrier or other opaque carrier, a thermal debonding or mechanical debonding is used to remove the composite carrier.
In some embodiments, after removing the support carrier, the method of preparing the fan-out package further comprises:
In some embodiments, the saw process includes at least one of dicing saw, dicing blades, laser grooving, and plasma cutting. In connection with the last step of
S110B, providing a supporting carrier.
In some embodiments, the supporting carrier 1 is used for fixing and supporting the package; the supporting carrier 1 can be selected from all types of carriers known to those skilled in the technologies, such as a glass carrier or a stainless steel carrier and so on, which is not limited herein. The supporting carrier 1 comprises a first surface 11 and a second surface 12 which are oppositely arranged, and the first surface 11 and the second surface 12 are both flat surfaces.
S120B, forming a first bonding layer on the first surface and forming a second bonding layer on the second surface.
In this step, as shown in
It should be noted that the thickness of the first bonding layer 21 is equal to the thickness of the second bonding layer 22, or the difference between the thickness of the layer 21 and the thickness of the second bonding layer 22 is less than the preset threshold. which is not limited herein.
In some embodiments, “forming a first bonding layer on a first surface and a second bonding layer on a second surface” includes the steps of:
And forming a first bonding layer and a second bonding layer by adopting a taping process.
In some embodiments, adhesive films (e.g., Dual-sided tape) are adhered to the first surface 11 and the second surface 12 of the supporting carrier 1, i.e., the first bonding layer 21 and the second bonding layer 22 are formed; the bonding surface is exposed by removing the backing paper, and the attachment of the semiconductor device 3 and the supporting carrier 1 can be completed by connecting the passive surface of the semiconductor device 3 with the bonding surface, which is easy to operate.
In some embodiments, forming a first bonding layer on a first surface of a supporting carrier and a second bonding layer on a second surface of the supporting carrier includes the steps of:
In this embodiment, the raw material for preparing the first bonding layer 21 and the second bonding layer 22 is underfill epoxy, which is in a viscous fluid state and has certain fluidity. Firstly, coating underfill epoxy layers with a preset thickness on the first surface 11 and the second surface 12 of the supporting carrier 1, that is a first bonding layer 21 and a second bonding layer 22; and then the first bonding layer 21 and the second bonding layer 22 are baked to optimize the adhesion of the first bonding layer 21 and the second bonding layer 22, both to ensure that the semiconductor device 3 is not disconnected to the supporting carrier during the packaging process and to ensure that the semiconductor device 3 and the packaging material layer in connect to the supporting carrier 1 are not damaged when the supporting carrier 1 is subsequently removed.
In the process of preparing the bonding layer 2, the bonding layer 2 needs to be baked or heated, the materials are heated to generate stresses, in order to balance the stresses, the bonding layer 2 is formed on the upper surface and the lower surface of the supporting carrier 1, the directions of the stresses generated by the first bonding layer 21 and the stress generated by the second bonding layer 22 are opposite, equal or similar, and the stresses can be offset each other, so that the warpage is reduced.
And S130B, providing the semiconductor devices, and attaching the active surface of the semiconductor devices to the surface of the side, facing away from the supporting carrier, of the first bonding layer.
In this embodiment, the semiconductor device 3 includes, but is not limited to, a die, a chip, and a wafer. The semiconductor device 3 includes a passive surface and an active surface that are disposed opposite to each other, and the active surface is provided with bonding sites and is electrically connected to the redistribution layer 5 prepared in the subsequent step.
In this embodiment, the packaging method adopted by Face-down, the active surface of the semiconductor device 3 faces the first bonding layer 21, and the passive surface of the semiconductor device 3 faces away from the first bonding layer 21, i.e. the active surface of the semiconductor device 3 faces the inner side. Illustratively, as shown in
In this embodiment, the molding layer 4 wraps the semiconductor device 3 and exposes the active surface of the semiconductor device 3, and the molding layer 4 also covers the surface of the first bonding layer 21 and the second bonding layer 22 on the side facing away from the supporting carrier 1 that is not covered by the semiconductor device 3. The molding layer 4 can be made of materials such as Molding Compound (MC) or liquid or powder epoxy resin and other materials.
In other embodiments, the molding layer 4 can also be made of a half-cure material, which includes one or a combination of one or more of epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, etc.
According to the different warpage directions, the type of warpage can be classified into “smiling face warpage” (as shown in
It should be noted that during the packaging process, the semiconductor device 3 has very little impact on warpage, and therefore, the semiconductor devices can be selectively attached to one side surface or both side surfaces of the supporting carrier 1 according to the need. The bonding layer 2 and the molding layer 4 are limited by the fabrication process and the materials used, the influence on the wafer warpage is very large, and the bonding layer and the molding layer 4 are required to be arranged on the upper surface and the lower surface of the supporting carrier 1.
In some embodiments, as shown in
The fabrication method of the fan-out package provided by the disclosure comprises the following steps: providing a supporting carrier 1; wherein, the supporting carrier 1 comprises a first surface 11 and a second surface 12 which are oppositely arranged; forming a first bonding layer 21 on the first surface 11 and a second bonding layer 22 on the second surface 12; providing a semiconductor device 3 and attaching an active face of the semiconductor device 3 to a side surface of the first bonding layer 21 facing away from the supporting carrier 1; forming a molding layer 4; the molding layer 4 covers the semiconductor device 3, and also covers the surface of the side of the first bonding layer 21 facing away from the supporting carrier 1, which is not covered by the semiconductor device 3, and the surface of the side of the second bonding layer 22 facing away from the supporting carrier 1. Therefore, the bonding layer 2 and the molding layer 4 are formed on the upper surface and the lower surface of the supporting carrier 1 simultaneously in a Dual-sided packaging mode, the stresses generated by the bonding layer 2 and the molding layer 4 on the upper surface are opposite to the stresses generated by the bonding layer 2 and the molding layer 4 on the lower surface, the sizes of the stresses and the stresses are similar or equal, the stresses and the stresses offset each other, the warpage degree is reduced, even the warpage is eliminated, and the packaging efficiency and the yield are improved.
In some embodiments, after “attaching an active face of the semiconductor devices to the side surface of the first bonding layer facing away from the supporting carrier”, the method of preparing further comprises:
In the present embodiment, as shown in
It should be noted that, since the package which is including the stresses balance device is eventually discarded, the precision requirement and the fabrication difficulty are reduced, which is beneficial to improve the packaging efficiency.
In some embodiments, “forming a molding layer” includes the steps of:
Forming the molding layer by using a compression molding or a transfer molding process.
Wherein, the material of the molding layer can be one or a combination of more of packaging molding material (Molding Compound, MC), epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane and ceramic. The molding layer is prepared by adopting compression molding and transfer molding processes, the molding material is pressurized and heated, the molding material is plasticized and flows to fill the die cavity, the molding material is cured after undergoing a crosslinking reaction, and the temperature, the pressure and the time are strictly controlled in the process.
In other embodiments, the molding layer may also be prepared using all processes known to those skilled in the technologies, such as injection molding, transfer molding and compression molding, which are not limited here.
In some embodiments, the method of making further comprises:
Forming a groove on the surface of the side of the molding layer, which is away from the first bonding layer; the grooves are used for releasing stresses.
Referring to
In this embodiment, the groove 41 may be formed using one of in-mold ribs, mechanical saw, or etching processes. When the groove 41 is formed by adopting the mold inner rib process, the inner rib is required to be arranged at the corresponding position in the mold for preparing the molding layer 4, so that the molding layer 4 and the groove 41 are simultaneously formed by one process, thereby being beneficial to save the process and improve the packaging efficiency. When the groove is formed by a mechanical saw or etching process, it is necessary to form the groove 41 at a corresponding position of the molding layer by using a saw device or an etching device after forming the molding layer 4, and thus, the surface of the formed groove 41 is smooth and has high accuracy.
It should be noted that
In some embodiments, forming a groove in a surface of a side of the molding layer facing away from the first bonding layer includes the steps of:
Forming a groove on the surface of the side of the molding layer between two adjacent semiconductor devices, which faces away from the first bonding layer.
In some embodiments, the projection of the groove 41 is located between the projections of the adjacent two semiconductor devices 3 in the thickness direction of the molding layer 4. Illustratively, as shown in
It should be noted that
In some embodiments, forming a groove in a side surface of the molding layer between two adjacent semiconductor devices facing away from the first bonding layer includes the steps of:
Along the thickness direction of the molding layer, the depth of the groove is less than or equal to ½ thickness of the molding layer.
In this embodiment, as shown in
It should be noted that, the embodiment of the present disclosure only exemplarily illustrates that the depth of the groove 41 is less than or equal to the preset depth, and the preset depth is ½ of the thickness of the molding layer 4 (i.e., ½H), but the method for manufacturing the fan-out package provided by the embodiment of the present disclosure is not limited. In other embodiments, the preset depth may be greater than ½H, or less than ½H, or a specific value, which is not limited herein.
In some embodiments, after “forming the molding layer,” the method of making further comprises:
Removing the supporting carrier by using one of thermal debonding, laser debonding and mechanical debonding to expose the active surface of the semiconductor devices.
In some embodiments, the mode of removing the supporting carrier can be selected according to the type of the supporting carrier. For example, if the supporting carrier is a glass carrier or other light-transmitting carrier, the composite carrier may be removed by any one of thermal debonding, mechanical debonding and laser debonding; if the supporting carrier is a stainless steel carrier or other opaque carrier, a thermal debonding or mechanical debonding is used to remove the composite carrier. After the supporting carrier 1 and the bonding layer 2 are removed in this step, the surface of the side where the molding layer 4 is originally attached to the bonding layer 2 is exposed, and the surface also exposes the active surface of the semiconductor device 3.
In some embodiments, the method of making further comprises:
Forming an interconnection structure on the surface of the side of the molding layer, which is exposed out of the active surface; the interconnection structure is electrically connected to the active surface and is used for connecting an external device.
The interconnection structure at least comprises a redistribution layer 5, In some embodiments, the redistribution layer 5 comprises at least one patterned metal layer and at least one insulator layer, and metal materials with good conductivity are selected from copper, titanium, gold, silver, aluminum and tin; the redistribution layer 5 is electrically connected to the active surface of the semiconductor device 3.
In some embodiments, as shown in
It should be noted that
In some embodiments, the method of making further comprises:
dicing (or segmenting) at least the first packaging layers to obtain fan-out packages;
In some embodiments, the saw process includes at least one of dicing saw, dicing blades, laser grooving, and plasma cutting. In connection to the last step of
S110C, providing a supporting carrier.
In some embodiments, the supporting carrier 1 is used for fixing and supporting the package; the supporting carrier 1 can be selected from all types of carriers known to those skilled in the technologies, such as a glass carrier or a stainless steel carrier and so on, which is not limited herein. The supporting carrier 1 comprises a first surface 11 and a second surface 12 which are oppositely arranged, and the first surface 11 and the second surface 12 are both flat surfaces.
S120C, forming a first bonding layer on the first surface of the supporting carrier and forming a second bonding layer on the second surface of the supporting carrier.
In this step, as shown in
It should be noted that the thickness of the first bonding layer 21 is equal to the thickness of the second bonding layer 22, or the difference between the thickness of the layer 21 and the thickness of the second bonding layer 22 is less than the preset threshold. which is not limited herein.
In some embodiments, “forming a first bonding layer on a first surface and a second bonding layer on a second surface” includes the steps of:
And forming a first bonding layer and a second bonding layer by adopting a taping process.
In some embodiments, adhesive films (e.g., Dual-sided tape) are adhered to the first surface 11 and the second surface 12 of the supporting carrier 1, i.e., the first bonding layer 21 and the second bonding layer 22 are formed; the bonding surface is exposed by removing the backing paper, and the attachment of the semiconductor device 3 and the supporting carrier 1 can be completed by connecting the passive surface of the semiconductor device 3 with the bonding surface, which is easy to operate.
In some embodiments, forming a first bonding layer on a first surface of a supporting carrier and a second bonding layer on a second surface of the supporting carrier includes the steps of:
In this embodiment, the raw material for preparing the first bonding layer 21 and the second bonding layer 22 is underfill epoxy, which is in a viscous fluid state and has certain fluidity. Firstly, coating underfill epoxy layers with a preset thickness on the first surface 11 and the second surface 12 of the supporting carrier 1, that is a first bonding layer 21 and a second bonding layer 22; and then the first bonding layer 21 and the second bonding layer 22 are baked to optimize the adhesion of the first bonding layer 21 and the second bonding layer 22, both to ensure that the semiconductor device 3 is not disconnected to the supporting carrier during the packaging process and to ensure that the semiconductor device 3 and the packaging material layer in connect to the supporting carrier 1 are not damaged when the supporting carrier 1 is subsequently removed.
In the process of preparing the bonding layer 2, the bonding layer 2 needs to be baked or heated, the materials are heated to generate stress, in order to balance the stress, the bonding layer 2 is formed on the upper surface and the lower surface of the supporting carrier 1, the directions of the stress generated by the first bonding layer 21 and the stress generated by the second bonding layer 22 are opposite, equal or similar, and the stress can be offset each other, so that the warpage is reduced.
S130C, forming a first redistribution layer on one side of the first bonding layer, which is away from the supporting carrier, and forming a second redistribution layer on one side of the second bonding layer, which is away from the supporting carrier.
A first redistribution layer 51 and a second redistribution layer 52 each include at least one patterned metal layer and at least one insulator layer, and are made of a metal material with good conductivity, including but not limited to copper, titanium, gold, silver, aluminum, tin, and the like. The thickness of the first and second redistribution layers 51 and 52 are equal, or the difference in thickness between them is less than a preset threshold.
S140C, providing semiconductor devices, and attaching an active surface of the semiconductor devices to the first and/or second redistribution layers.
In this embodiment, a semiconductor device 3 includes, but is not limited to, a die, a chip, and a wafer. The semiconductor devices 3 includes a passive face and an active face that are disposed opposite to each other, the active face being provided with bonding sites. The active surface of the semiconductor devices 3 is attached to the first and/or second redistribution layers 51 and 52 by thermocompression bonding (Thermal Compress Bonding, TCB), Die Attach (DA), or Surface Mount (Surface Mount Technology, SMT), thereby achieving electrical interconnection of the semiconductor devices 3 to the first and/or second redistribution layers 51 and 52. The semiconductor devices 3 may be attached only to the first redistribution layer 51, the semiconductor devices 3 may also be attached only to the second redistribution layer 52, or the semiconductor devices 3 may be attached to both the first redistribution layer 51 and the second redistribution layer 52.
S150C, forming a molding layer.
In this embodiment, a molding layer 4 embeds the semiconductor devices 3 and also covers a surface of the first redistribution layer 51 facing away from the first bonding layer 21 and a surface of the second redistribution layer 52 facing away from the second bonding layer 22, which is not covered by the semiconductor devices 3. The thickness of the molding layer 4 on the first redistribution layer 51 is equal to the thickness of the molding layer 4 on the second redistribution layer 52, or the difference between the two thicknesses is smaller than a preset threshold.
In other embodiments, the molding layer 4 can also be made of a half-cure material, which includes one or a combination of one or more of epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane, etc.
In other embodiments, the packaging method adopted by RDL-first, and the bonding layer 2 and the redistribution layer 5 are formed on both sides of the support carrier, that is, the first bonding layer 21 and the first redistribution layer 51 are sequentially formed on the first surface 11 of the support carrier 1, the second bonding layer 22 and the second redistribution layer 52 are sequentially formed on the second surface 12, then the semiconductor devices 3 is fixed, and then the molding layer 4 is formed on both the redistribution layers 5.
According to the different warpage directions, the type of warpage can be classified into “smiling face warpage” (as shown in
It should be noted that during the packaging process, the semiconductor device 3 has very little impact on warpage, and therefore, the semiconductor device can be selectively attached to one side surface or both side surfaces of the supporting carrier 1 according to the need. The bonding layer 2, the molding layer 4 and the redistribution layer 5 are limited by the fabrication process and the materials used, the influence on the wafer warpage is very large, and the bonding layer 2, the molding layer 4 and the redistribution layer 5 are required to be arranged on the upper surface and the lower surface of the supporting carrier 1.
In some embodiments, As shown in
In some embodiments, As shown in
The fabrication method of the fan-out package provided by the embodiment of the disclosure comprises the following steps: providing a supporting carrier 1; wherein, the supporting carrier 1 comprises a first surface 11 and a second surface 12 which are oppositely arranged; forming a first bonding layer 21 on the first surface 11 and a second bonding layer 22 on the second surface 12; forming a first redistribution layer 51 on a side of the first bonding layer 21 facing away from the support carrier 1, and forming a second redistribution layer 52 on a side of the second bonding layer 22 facing away from the support carrier 1; providing a semiconductor devices 3 and attaching an active face of the semiconductor devices 3 to the first and/or second redistribution layers 51, 52; forming a molding layer 4; the molding layer 4 covers the semiconductor devices 3 and also covers the surface of the first redistribution layer 51 that is not covered by the semiconductor devices 3, of the side surface facing away from the first bonding layer 21 and the side surface of the second redistribution layer 52 that is facing away from the second bonding layer 22. Therefore, the same packaging material layers (comprising the bonding layer 2, the redistribution layer 5 and the molding layer 4) are formed on the upper surface and the lower surface of the supporting carrier 1 simultaneously in a Dual-sided packaging mode, and the stresses generated by the packaging material layers on the upper surface and the stresses generated by the packaging material layers on the lower surface are opposite in direction and similar or equal in size, and offset with each other, so that the warpage degree is reduced, even the warpage is eliminated, and the packaging efficiency and the yield are improved.
In some embodiments, a first redistribution layer includes at least one metal layer and at least one insulator layer; a second redistribution layer comprises at least one metal layer and at least one insulator layer; forming the first redistribution layer on a side of the first bonding layer facing away from the supporting carrier, and forming the second redistribution layer on a side of the second bonding layer facing away from the supporting carrier, including:
Forming a metal layer and an insulator layer alternately in sequence on one side of the first bonding layer, which is away from the supporting carrier, and one side of the second bonding layer, which is away from the supporting carrier, until all metal layers and all insulator layers of the first redistribution layer are formed on one side of the first bonding layer, which is away from the supporting carrier, and all metal layers and insulator layers of the second redistribution layer are formed on one side of the second bonding layer, which is away from the supporting carrier.
In some embodiments, As shown in
It should be noted that, all processes known to those skilled in the technologies are used to prepare the patterned metal layer, such as photolithography+sputtering+electroplating processes, which are not described herein.
In some embodiments, “attaching an active face of the semiconductor devices to the first and/or second redistribution layers” includes:
In the present embodiment, as shown in
In some embodiments, “attaching an active face of the semiconductor devices to the first and/or second redistribution layer” includes the steps of:
In this embodiment, as shown in
In some embodiments, “forming a molding layer” includes the steps of:
Forming a molding layer by adopting a compression molding or transfer molding process.
Wherein, the material of the molding layer can be one or a combination of more of packaging molding material (Molding Compound, MC), epoxy resin, polyethylene, polypropylene, polyolefin, polyamide, polyurethane and ceramic. The molding layer is prepared by adopting compression molding and transfer molding processes, the molding material is pressurized and heated, the molding material is plasticized and flows to fill the die cavity, the molding material is cured after undergoing a crosslinking reaction, and the temperature, the pressure and the time are strictly controlled in the process.
In other embodiments, the molding layer may also be prepared using all processes known to those skilled in the technologies, such as injection molding, transfer molding and compression molding, which are not limited here.
In some embodiments, the method of making further comprises:
Forming a groove on the surface of one side of the molding layer, which is away from the supporting carrier; the grooves are used for releasing stresses.
Referring to
In this embodiment, the groove 41 may be formed using one of in-mold ribs, mechanical saw, or etching processes. When the groove 41 is formed by adopting the mold inner rib process, the inner rib is required to be arranged at the corresponding position in the mold for preparing the molding layer 4, so that the molding layer 4 and the groove 41 are simultaneously formed by one process, thereby being beneficial to save the process and improve the packaging efficiency. When the groove is formed by a mechanical saw or etching process, it is necessary to form the groove 41 at a corresponding position of the molding layer by using a saw device or an etching device after forming the molding layer 4, and thus, the surface of the formed groove 41 is smooth and has high accuracy.
It should be noted that
In some embodiments, forming a groove in a surface of a side of the molding layer facing away from the supporting carrier includes:
Forming a groove on the surface of one side of the molding layer between two adjacent semiconductor devices, which faces away from the supporting carrier.
In some embodiments, the projection of the groove 41 is located between the projections of the adjacent two semiconductor devices 3 in the thickness direction of the molding layer 4. Illustratively, as shown in
It should be noted that
In some embodiments, forming a groove in a surface of a side of the molding layer between two adjacent semiconductor devices facing away from the support carrier includes:
Along the thickness direction of the molding layer, the depth of the groove is less than or equal to ½ thickness of the molding layer.
In this embodiment, as shown in
It should be noted that, the embodiment of the present disclosure only exemplarily shows that the depth of the groove 41 is less than or equal to the preset depth, and the preset depth is ½ of the thickness of the molding layer 4 (i.e., ½H), but the embodiment of the present disclosure does not limit the fan-out package. In other embodiments, the preset depth may be greater than ½H, or less than ½H, or a specific value, which is not limited herein.
In some embodiments, after “forming the molding layer,” the method of making further comprises:
Removing the supporting carrier and the bonding layer by adopting one of thermal debonding, laser debonding and mechanical debonding.
The mode of removing the supporting carrier can be selected according to the type of the supporting carrier. For example, if the supporting carrier is a glass carrier or other light-transmitting carrier, the composite carrier may be removed by any one of thermal debonding, laser debonding and mechanical debonding; if the supporting carrier is a stainless steel carrier or other opaque carrier, a thermal debonding or mechanical debonding is used to remove the composite carrier. After the supporting carrier 1 and the bonding layer 2 are removed in this step, the surface of the side where the redistribution layer 5 is originally attached to the bonding layer 2 is exposed.
In some embodiments, the method of making further comprises:
In some embodiments, as shown in
It should be noted that
It should be noted that
In some embodiments, the method of making further comprises:
It is noted that relational terms such as “bottom” and “top” and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, material, or equipment that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, material, or equipment. Without further limitation, an element defined by the phrase “comprising one” does not exclude the presence of other like elements in a process, method, material, or equipment that comprises the element.
The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the technologies to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the technologies, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope includeent with the principles and novel features disclosed herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311110768.X | Aug 2023 | CN | national |
| 202311115225.7 | Aug 2023 | CN | national |
| 202311115241.6 | Aug 2023 | CN | national |
