Patent Grant
8647953
1. Field of the Invention
The present invention relates to a metal oxide semiconductor (MOS) device and a method for fabricating the same.
2. Description of Related Art
Metal oxide semiconductor (MOS) transistor is one of the most common elements used in many different semiconductor devices, such as memories, image sensors or displays. A typical MOS includes a silicon oxide dielectric layer, a gate conductive layer, and heavily doped source/drain contact regions. Along with decrease in linewidth of semiconductor devices, dimensions thereof are reduced. Due to the reduction in the gate width of the typical MOS, the channel length of the MOS is consequentially reduced.
As the channel length reduces, applying mechanical stress to the channel is proposed to effectively change mobility of electrons and holes in the channel, thereby increasing operating speed of the transistor. A conventional technique has been provided with using silicon germanium (SiGe) epitaxy material as a major component of the source/drain contact regions in the transistor. As compared with characteristics of silicon material, germanium has larger atomic volume and can apply a compressive stress toward the channel. Thus, the mobility of the holes can be enhanced in the source/drain contact regions majorly made of silicon germanium (SiGe), and thereby device performance can be improved.
In the fabrication process of the device, an epitaxial growth rate of silicon germanium (SiGe), however, varies in accordance with different density of surrounding patterns of the device to be formed. Accordingly, the thickness of the resultant silicon germanium (SiGe) is non-uniform (i.e. so-called loading effects), and issues regarding mismatches of the device performance arise therefrom.
The present invention is directed to a MOS device, capable of enhancing turn-on currents and lessening turn-off currents, so that the mismatches of the device performance can be ameliorated.
The present invention is directed to a method for fabricating a MOS device, wherein alterations in the fabrication process can achieve enhancement of the turn-on currents, decrease in the turn-off currents, and improvement in the mismatches of the device performance.
A method for fabricating a MOS device of the present invention is described as follows. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers.
Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.
According to an embodiment of the present invention, an included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
According to an embodiment of the present invention, the second semiconductor compound layers have a (311) facet.
According to an embodiment of the present invention, the first semiconductor compound layers and the second semiconductor compound layers contain dopants therein, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
According to an embodiment of the present invention, the epitaxial temperature of the second epitaxy growth process ranges between 650° C. and 680° C.
According to an embodiment of the present invention, an epitaxial temperature of the first epitaxy growth process ranges between 630° C. and 660° C.
According to an embodiment of the present invention, the method further includes performing a third epitaxy growth process before performing the first epitaxy growth process, so as to form a buffer layer in each of the recesses. Each of the buffer layers includes a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
According to an embodiment of the present invention, the first epitaxy growth process finishes when a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 Å to 100 Å.
Another method for fabricating a MOS device of the present invention is described as follows. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed, so as to form a second semiconductor compound layer on each of the first semiconductor compound layers. The second semiconductor compound layers protrude from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers. The second epitaxy growth process includes a first growth stage and a second growth stage, wherein a growth rate of the second growth stage is less than a growth rate of the first growth stage.
According to an embodiment of the present invention, the growth rate of the second epitaxy growth process is less than 80 Å/100 sec.
According to an embodiment of the present invention, the growth rate of the first growth stage is at least 2 times of the growth rate of the second growth stage in the second epitaxy growth process.
According to an embodiment of the present invention, an included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
According to an embodiment of the present invention, the second semiconductor compound layers have a (311) facet.
According to an embodiment of the present invention, the first semiconductor compound layers and the second semiconductor compound layers contain dopants therein, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
According to an embodiment of the present invention, the method further includes performing a third epitaxy growth process before performing the first epitaxy growth process, so as to form a buffer layer in each of the recesses. Each of the buffer layers includes a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
According to an embodiment of the present invention, the first epitaxy growth process finishes when a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 Å to 100 Å.
A MOS device of the present invention is provided, including a substrate, first semiconductor compound layers, and cap layers. The substrate has two recesses therein. The first semiconductor compound layers are disposed in the recesses. Each of the cap layers includes a second semiconductor compound layer that is disposed on each of the first semiconductor compound layers and protrudes from a surface of the substrate. An included angle between each of the second semiconductor compound layers and the surface of the substrate is less than 40°.
According to an embodiment of the present invention, the second semiconductor compound layers have a (311) facet.
According to an embodiment of the present invention, the first semiconductor compound layers and the second semiconductor compound layers contain dopants therein, and a dopant concentration in the second semiconductor compound layers is equal to or lower than a dopant concentration in the first semiconductor compound layers.
According to an embodiment of the present invention, the MOS device further includes buffer layers, respectively disposed in the recesses and intervening between the substrate and the first semiconductor compound layers. Each of the buffer layers includes a semiconductor compound layer having a dopant concentration equal to 0 or lower than a dopant concentration in the first semiconductor compound layers.
According to an embodiment of the present invention, a top of the first semiconductor compound layers protrudes from the surface of the substrate by 50 Å to 100 Å.
According to an embodiment of the present invention, a thickness of the cap layers is 1/X to 1/Y times of a thickness of the first semiconductor compound layers.
As mentioned above, the MOS device in this invention can enhance the turn-on currents and lessen the turn-off currents, thereby improving the mismatches of the device performance. Moreover, the fabricating method of the MOS device in this invention is capable of enhancing the turn-on currents, lessening the turn-off currents, and improving the mismatches of the device performance through modifications in the fabrication process.
In order to make the aforementioned and other features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawings will be provided by the Office upon request and payment of the necessary fee. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Referring to
Stack structures are then formed on the first and the second active areas 14a, 14b of the substrate 10, respectively. Each stack structure 16 includes an insulating layer 18, a conductor layer 20 and a hard mask layer 22. In an embodiment, a width of the stack structures 16 is, for example, about 24 nm. The insulating layers 18 may include a dielectric layer, a high-dielectric constant (K value greater than 4) material, a barrier layer, or combination thereof. The dielectric layer is, for example, made of silicon oxide. The high-K dielectric material is, for example, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), or hafnium zirconium oxide (HfZrO). The barrier layer is, for example, made of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or combination thereof. The material of the conductor layers 20 can be monocrystalline silicon, undoped polysilicon, doped polysilicon, amorphous silicon, silicon germanium material, or combination thereof with a thickness of, for example, about 650 Å. The material of the hard mask layers 22 can be silicon oxide, silicon nitride, silicon carbide or silicon oxynitride with, for example, hundreds of angstroms in thickness. The formation of the stack structures 16 can be carried out by forming an insulating material layer, a conductor material layer and a hard mask material layer, and then patterning the foregoing layers through lithography and etching processes.
Afterwards, first spacers 24 are formed on respective sidewalls of each stack structure 16. The material of the first spacers 24 are, for example, silicon nitride. Then, ion implantation processes are conducted individually, so that a lightly doped drain (LDD) 25a and an LDD 25b are formed respectively in the first active area 14a and in the second active area 14b. In an embodiment, when a PMOS device is to be formed on the first active area 14a, dopants implanted into the LDD 25a may be P-type; when an NMOS is to be formed on the second active area 14b, dopants implanted into the LDD 25b may be N-type. In another embodiment, when the NMOS device is to be formed on the first active area 14a, dopants implanted into the LDD 25a may be N-type; when the PMOS device is to be formed on the second active area 14b, dopants implanted into the LDD 25b may be P-type. The P-type dopants can be boron or BF2+, while the N-type dopants can be phosphorous or arsenic.
Subsequently, a block layer 26 is formed on the substrate 10. The block layer 26 is, for example, made of silicon nitride. A mask layer 28 is then formed on the first active area 14a. The mask layer 28 is, for example, made of photoresist, and the formation thereof can be implemented by the lithography process.
Referring to
Afterwards, a portion of the substrate 10 in the first active area 14a is removed by dry or wet etching or combination thereof, so that two recesses 32 are formed in the substrate 10 at both sides of the second spacers 30a. In an embodiment, a depth of each recess 32 is, for example, about hundreds of angstroms. The recesses 32 can have diamond-shaped profiles or rectangle-shaped profiles, and are not particularly limited by the present invention.
Referring to
A semiconductor compound layer 33 is then formed in each of the recesses 32. The fabricating method of the semiconductor compound layers 33 includes performing a first epitaxy growth process to form a first semiconductor compound layer 34 in each recess 32, and then performing a second epitaxy growth process to form a cap layer 36 on each first semiconductor compound layer 34. Each cap layer 36 includes a second semiconductor compound layer that may protrude from the surface of the substrate 10. Before conducting the first epitaxy growth process, thermal annealing can be optionally performed in a hydrogen ambiance.
The first and the second semiconductor compounds described herein are, for example, IV-IV semiconductor compounds. The IV-IV semiconductor compounds can be composed of a first Group N element and a second Group IV element. The first Group IV element is, for example, silicon (Si). The second Group N element is, for example, a nonsilicon element, such as germanium (Ge) or carbon (C). In other words, the IV-IV semiconductor compounds can be silicon germanium (SiGe) or silicon carbide (SiC). In the PMOS device, the material of the first semiconductor compound layers 34 and the second semiconductor compound layers may be silicon germanium (SiGe); in the NMOS device, the material of the first semiconductor compound layers 34 and the second semiconductor compound layers may be silicon carbide (SiC).
The content of the second Group IV element (e.g. germanium content or carbon content) in the second semiconductor compound layers is less than that of the second Group N element (e.g. germanium content or carbon content) in the first semiconductor compound layers 34. The first semiconductor compound layers 34 and the second semiconductor compound layers of the cap layers 36 have dopants contained therein, and the dopant concentration in the second semiconductor compound layers of the cap layers 36 is equal to or lower than that in the first semiconductor compound layer 34. In the PMOS device, the first semiconductor compound layers 34 and the second semiconductor compound layers are doped with the P-type dopants, e.g. boron or BF2+; in the NMOS device, the first semiconductor compound layers 34 and the second semiconductor compound layers are doped with the N-type dopants, e.g. phosphorous or arsenic.
In an embodiment, when the semiconductor compound is silicon germanium (SiGe), reactant gas utilized in the epitaxy growth processes includes a silicon source and a germanium source. The epitaxial temperatures of the first epitaxy growth process and the second epitaxy growth process are lower than 700° C. Owing to the relatively low epitaxial temperatures of the first and the second epitaxy growth processes, outward diffusion of the dopants in the first semiconductor compound layers 34 and in the second semiconductor compound layers can be significantly mitigated.
In an embodiment, the epitaxial temperature of the second epitaxy growth process may range between 650° C. and 680° C., and the epitaxial temperature of the first epitaxy growth process may range between 630° C. and 660° C. In other words, the epitaxial temperature of the second epitaxy growth process is slightly higher than that of the first epitaxy growth process by about 10° C. to tens of degrees Celsius, but the epitaxial temperature of the second epitaxy growth process is still lower than 700° C.
Referring to
When the first epitaxy growth process finishes, the top of the resultant first semiconductor compound layers 34 may protrude from the surface of the substrate 10 by 50 Å to 100 Å. When the second epitaxy growth process finishes, the second semiconductor compound layers of the resultant cap layers 36 reach tens of angstroms to hundreds of angstroms in thickness.
In an embodiment, as the semiconductor compound is silicon germanium (SiGe), an included angle between the second semiconductor compound layer of the cap layers 36 and the surface of the substrate 10 is less than 40°, for example about 25°. In an embodiment, as the semiconductor compound is silicon germanium (SiGe), the second semiconductor compound layers in the lateral of the cap layers 36 may have a (311) facet, and the second semiconductor compound layers in the upper surface of the cap layers may have a (100) facet.
In another embodiment, the formation of the semiconductor compound layers 33 further includes performing a third epitaxy growth process before the first epitaxy growth process is performed, so as to form a buffer layer 38 in each recess 32. Each buffer layer 38 includes a third semiconductor compound layer, and a dopant concentration therein equal to 0 or lower than that in the first semiconductor compound layers 34. In the PMOS device, the buffer layers 38 are doped with the P-type dopants, such as boron or BF2+. In the NMOS device, the buffer layers 38 are doped with the N-type dopants, such as phosphorous or arsenic.
In the PMOS device at 40 nm process node, the semiconductor compound layers of the first semiconductor compound layers 34, the second semiconductor compound layers 36 and the buffer layers 38 are silicon germanium (SiGe). The germanium content in the semiconductor compound layers of the buffer layers 38 is, for example, about 22-25%; the germanium content in the first semiconductor compound layers 34 is, for example, about 28%; and the germanium content in the second semiconductor compound layers of the cap layers 36 is, for example, about 8%. A boron-doped content in the semiconductor compound layers of the buffer layers 38 is, for example, about 0%; a boron-doped content in the first semiconductor compound layers 34 is, for example, about 2×1020/cm2; and a boron-doped content in the second semiconductor compound layers of the cap layers 36 is, for example, about 7×1019/cm2 to 2×1020/cm2. It is verified, in this invention, by experiments that the turn-on currents (Ion) can be enhanced by 2%, and the turn-off currents (Ioff) can be diminished, thereby the mismatches of the device performance can be ameliorated by 6% or above.
The foregoing first semiconductor compound layers 34, the foregoing cap layers (the second semiconductor compound layers) 36 and the foregoing buffer layers 38 can be formed by conducting the epitaxy growth processes in the same reaction chamber, wherein the silicon germanium (SiGe) (or silicon carbide (SiC)) with various germanium content (or carbon content) is formed by adjusting the ratio of the silicon source and the germanium source in the reactant gas (or the ratio of the silicon source and the carbon source in the reactant gas). In addition, in-situ doping is conducted during the epitaxy growth processes.
Referring to
Referring to
Referring to
A metal layer 52 is then formed on the substrate 10. The material of the metal layer 52 includes refractory metal, e.g. nickel (Ni), titanium (Ti), tungsten (W), cobalt (Co), platinum (Pt) or palladium (Pd).
Referring to
In view of the above, the present invention is carried out by growing the semiconductor compounds of the source and drain regions through the first and the second epitaxy growth processes with the relatively low epitaxial temperatures, and the outward diffusion of the dopants in the resultant first and second semiconductor compound layers can be alleviated. In addition, the second semiconductor compound layers formed by this fabrication process have an included angle with the surface of the substrate less than 40°, which can enhance the turn-on currents and lessen the turn-off currents of the MOS device, so that the improvement in the mismatches of the device performance can be achieved.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
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