Method for fabricating semiconductor device

Abstract

A method for fabricating a semiconductor device includes forming a plurality of bit line patterns, each bit line pattern having a double-layer hard mask including a nitride-based layer and an amorphous carbon-based layer, forming a planarized insulation layer filled between the bit line patterns, the planarized insulation layer flush with the nitride-based layer, forming line type storage node contact masks over predetermined portions of the planarized insulation layer, etching the planarized insulation layer to form storage node contact holes each having a top portion which is wider than a bottom portion, forming storage node contact spacers in a double layer structure on sidewalls of the storage node contact holes, and forming storage node contacts filling the storage node contact holes.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention will become better understood with respect to the following description of the exemplary embodiments given in conjunction with the accompanying drawings, in which:

FIG. 1A illustrates a micrographic view of typical bit lines lacking sufficient top surface areas;

FIG. 1B illustrates a micrographic view of typical nitride-based bit line hard mask layers damaged during a self-aligned contact (SAC) etching process due to a lack of sufficient top surface areas;

FIG. 1C illustrates a micrographic view of a SAC fail caused by a lack of bit line spacer thickness during a typical storage node contact formation process;

FIGS. 2A to 2E illustrate cross-sectional views to describe a method for fabricating a semiconductor device in accordance with an exemplary embodiment of the present invention;

FIG. 3 illustrates a micrographic view of bit line patterns including nitride-based bit line hard mask layers with a minimized loss due to a usage of amorphous carbon-based bit line hard mask layers;

FIG. 4 illustrates a micrographic view of bit line patterns with a reduced SAC fail due to an improved bit line spacer thickness in accordance with an exemplary embodiment of this invention; and

FIG. 5 illustrates a micrographic view of a bit line pattern including a nitride-based bit line hard mask layer wherein a loss of the bit line hard mask layer is prevented by applying a buffer oxide layer.

Claims

1. A method for fabricating a semiconductor device, comprising: forming a plurality of bit line patterns, each bit line pattern having a double-layer hard mask including a nitride-based layer;forming a planarized insulation layer filled between the bit line patterns;forming line type storage node contact masks over predetermined portions of the planarized insulation layer;etching the planarized insulation layer to form storage node contact holes each having a top portion which is wider than a bottom portion;forming storage node contact spacers in a double layer structure on sidewalls of the storage node contact holes; andforming storage node contacts filling the storage node contact holes.

2. The method of claim 1, wherein forming the storage node contact spacers comprises: forming another nitride-based layer and a buffer oxide layer in sequential order; andetching the buffer oxide layer and the other nitride-based layer to form the storage node contact spacers in the double layer structure including nitride-based spacers and buffer oxide spacers.

3. The method of claim 2, wherein the other nitride-based layer and the buffer oxide layer each has a thickness ranging from approximately 100 Å to approximately 300 Å.

4. The method of claim 1, wherein etching the planarized insulation layer using the storage node contact masks to form the storage node contact holes comprises: etching portions of the planarized insulation layer to form first trenches enlarged in a horizontal direction; andetching other portions of the planarized insulation layer below the first trenches to form second trenches.

5. The method of claim 4, wherein etching the portions of the planarized insulation layer to form the first trenches enlarged in a horizontal direction comprises: performing a dry etching process onto the portions of the planarized insulation layer using the storage node contact masks as an etch mask to form the first trenches; andperforming a wet etching process to enlarge the first trenches in a horizontal direction.

6. The method of claim 5, wherein performing the dry etching process comprises applying a pressure ranging from approximately 15 mT to approximately 50 mT and a power ranging from approximately 1,000 W to approximately 2,000 W, and flowing a gas mixture including CF4, C4F8, C5F8, C4F6, CHF3, CH2F2, Ar, O2, CO, and N2.

7. The method of claim 6, wherein performing the dry etching process comprises etching the portions of the planarized insulation layer to a thickness ranging from approximately 1,000 Å to approximately 2,000 Å.

8. The method of claim 5, wherein performing the wet etching process comprises using one of hydrogen fluoride (HF) solution and buffered oxide etchant (BOE) solution.

9. The method of claim 4, wherein etching the other portions of the planarized insulation layer below the first trenches to form the second trenches comprises performing a dry etching process.

10. The method of claim 9, wherein performing the dry etching process comprises applying a pressure ranging from approximately 15 mT to approximately 50 mT and a power ranging from approximately 1,000 W to approximately 2,000 W, and flowing a gas mixture including C4F8, C5F8, C4F6, CH2F2, Ar, O2, CO, and N2.

11. The method of claim 1, wherein forming the planarized insulation layer comprises: forming an insulation layer over the bit line patterns in a manner to fill the space between the bit line patterns; andperforming a chemical mechanical polishing (CMP) process on the insulation layer, wherein the insulation layer comprises an oxide-based material.

12. The method of claim 11, wherein the double-layer hard mask of each bit line pattern includes an amorphous carbon-based layer and the amorphous carbon-based layers are formed to have a predetermined polishing rate substantially the same as the insulation layer.

13. The method of claim 12, wherein the insulation layer has a thickness ranging from approximately 4,000 Å to approximately 10,000 Å, and the amorphous carbon-based layers have a thickness ranging from approximately 1,000 Å to approximately 2,000 Å.

14. The method of claim 1, wherein the storage node contact masks comprise a KrF-based photoresist material.

15. The method of claim 14, wherein forming the bit line patterns comprises: forming a barrier metal;forming a bit line tungsten layer over the barrier metal;forming a double-layer hard mask layer including a preformed nitride-based layer and a preformed amorphous carbon-based layer over the bit line tungsten layer;forming an anti-reflective coating layer over the hard mask layer; andetching the anti-reflective coating layer, the preformed amorphous carbon-based layer, the preformed nitride-based layer, the bit line tungsten layer, and the barrier metal in sequential order.

16. The method of claim 15, wherein the barrier metal comprises a double layer structure including titanium (Ti) and titanium nitride (TiN) formed in sequential order and has a thickness ranging from approximately 100 Å to approximately 1,000 Å.

17. The method of claim 15, wherein the bit line tungsten layer has a thickness ranging from approximately 300 Å to approximately 1,000 Å.

18. The method of claim 15, wherein the preformed nitride-based layer has a thickness ranging from approximately 1,000 Å to approximately 2,500 Å, and the preformed amorphous carbon-based layer has a thickness ranging from approximately 1,000 Å to approximately 2,000 Å.

19. The method of claim 15, wherein etching the preformed amorphous carbon-based layer and the preformed nitride-based layer comprises using a gas mixture including CF4, CHF3, O2, and Ar at a pressure ranging from approximately 20 mT to approximately 70 mT and applying a power ranging from approximately 300 W to approximately 1,000 W.

20. The method of claim 15, wherein etching the bit line tungsten layer and the barrier metal comprises using a gas mixture including SF6, BCl3, N2, and Cl2 at a pressure ranging from approximately 20 mT to approximately 70 mT and applying a power ranging from approximately 300 W to approximately 1,000 W.

21. The method of claim 1, wherein the planarized insulation layer is flush with the nitride-based layer.