Patent Application
20230187528
The present application is a non-provisional patent application claiming priority to European Patent Application No. EP 21214869.6, filed Dec. 15, 2021, the contents of which are hereby incorporated by reference.
The present disclosure relates to a method for forming a precursor semiconductor device structure, and a method for forming a semiconductor device.
The constant strive to achieve ever more area- and power-efficient circuits has resulted in development of horizontal channel transistor devices with a 3D geometry, based on stacks of nanowires or nanosheets, such as nanowire field-effect transistors (NWFET) and nanosheet FETs (NSHFET) including one or more nanowire- or nanosheet-shaped channel layers and a “wrap-around” gate surrounding the channel layers completely or at least partly. Further examples are the forksheet device and the Complementary FET (CFET).
Current fabrication processes for such devices may involve processing of a semiconductor layer stack of alternatingly channel layers of Si and sacrificial layers of SiGe. Etching processes have been developed which allow for SiGe to be etched with a relatively high selectively to Si, such that the sacrificial layers may be removed selectively to the channel layers. For example, wrap-around gates may be formed by removing sacrificial layer material above and below the channel layers to form “released” channel layers (e.g. in connection with a replacement metal gate process), to subsequently be surrounded by the gate stack.
Combining layers of Si and SiGe in a layer stack is not without issues. The presence of SiGe may require a lowering of the thermal budget for the fabrication process, e.g. to avoid intermixing of the Si- and SiGe-layers and/or defect formation in the SiGe-layers. Among others, a lower thermal budget may result in a less robust shallow trench isolation (STI) oxide, which in turn may result in a greater loss of STI oxide in subsequent processing stages.
In light of the above, the disclosure provides a method for semiconductor device fabrication. In particular, the disclosure provides a method enabling forming of a semiconductor device structure, which may be used as a precursor structure in methods for forming semiconductor devices, comprising e.g. NW- or NSHFETs, without requiring a lowering of the thermal budget. Further and alternative objectives may be understood from the following.
An embodiment discloses a method for forming a precursor semiconductor device structure, the method comprising:
By the method, sacrificial layers of the first semiconductor material may be replaced by insulating layers of the insulating material. Thereby, a precursor semiconductor device structure may be formed comprising fin structures, each comprising a respective insulating layer and a channel layer over the insulating layer. The insulating layers of the fin structures may facilitate a selective processing of the insulating layers and semiconductor channel layers, for instance selective removal and etching of the insulating material for the purpose of channel release. However, the insulating layers may additionally function as a bottom isolation underneath the channels, enabling reduced leakage currents and improved device performance.
For instance, the sacrificial layers may be formed of SiGe (e.g. SiGey≥0.15) and the channel layers may be formed of Si, wherein the sacrificial layers may be removed selectively to the channel layers and replaced by insulating layers. The resulting fin structures may thereby be more thermally stable and thus facilitate fabrication of semiconductor devices, e.g. NW- or NSHFETs, without requiring a reduced thermal budget. This may enable a more robust STI oxide and in turn contribute to improved process margins in various steps in a CMOS semiconductor fabrication flow in terms of STI loss.
Although applying the method to layer stacks comprising SiGe sacrificial layers and Si channel layers is one notable application of the method, it is contemplated that the method may have further applicability, and may be used in any context where it may be advantageous to provide an insulating layer underneath a channel layer. As one example, the first semiconductor material may be SiGey and the second semiconductor material may be SiGex, where 0 ≤ x < y, e.g. y ≥ x + 0.15. The method may be used to replace a SiGe-sacrificial layer with a higher Ge-content than a Si- or SiGe-channel layer, by an insulating layer. The resulting fin structures may be less sensitive to thermally driven inter-mixing of the SiGex and SiGey layers.
The at least one anchoring structure allows the channel layers to be anchored and thus supported above the cavities formed in the respective fin structures by removing the sacrificial layers. As the sacrificial layers are removed from the fin structures (i.e. completely), each cavity may be formed to be coextensive with the respective fin structure and the channel layer thereof (as seen along a longitudinal dimension of the fin structure). This applies correspondingly to the insulting layers.
Depositing the insulating material in the form of a flowable dielectric enables reliable and void-free filling also of cavities of relatively great longitudinal dimensions and narrow cross-sectional dimensions. The insulating material may for example be a flowable oxide, e.g. a flowable-Chemical Vapor Deposition (FCVD) oxide such as FCVD SiO2.
As used herein, the wording “precursor semiconductor device structure” refers to a semiconductor device structure which may be used as a precursor or an intermediate product in a method for forming a semiconductor device, wherein the precursor semiconductor device structure may be subjected to device processing steps to form a semiconductor device.
Accordingly, in one embodiment, the disclosure provides a method for forming a semiconductor device, the method comprising: forming a precursor semiconductor device structure in accordance with the above or any of the embodiments or variations thereof described herein; and subsequently, along one or more of the fin structures of the precursor semiconductor device structure, forming a gate structure and source and drain regions.
One or more transistor devices, such as FET devices, may accordingly be formed along one or more of the fin structures. It is contemplated that the preliminary semiconductor device structure advantageously may be used to facilitate forming of NW- or NSHFETs, as well as stacked transistor device structures such as the complementary FET (CFET) device.
Embodiments of methods for forming the precursor semiconductor structure will be described hereinafter:
In some embodiments, the channel layer may be a second channel layer and the initial layer stack and each fin structure may further comprise a first channel layer of the second semiconductor material, wherein the sacrificial layer is formed on the first channel layer and the second channel layer is formed on the sacrificial layer.
The initial layer stack and each fin structure may accordingly comprise (e.g. in a bottom-up direction) a first channel layer of the second semiconductor material, a sacrificial layer of the first sacrificial layer and a second channel layer of the second semiconductor material. By replacing the sacrificial layer of each fin structure with an insulating layer in accordance with the method, fin structures comprising the first and the second channel layers separated by an insulating layer may be formed. The insulating layer may be used as a sacrificial layer in a method for forming a semiconductor device to facilitate forming of a gate stack between the channel layers. The insulating layer may also be used as an insulating layer to electrically separate the bottom device from the top device in a CFET device.
The sacrificial layer may further be a second sacrificial layer and the initial layer stack and each fin structure may further comprise a first sacrificial layer of the first semiconductor material, wherein the first channel layer is formed on the first sacrificial layer. The initial layer stack and each fin structure may accordingly comprise (e.g. in a bottom-up direction) a first sacrificial layer of the first semiconductor material, a first channel layer of the second semiconductor material, a second sacrificial layer of the first sacrificial layer and a second channel layer of the second semiconductor material. By replacing the first and second sacrificial layers of each fin structure with an insulating layer in accordance with the method, fin structures comprising a first insulating layer, the first channel layer, a second insulating layer, and the second channel layer may be formed. The insulating layers may be used as sacrificial layers in a method for forming a semiconductor device to facilitate forming of a gate stack completely surrounding the first channel layer.
In some embodiments, the layer stacks and fin structures may each comprise a plurality of sacrificial layers of the first semiconductor material and a plurality of channel layers of the second semiconductor material, wherein the channel layers are arranged alternatingly with the sacrificial layers (e.g. in a bottom-up direction). This allows forming of semiconductor devices comprising plural channel layers.
In some embodiments, forming the at least one anchoring structure may comprise depositing an anchoring material layer structure of one or more layers on the set of fin structures and in the trenches, and patterning the anchoring material layer structure to form the at least one anchoring structure.
An anchoring material layer structure may be formed in contact (i.e. in abutment with) with each fin structure and subsequently be patterned to form at least one anchoring structure at desired locations along the fin structures.
In some embodiments, patterning the anchoring material layer structure may comprise forming at least one mask line extending across the set of fin structures and etching the anchoring material layer structure using the at least one mask line as an etch mask such that fin structure side surface portions not masked by the at least one mask line are exposed,
The at least one anchoring structure may be formed to allow access to side surface portions of each fin structure. The etching of the sacrificial layers and the deposition of the insulating material may be performed from the sides of the fin structure, which may facilitate removal of the sacrificial layers as well as the filling of the cavities.
The number of mask lines may be varied to form a number of anchoring structures sufficient for securely anchoring the channel layers. For example, first and second parallel mask lines may be formed across the set of fin structures, at opposite ends thereof. A first and second anchoring structure extending across the set of fin structures may thus be formed at the opposite ends of the set of fin structures. The channel layers may be supported by the anchoring structure, at least at opposite ends of the fin structures. In another example, a plurality of parallel and regularly spaced apart mask lines may be formed across the set of fin structures. A plurality of parallel and regularly spaced apart anchoring structures extending across the set of fin structures may thus be formed with a regular spacing along the set of fin structures. Plural anchoring structures may enable a mechanically reliable anchoring of the channel layers.
The anchoring material layer structure may comprise an insulating fill layer deposited to fill the trenches.
The insulating fill layer may accordingly embed the fin structures. This enables forming one or more anchoring structures along a full height of the fin structures may be formed, i.e. “tall” anchoring structures. A tall anchoring structure may provide a secure anchoring function. Each anchoring structure may for example comprise a plurality of (tall) anchoring parts, each anchoring part bridging a trench between a neighboring pair of fin structures. As the fill layer is insulating, if thickness portions of the insulating fill layer remain after recessing the at least one anchoring structure (intentionally or as trace amounts), such portions may have little or no impact on the performance of the final device.
The recessing of the at least one anchoring structure and the insulating material may comprise simultaneously recessing the insulating fill layer and the insulating material to the level below the cavities. The level to which the recess proceeds may be such that a thickness portion of the insulating fill layer and the insulating material remains to form STI in a bottom part of the trenches.
A simultaneous recess may reduce a complexity of the process. Furthermore, preserving a thickness portion of the insulating fill layer and the insulating material as STI in the trenches, between the fin structures, obviates the need for a separate STI deposition step. The fill layer and the insulating layer may each provide a double-function of forming the at least one anchoring structure and forming the STI, and forming the insulating layers replacing the sacrificial layers and forming the STI, respectively.
In some embodiments representing alternatives to the embodiments comprising patterning using one or more mask lines, the method may further comprise forming a fin cut mask over the anchoring material layer structure, wherein patterning the anchoring material layer structure may comprise etching the anchoring material layer structure using the fin cut mask as an etch mask, wherein the patterned anchoring material layer structure may form part of the anchoring structure.
The method may further comprise, subsequent to patterning the anchoring material layer structure, removing parts of each fin structure by etching the fin structures using the fin cut mask as an etch mask, thereby forming a set of cut fin structures covered by the anchoring structure and having exposed end surfaces.
Removing the sacrificial layers may accordingly comprise etching the first semiconductor material from the end surfaces of each fin structure.
Additionally, the deposition of the insulating material may be performed from openings of the cavities formed at the end surfaces portions of each fin structure.
The sacrificial layer replacement may be combined with a fin cut process.
A single anchoring structure coextensive with the (cut) fin structures may be formed across the set of fin structures. The anchoring structure may support the channel layers along the full longitudinal dimension of the fin structures, thus enabling a mechanically reliable anchoring of the channel layers.
The fin cut mask may be removed subsequent to forming the set of cut fin structures, at least prior to depositing the insulating material, such as prior to removing the sacrificial layers to form the cavities.
The anchoring material layer structure may comprise an insulating fill layer deposited to fill the trenches.
The insulating fill layer may accordingly embed the fin structures. This enables forming of the anchoring structure along the full height and full length of the fin structures, i.e. “tall” and “long” anchoring structures.
A tall and long anchoring structure may provide a secure anchoring function. The anchoring structure may for example comprise a plurality of (e.g. tall and long) anchoring parts, each anchoring part bridging and being coextensive with (i.e. filling) a trench between a neighboring pair of fin structures. As the fill layer is insulating, if thickness portions of the insulating fill layer remain after recessing the anchoring structure (intentionally or as trace amounts), such portions may have little or no impact on the performance of the final device.
The recessing of the anchoring structure and the insulating material may comprises simultaneously recessing the insulating fill layer and the insulating material to the level below the cavities, wherein the level is such that a thickness portion of the insulating fill layer remains to form STI in a bottom part of the trenches.
A simultaneous recess may reduce a complexity of the process. Furthermore, preserving a thickness portion of the insulating fill layer as STI in the trenches, between the fin structures, obviates the need for a separate STI deposition step. The fill layer may provide a double-function of forming the at least one anchoring structure and forming the STI.
In embodiments comprising patterning using one or more mask lines , and embodiments comprising patterning using a fin cut mask alike, the insulating fill layer may be formed of a same material as the insulating material, i.e. the flowable dielectric, e.g. a flowable oxide such as FCVD SiO2.
The insulating fill layer may be formed in direct contact, i.e. in abutment with, the side surfaces of the fin structures and bottom surface of the trenches. This enables an anchoring structure of a single material composition, which may facilitate the patterning and avoid the need of additional etching steps during the recessing.
Alternatively or additionally, the anchoring material layer structure may comprise an insulating liner layer conformally deposited on the fin structures and in the trenches. A conformally deposited layer, e.g. deposited by atomic layer deposition (ALD) enables forming anchoring structures with precise thickness control and good adhesion to the fin structures, e.g. the side surfaces thereof. Similar to the discussion of the fill layer, as the liner layer is insulating, if portions of the insulating fill layer remain after recessing the at least one anchoring structure (intentionally or as trace amounts), such portions may have little or no impact on the performance of the final device.
The insulating liner layer may further be combined with the insulating fill layer, by depositing the insulating fill layer on the liner layer, thereby providing a combination of the respective advantages discussed above.
The recessing of the at least one anchoring structure may further comprise removing portions of the liner layer present above said level by etching. That is, the recessing may comprise first recessing the insulating material and the insulating fill layer (if present) to said level below the cavities, and thereafter recessing liner layer to said level by removing portions of the liner layer present above said level by etching.
The above, as well as additional features will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.
A method for forming a semiconductor device structure 100 will now be described with reference to
In the figures, axes X, Y and Z indicate a first direction, a second direction transverse to the first direction, and a vertical or bottom-up direction, respectively. The X- and Y-direction may in particular be referred to as lateral or horizontal directions in that they are parallel to a main plane of a substrate 102 of the structure 100. The Z-direction is parallel to a normal direction to the substrate 102.
The number of sacrificial and channel layers 111, 113 shown in the figures is merely one example and an initial layer stack comprising fewer or greater numbers of sacrificial and channel layers is also possible. In one example, an initial layer stack may comprise a single sacrificial layer and a single channel layer on the sacrificial layer. In another example, an initial layer stack may comprise a bottom sub-stack of alternating sacrificial and channel layers, a top sub-stack of alternating sacrificial and channel layers, and an intermediate sacrificial layer separating the lower and upper sub-stacks. Such a layer composition may be suitable for a CFET device, wherein a bottom device may be formed at the bottom sub-stack and a top device may be formed at the top sub-stack. As may be appreciated from the following, the intermediate sacrificial layer may be replaced with an insulating layer to provide electrical and physical separation between the bottom and top devices. The intermediate sacrificial layer may be thicker than the sacrificial layers of the bottom and top sub-stacks to enable an increased device separation.
The sacrificial layers 111 are formed of a first semiconductor material. The channel layers 113 are formed of a second semiconductor material. For example, the first and second semiconductor materials may be:
Si1-yGey and Si1-xGex respectively, wherein 0 ≤ x < y. For example, y may be equal to or greater than x + d, where d ≥ 0.15. In a more specific example, the first semiconductor material may be SiGe0.15 and the second semiconductor material may be a Si. These relative differences in Ge-content may facilitate subsequent selective processing (e.g. selective etching) of the first semiconductor material and the second semiconductor material.
The layers of the device layer stack 104 may each be epitaxial layers, e.g. epitaxially grown using deposition techniques which per se are known, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). This enables high quality material layers with an advantageous degree of control of composition and dimensions.
In another example of an initial layer stack, a further sacrificial layer of a third semiconductor material (different from the first and second semiconductor materials) may be present between a sacrificial layer of the first semiconductor material and a channel layer of the second semiconductor material. The third semiconductor material may for example be a layer of SiGe with Ge content less than the first semiconductor material and greater than the second semiconductor material. This may allow the further sacrificial layer to be replaced with a different insulating material than the insulating material replacing the sacrificial layer of the first semiconductor material.
After forming the initial layer stack 104, a hard mask 106 may be formed over the initial layer stack 104. The hard mask 106 may comprise one or more layers of hard mask material (e.g. oxide- or nitride-based hard mask material) and be patterned to form a set of parallel and regularly spaced line features, extending along the X-direction. The hard mask 106 is to be used for a subsequent step of fin patterning, as will be described below, and may be patterned using any suitable conventional patterning technique, such as lithography and etching (“litho-etch”) or multiple-patterning techniques such as (litho-etch)x, self-aligned double or quadruple patterning (SADP or SAQP).
In
In the illustrated example, the hard mask 106 is preserved on the fin structures 110 during the subsequent processing, however it is envisaged that the hard mask 106 also may be removed after forming the fin structures 110.
In
In
In
As shown in
The (patterned) liner layer 120 defines an anchoring structure extending across the cut fin structures 110 along the Y-direction and being coextensive with the longitudinal dimension of the cut fin structures 110, i.e. along the X-direction. The label “cut” may in the following be omitted for conciseness.
In
In
Depositing the insulating material 122 in the form of a flowable dielectric enables reliable and void-free filling of the trenches 108 and the cavities 116. The insulating material may for example be a flowable oxide, e.g. a FCVD oxide such as FCVD SiO2. However other types of flowable dielectrics suitable to provide insulation underneath and between the channel layers 114 are also possible. Deposition of a flowable dielectric may comprise a number of substeps such as introducing a number of gas-phase precursor to deposit a flowable dielectric film with a flowable (i.e. fluid) appearance, such that the flowable dielectric film may flow into the trenches 108 and into the cavities 116. The flowable film may subsequently be subjected to post-processing steps to solidify the film (e.g. annealing or and/or subjecting the film to an oxidizing plasma) and form a solid (i.e. non-fluid) insulating layer 122. After deposition, the insulating material 122 may if needed be planarized, e.g. by chemical mechanical polishing (CMP). Optionally, the deposition of the insulating material 122 may be preceded by a conformal deposition of a further insulating material, such that exposed surfaces of each fin structure 110 (e.g. lower and/or upper surfaces of the channel layers 114 exposed in the cavities 116) are covered by the further insulating material. The further insulating material may for example be a nitride such as SiN, e.g. deposited by ALD. The insulating material 122 may accordingly fill a remaining space of the cavities 116. The conformally deposited layer may mask the semiconductor material of the channel layers 114 from the process conditions during the deposition of the flowable dielectric insulating material 112.
In
In the example described above, an anchoring structure coextensive with the fin structures 110 is formed by patterning an anchoring material layer structure of a single liner layer 120, using a fin cut mask 130. In the following, an alternative embodiment will be disclosed with reference to
Additionally, a number of mask lines 230 have been formed over the fin structures 110, the liner layer 120 and the fill layer 222. The mask lines 230 extend in parallel and across the fin structures 100 along the Y-direction. The mask lines 230 may be formed in a manner similar to the hard mask 106, e.g. by depositing and then patterning one or more layers of a mask material (e.g. an organic spin-on-layer, a nitride layer, an oxide layer, a photoresist layer) using single- or multiple-patterning techniques to define a desired number of mask lines 230. In contrast to the fin cut mask 130, the mask lines 230 will not be used to cut the fin structures 110, but merely to pattern the anchoring material layer structure. Fin cutting may for example have been performed using a conventional process prior to the stage depicted in
In
In
In
After deposition, the insulating material (i.e. flowable dielectric) 222 may if needed be planarized, e.g. by chemical mechanical polishing (CMP).
In
In a further alternative embodiment, a liner layer 120 may be omitted wherein the fill layer 222 may be deposited in contact with the fin structure 110. , a number of anchoring structures may be formed comprising only (i.e. consisting of) a portion of the fill layer 222 preserved underneath a respective mask line 230. The anchoring structures of this alternative embodiment may similar to the embodiment discussed in connection with
In yet another alternative embodiment, a fill layer 222 may be omitted wherein a number of anchoring structures may be formed comprising only (i.e. consisting of) a portion of the liner layer 120 preserved underneath a respective mask line 230.
The resulting semiconductor device structure 100 shown in either of
The processing steps may be applied to each of the fin structures 110, or only to a subset of “active” fin structures, wherein the other fin structures may define dummy fin structures.
In step S202 a number of sacrificial gate structures may be formed across the fin structures 110. Each sacrificial gate structure may comprise a sacrificial gate body (e.g. of amorphous Si) and a pair of gate spacers on opposite sides of the sacrificial gate body. The sacrificial gate structures may be formed using conventional processing techniques as per se are known in the art.
In step S204 the fin structures 110 may be recessed (e.g. etched back top-down) using the (respective) sacrificial gate structure as an etch mask, such that portions of insulating layers 124 or 224, and channel layers 114 of each fin structure 110 are preserved underneath the sacrificial gate structure to define a respective device layer stack.
In step S206 inner spacers may be formed at opposite sides of each device layer stack. Inner spacers may be formed in a manner which per se is known in the art of NWFETs/NSHFETs. However, instead of as conventionally done forming recesses by selectively etching a sacrificial semiconductor material (e.g. of SiGe), the recesses may be formed by etching the insulating material of the insulating layers 124, 224. Accordingly, inner spacer cavity formation may proceed by: forming recesses in each device layer stack by an isotropic etching process selective to the insulating material of the insulating layers 124 or 224; a conformal spacer material deposition (e.g. SiN, SiCO deposited by ALD-dielectric); followed by etching of the spacer material such that spacer material remains only in the recesses to form the inner spacers.
In step S208 source/drain regions may be formed on end surfaces of the channel layers 114 of each device layer stack, at opposite sides of the respective sacrificial gate structures. The source/drain regions may for example be formed by selective area Si epitaxy. Techniques such as in-situ doping and/or ion implantation may be used to define n-type and p-type source/drain regions.
In step S210 one or more inter-layer dielectric (ILD) materials may be deposited to cover the device layer stacks, the source/drain regions and the sacrificial gate structures.
In step S212, the sacrificial gate structures may be replaced by functional gates stacks. The replacement may proceed in accordance with a replacement metal gate (RMG) flow. According to an RMG flow, gate trenches are formed by removing the sacrificial gate bodies (e.g. using a selective amorphous Si etch). The RMG flow may proceed by gate dielectric deposition (e.g. high-K dielectric such as HfO2, HfSiO, LaO, AlO or ZrO), gate work function metal deposition and gate (metal) fill deposition.
The process may further comprise a step of channel release, interleaved in the RMG process: That is, subsequent to forming the gate trenches, selectively removing the insulating layers 124 or 224 of each device layer stack by selective etching of the insulating material. Suspended channel layers 114 (e.g. nanosheets) may be defined in each gate trench. The functional gate stacks may thus be formed to wrap around the channel layers 114.
In some embodiments, step S212 may be followed by step S214 of recessing the functional gate stacks, and optionally, gate cut formation, as per se is known in the art.
The method may further comprise forming source/drain contacts on the source/drain regions, e.g. by etching contact trenches in the ILD and depositing one of more contact metals therein.
In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 21214869.6 | Dec 2021 | EP | regional |
