The present application claims priority of Korean Patent Application No. 10-2010-0064952, filed on Jul. 6, 2010, which is incorporated herein by reference in its entirety.
Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a method for forming a contact hole of a semiconductor device.
As semiconductor devices become more highly integrated, pattern linewidth becomes narrower and narrower. Herein, pattern linewidth refers to the width of parallel line-shaped structures separated by a space. Particularly, when the linewidth is approximately 30 nm, it may be difficult to perform a patterning process with a photoresist layer alone due to the limitation in the resolution of exposure equipment.
To address this concern, a method of decreasing the diameter of a contact hole by performing a reflow process on a photoresist layer or performing a Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) process on a photoresist layer has been suggested.
The reflow process is a method of decreasing the diameter of a contact hole by forming a contact hole pattern using a photoresist layer, performing a baking process at a temperature that is not lower than a glass transition temperature, and using the characteristic that the photoresist layer expands. The RELACS process is a method of decreasing the diameter of a contact hole by forming a contact hole pattern using a photoresist layer, coating the upper portion of the photoresist layer with a RELACS material, and performing a baking process to form a new layer through a reaction between the photoresist layer and the RELACS material.
While the reflow process and the RELACS process may each decrease the diameter of a contact hole pattern, they do not reduce the pitch of the pattern. Therefore, neither the reflow process nor the RELACS process can decrease the size of a semiconductor chip itself. Also, since extreme ultraviolet (EUV) exposure technology requires expensive facilities, the use of such technology may be less economical.
Therefore, it is desirable to develop a method for forming a contact hole of a semiconductor device that may overcome the limitation of a photoresist layer pattern and achieve the goals of device integration and formation of a contact hole.
Exemplary embodiments of the present invention are directed to a method for forming a contact hole of a semiconductor device.
In accordance with an exemplary embodiment of the present invention, a method for forming a contact hole of a semiconductor device, includes forming a hard mask over an etch target layer, forming a first line pattern over the hard mask, forming a second line pattern over the hard mask and the first line pattern in a direction crossing the first line pattern, forming a mesh-type hard mask pattern by etching the hard mask using the first and second line patterns as etch barriers, and forming a contact hole by etching the etch target layer using the mesh-type hard mask pattern as an etch barrier.
The hard mask may have a stacked structure of a first polysilicon layer and a first silicon oxynitride layer. The hard mask may further include an oxide layer, an amorphous carbon layer, or a stacked layer of an oxide layer and an amorphous carbon layer between the first polysilicon layer and the first silicon oxynitride layer.
The forming of the first line pattern may include forming a first line mask over the hard mask, forming a first sacrificial layer pattern over the first line mask, forming a first spacer pattern on sidewalls of the first sacrificial layer pattern, removing the first sacrificial layer pattern, forming the first line pattern by etching the first line mask using the first spacer pattern as an etch barrier, and removing the first spacer pattern.
The forming of the first sacrificial layer pattern may include forming a first sacrificial layer over the first line mask, forming a second silicon oxynitride layer over the first sacrificial layer, forming a first anti-reflection layer over the second silicon oxynitride layer, forming a first photoresist layer pattern, having a line type pattern, over the first anti-reflection layer, etching the first anti-reflection layer and the second silicon oxynitride layer by using the first photoresist layer pattern as an etch barrier, removing the first photoresist layer pattern and the first anti-reflection layer, and forming the first sacrificial layer pattern by etching the first sacrificial layer using the etched second silicon oxynitride layer as an etch barrier.
The forming of the first spacer pattern may include forming a spacer-forming insulation layer over the first line mask and the first sacrificial layer pattern, and etching the spacer-forming insulation layer in such a manner that the spacer-forming insulation layer remains on sidewalls of the first sacrificial layer pattern.
The first sacrificial layer pattern may have an etch selectivity with respect to the first spacer pattern. The first spacer pattern may have an etch selectivity with respect to the first line mask. The first line mask may be a polysilicon layer. The first sacrificial layer pattern may be a spin-on carbon (SOC) layer. The first spacer pattern may be an ultra low temperature oxide (ULTO) layer.
The removing of the first sacrificial layer pattern may be performed through an oxygen stripping process.
The forming of the second line pattern may include forming a second line mask over the hard mask and the first line pattern, forming a second sacrificial layer pattern over the second line mask, forming a second spacer pattern on sidewalls of the second sacrificial layer pattern, removing the second sacrificial layer pattern, and forming the second line pattern by etching the second line mask using the second spacer pattern as an etch barrier.
The second sacrificial layer pattern may have a stacked structure of a second anti-reflection layer and a second photoresist layer pattern. The forming of the second line pattern may further include forming a third silicon oxynitride layer over the second line mask, before the forming of the second sacrificial layer pattern.
The second line pattern may be formed of a material having an etch selectivity with respect to the first line pattern. The second spacer pattern may be formed of a material having an etch selectivity with respect to the second line mask.
The second line mask may be a spin-on carbon (SOC) layer. The second spacer pattern may be an ultra low temperature oxide (ULTO) layer.
In accordance with another exemplary embodiment of the present invention, a method for forming a contact hole of a semiconductor device may include forming a hard mask over an etch target layer, forming a first line mask over the hard mask, forming a first spacer pattern over the first line mask, forming a first line pattern by etching the first line mask using the first spacer pattern as an etch barrier, removing the first spacer pattern, forming a second line mask over the hard mask and the first line pattern, forming a second spacer pattern over the second line mask in a direction crossing the first line pattern, forming the second line pattern by etching the second line mask using the second spacer pattern as an etch barrier, removing the second spacer pattern, forming a mesh-type hard mask pattern by etching the hard mask, and forming a contact hole by etching the etch target layer using the mesh-type hard mask pattern as an etch barrier.
The method may further include forming a first hard mask between the hard mask and the first line mask, forming a second hard mask between the first hard mask and the first line mask, etching the second hard mask using the first and second line patterns as etch barriers, and etching the first hard mask using the etched second hard mask as an etch barrier, wherein the forming of the mesh-type hard mask pattern by etching the hard mask uses the etched first and second hard masks as etch barriers.
Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.
The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate, but also a case where a third layer exists between the first layer and the second layer or the substrate.
Referring to
Ultimately, the contact hole is formed by etching the etch target layer (not shown) using a mesh-type hard mask made from at least the polysilicon layer 10.
Returning to
Subsequently, the first photoresist layer pattern 17 is formed over the first anti-reflection layer 16. The first photoresist layer pattern 17 is a line type pattern, which is characterized by parallel line-shaped structures separated by a space. The space between patterns may be controlled in consideration of a spacer pattern which is formed subsequently.
Referring to
The etched first anti-reflection layer 16 (refer to
Referring to
Subsequently, the first SOC layer 14 (refer to
Referring to
Referring to
Subsequently, the first SOC layer pattern 14A (refer to
As a result, only the first spacer pattern 18A remains over the second polysilicon layer 13.
Referring to
Referring to
Therefore, the asymmetrical structure may be prevented from being transcribed during a subsequent process of etching a lower layer by removing the first spacer pattern 18A (refer to
Referring to
Subsequently, the second photoresist layer pattern 22 is formed over the second anti-reflection layer 21. The second photoresist layer pattern 22 is a line type pattern. Particularly, the second photoresist layer pattern 22 may be formed in such a manner that a projection of it crosses the first line pattern 13A (i.e., if the second photoresist layer pattern 22 was in the same plane as the first line pattern 13A, they would cross). Also, the second photoresist layer pattern 22 is formed to have a space between its structures that takes into consideration a spacer pattern which will be formed later. The second photoresist layer pattern 22 may be formed to have pattern characteristics similar to the first photoresist layer pattern 17 (refer to
Referring to
The second anti-reflection layer pattern 21A and the second photoresist layer pattern 22 function as sacrificial layers for forming a spacer pattern, which is formed later.
Referring to
Referring to
Subsequently, the second anti-reflection layer pattern 21A (refer to
As a result, only the second spacer pattern 23A remains over the third silicon oxynitride layer 20.
Referring to
Referring to
The second line pattern 19A crosses the first line pattern 13A, which remains and is partially exposed after etching the second SOC layer 19. The first line pattern 13A and the second line pattern 19A are used together as an etch mask when a mesh-type hard mask pattern for forming contact holes is formed.
The first line pattern 13A is not etched during the process for forming the second line pattern 19A due to its etch selectivity with respect to the second SOC layer 19.
Referring to
Since the second spacer pattern 23A (refer to
Therefore, it is possible to prevent the asymmetrical structure from being transcribed by removing the second spacer pattern 23A (refer to
Subsequently, the first silicon oxynitride layer 12 (refer to
Because the first line pattern 13A remains when the second line pattern 19A is formed and the two patterns cross, the first silicon oxynitride layer pattern 12A can be etched to form a mesh-type pattern, which has openings to expose parts of the amorphous carbon layer 11 below.
Referring to
The first line pattern 13A (refer to
The amorphous carbon layer 11 (refer to
Referring to
Subsequently, the first silicon oxynitride layer pattern 12A (refer to
Subsequently, the etch target layer (not shown) is etched using the hard mask pattern 10A as an etch barrier so as to form a contact hole. In
As described above, in the embodiment of the present invention, a Spacer Pattern Technology (SPT) process for forming a spacer pattern is performed twice to form line type patterns with crossing directions so as to form a mesh-type hard mask pattern. In particular, by removing a spacer pattern having an asymmetrical structure before a lower layer is etched, it is possible to prevent etch non-uniformity and pattern non-uniformity, which may be caused by the asymmetrical structure.
Also, the SPT process overcomes the limitation in resolution of the photoresist layer pattern.
While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Number | Date | Country | Kind |
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10-2010-0064952 | Jul 2010 | KR | national |