The field of the invention relates to thin-film microstructures formed by surface micromachining processes in the field of Micro-Electro-Mechanical-Systems (MEMS).
Although MEMS-based products are increasingly being used in commercial and research applications, the packaging of the MEMS microdevices is usually developed on a case-by-case basis in-house and remains as a significant obstacle to large scale commercial production. Due to the sensitive and fragile nature of the free standing microstructures formed in many MEMS devices, the packaging process often amounts to a significant portion (e.g., as much as 80-90%) of the cost of a MEMS-based product. The so called “on-wafer packaging” (also known as zero-level or device-level packaging) of MEMS devices on a single wafer, i.e., packaging the delicate devices in a protective housing on the wafer before the wafer is ready for dicing, has long been recognized as a promising approach, because it allows the use of packaging procedures similar to those used for regular electronics manufacturing in producing a large numbers of MEMS-based devices.
In general, the on-wafer packaging (or encapsulation) approaches fall into two categories: (1) wafer bonding packaging and (2) integrated thin-film packaging. In the wafer bonding approach, a separate substrate is bonded to the MEMS wafer to cap the MEMS components using a wide variety of bonding techniques. While wafer bonding has a proven track record and is being widely used in industry, integrated thin-film packaging has long been considered to be a potentially more cost effective approach for mass production.
In the so-called integrated thin-film packaging approach, the packaging process is carried out on the same wafer where the MEMS devices are fabricated by adding extra steps to the surface micromachining process used to construct the device. For example, an additional sacrificial layer is deposited on top of an unreleased microdevice and then covered by a thin-film structural layer that will eventually form a cavity and encapsulate the microdevice inside. The device is released after the sacrificial layer is removed through the etch holes opened in the structural layer (e.g., encapsulating shell). One known approach is to use wet or gas etchants that pass through a limited number of micrometer-sized etch holes that are lithographically opened in the encapsulation shell. The MEMS package is then sealed by conformal deposition of a thin-film on top of the encapsulation layer in an appropriate pressure condition.
Compared with wafer-bonding packaging techniques, integrated thin-film packaging has several advantages including: (1) the use of surface-micromachining batch fabrication processes, thereby avoiding the need for aligning two wafers and the challenges of bonding on “processed” (i.e., not smooth) surfaces; (2) the elimination of the seal ring, allowing much smaller volume cavities, therefore increasing the number of available dice per wafer; and (3) a lower topography. Thin-film encapsulation processes even allow the post-encapsulation processes for additional MEMS or IC steps, if desired.
Despite the anticipated advantages of integrated thin-film packaging, existing encapsulation methods suffer from a few drawbacks for on-wafer packaging. First, because of the lithography and etching techniques employed, the etch holes patterned in the encapsulation shell have a typical size of a few micrometers. Opening vertical etch holes in the encapsulation layer right above the device area is not desirable, because a significant amount of sealing material can diffuse through the etch holes and deposit on the MEMS device surfaces inside the cavity, thereby changing the device characteristics.
While this issue can be alleviated by utilizing laterally directed etch channels, such channels require relatively long times to remove the sacrificial materials out of the cavity, lowering the process throughput and even potentially degrading the mechanical properties of the structure material. Improperly designed lateral etch channels can also lead to excessive gas evacuation time during the sealing process. Consequently, despite more recent advances, the parasitic deposition of sealing material inside the cavity has not been fully prevented.
Polycrystalline silicon (polysilicon) thin-films have been found permeable if made very thin (nanometers) and potentially useful for integrated thin-film encapsulation. However, this thin-film is too thin and weak to serve as an encapsulating structural layer for typical MEMS devices. Thus, this method uses an additional layer of regular thin-film with etch windows, somewhat defeating the purpose of using permeable encapsulation layer.
There thus is a need for a thin-film encapsulation layer that is permeable yet structurally strong enough to freely stand as an encapsulation shell. The need for structural strength means that the use of very thin layers should be avoided. The need for permeability suggests that the pores should be very small so they are sealed quickly before the sealing material passes through them. Yet, the sacrificial material needs to be removed through the tiny pores. The two seemingly conflicting requirements can be met, if the pores are very small but highly populated. Considering all the requirements, it is desired to have a relatively thick (i.e., on the order of micrometers) encapsulation layer with highly populated nanometer-scale pores formed through the layer preferably in a normal orientation.
Moreover, because many MEMS-based devices use metals, which cannot withstand high processing temperatures, there is a need for thin-film encapsulation methods that avoid high-temperature processing steps. Metallic structures (e.g., gold, aluminum) are currently most commonly used in radio-frequency (RF) MEMS devices. These devices, however, cannot be packaged by integrated thin-film packaging if the processing includes high temperature steps.
In a first embodiment of the invention, a method of forming a free standing microstructure (e.g., a shell or encapsulation structure) includes providing a substrate and forming a sacrificial layer over the substrate. A thin-film structural layer is then formed over and around the sacrificial layer. Nanometer-scale pores are then introduced in the thin-film structural layer. For example, non-lithographic methods may be used to form an array of highly populated, directional pores having diameters in the nanometer range. Via the pores, at least a portion of the sacrificial layer is etched away or otherwise removed from underneath the thin-film structural layer. The thin-film structural layer may be sealed by application of a sealing layer on top thereof.
The free standing structural microstructure or encapsulation layer can be used to enclose one or more microdevices (e.g., MEMS devices). The microdevice may include, for example, an RF-based MEMS device. The process described herein may also be used to liberate or initiate free standing of one or more portions of the MEMS device contained beneath the thin-film structural microstructure or encapsulation layer.
In one aspect of the invention, the sacrificial layer is formed from a ceramic material such as phosphosilicate glass (PSG). In another aspect of the invention, the sacrificial layer may be formed from a polymer material such as, for instance, a photoresist material. In yet another embodiment of the invention, the sacrificial layer may be formed from a metallic material such as aluminum. The thin-film structural layer may be formed using, for example, a ceramic material (e.g., silicon), a metal (e.g., aluminum), or a polymer in combination with an appropriate sacrificial layer of material underlying the same.
In one aspect of the invention, the sacrificial layer is formed at a temperature at or below 300° C. In another aspect of the invention, the sacrificial layer is formed at a temperature that is at or around room temperature. Similarly, in one aspect of the invention, the structural layer may be deposited at or below 300° C. In yet another aspect, the structural layer may be formed at a temperature that is at or around room temperature. Again, similarly, in one aspect of the invention, the sealing layer may be deposited at or below 300° C. In yet another aspect, the sealing layer may be formed at a temperature that is at or around room temperature. In one aspect of the invention, the sacrificial layer, structural layer, and sealing layer are all formed at a temperature at or below 300° C. In yet another aspect, the sacrificial layer, structural layer, and sealing layer are all formed at a temperature that is at or around room temperature.
In one embodiment of the invention, a sacrificial layer is formed on the substrate, and a polymer structural layer is then deposited. The sacrificial layer can be either electrically conductive or non-conductive. Highly populated, highly directional nanopores can be introduced into the polymer layer via ion irradiation followed by etching. The sacrificial layer is then at least partially etched away or otherwise removed. Optionally, the structural layer may be sealed with a sealing layer. The sealing layer may be substantially impermeable to fluids.
In another embodiment of the invention, a sacrificial layer is formed on the substrate, and an aluminum structural layer is then deposited. The sacrificial layer can be either electrically conductive or non-conductive. Highly populated, highly directional nanopores can be introduced into the aluminum layer via anodization etching, which turns the aluminum into alumina at the same time. The sacrificial layer is then at least partially etched away or otherwise removed. If the sacrificial layer is electrically non-conductive, a seed layer is formed on the sacrificial layer before the structural layer and removed before the sacrificial etching. Optionally, the structural layer may be sealed with a sealing layer.
In still another embodiment of the invention, a sacrificial layer is formed on the substrate, and silicon structural layer, such as polysilicon, is then deposited. The sacrificial layer can be either electrically conductive or non-conductive. However, if a non-conductive material, such as a glass layer (e.g., phosphosilicate glass (PSG)) is used for the sacrificial layer, the silicon structural layer should be doped to be conductive. Highly populated, directional nanopores can be introduced into the structural layer via anodization etching. The sacrificial layer is then at least partially etched away or otherwise removed. Optionally, the structural layer may be sealed with a sealing layer.
A thin-film structural layer 16 is formed over the sacrificial layer 14. Pores are then introduced into the thin-film structural layer 16 through the use of, for example, an anodized etching process. The pores preferably are nanometer-sized pores. In certain embodiments, the structural layer 16 may be formed from a polymer, in which case the pores are introduced by a different method, for example, an ion-irradiation followed by etching. Following pore formation, at least a portion of the sacrificial layer is then etched or otherwise removed from underneath the thin-film structural layer 16.
With respect to anodized porous alumina, the typical pore structure is a hexagonal array of cylindrical-shaped pores with a bottom Al2O3 barrier layer. The pore diameter generally ranges from around 10 nm to around 300 nm. To form free standing microstructures, the bottom Al2O3 barrier layer needs to be removed to allow the diffusion of etchant(s) through the pores to etch away the sacrificial material.
With reference to
The etching process was stopped when the thin film became transparent. The structure of the bottom barrier layer during and after the anodization etching process was completed is shown in the SEM pictures in
The 100 Å Au layer 24 was needed to form the numerous thin arches. Without the existence of the Au layer 24, the Ti adhesion layer 22 would have been turned into an oxide layer by the electrolyte with a bottom barrier layer, similar to the typical pore morphology of porous alumina. Next, as best seen in
A SEM cross-sectional image of the porous alumina layer 16 is displayed in
The hermeticity of the encapsulation with the porous alumina thin-film layer 16 was studied by monitoring the pressure change inside the formed package through an encapsulated metal Pirani gauge 30. See
Referring now to
Vacuum sealing of the package 40 was performed by depositing a sealing layer 34. In a preferred aspect of the invention, the sealing layer 34 is substantially impermeable to fluids (e.g., liquids and gases). In this case, the sealing layer 34 was a PECVD low stress nitride layer of 2.5 μm thickness at 300° C. It should be understood, however, that the entire packaging process may be carried out at or below 300° C. For example, the entire packaging process may be carried out at or around room temperature if a room temperature sacrificial layer 14, 32 and sealing layer 34 are used. As seen in
The package 40 containing the Pirani gauge 30 was then intentionally ruptured to expose the free standing Pirani gauge 30 inside in addition to each layer of the structural layer 16. The Pirani gauge 30 was observed to be free standing in SEM images. See He and Kim, “A Low Temperature Vacuum Package Utilizing Porous Alumina Thin Film Encapsulation,” IEEE Conference on Micro Electro Mechanical Systems held in Istanbul Turkey, January, 2006, which is incorporated by reference as if set forth fully herein.
The pressure inside the sealed package 40 was obtained by matching the resistance-current curve of the sealed Pirani gauge 30 with the resistance-current curves of the Pirani gauge 30 calibrated at different known pressures.
Measurements were performed on test packages 40 to measure the extent to which the material of the sealing layer 34 was present inside the structural layer 16. Substantial encroachment of the sealing layer 34 material inside the package 40 would have been likely if lithographically-defined etch holes in the structural shell 16 were to be sealed. The test packages 40 had porous alumina cavities (1.5 μm thick) formed on a bare silicon substrate. After a 5000 Å PECVD oxide deposition layer was formed, the cavity was ruptured using a probe tip and the thickness of oxide on top of the silicon substrate inside the cavity was measured by a NANOSPEC® thin-film measurement system (available from NANOMETRICS, INC., Milpitas, Calif.) using a thin oxide program (low limit: 20 Å). For all the tested packages 40, a “less than 20 Å” result was obtained, indicating the porous alumina shell 16 effectively prevented the internal deposition of the sealing material 34 during the sealing process.
To investigate the RF performance of the porous alumina thin-film package 40, a CPW (Coplanar Waveguide) line (Cr/Au: 250/8000 Å) was packaged on a silicon substrate 12 with high resistivity (>2000 Ω*cm). Following a similar fabrication process as that shown in
Cross-sectional and optical microscopic views of the fabricated RF device 50 are shown in
The insertion loss introduced by the packaging structure was extracted from the difference between the measured insertion loss of a packaged CPW line and an un-packaged CPW line. As seen in
According to another embodiment of the invention, a free standing microstructure 70 is formed using porous polysilicon. Alternatively, the free standing encapsulation structure 70 may be formed from single crystal silicon.
In certain embodiments, the thin-film structural layer 16, 70 may be formed from polysilicon or aluminum. In still other embodiments, the thin-film structural layer 16 may be formed using type III-V materials. In particular, the material may include compounds formed with at least one group III element and at least one group V element. These include, by way of example, gallium phosphide (GaP), gallium arsenide (GaAs), indium arsenide (InAs), gallium antimonide (GaSb), and indium antimonide (InSb).
As best seen in
After dicing the wafer into 1 cm×1 cm dice, a photoresist mask layer 84 (
After 200 seconds of electrochemical etching at 4 mA/cm2 the porous region in the upper part of the polysilicon layer 80 was visually distinguishable from the solid region underneath. After 250 seconds of electrochemical etching, many trenches were present in the PSG sacrificial layer 76 located right underneath the polysilicon layer 80, signifying that the polysilicon layer 80 was turned porous through its entire thickness and thus HF in the electrochemical solution diffused through the porous polysilicon 80 to attack the PSG layer 76. An irregular etching pattern in the PSG layer 76 was observed. This indicated that pore growth inside the polysilicon layer 80 was not uniform along the thickness direction. It was hypothesized that the electrochemical etching current flows mainly along the polysilicon grain boundaries, resulting in preferential etching and thus a higher pore growth rate at the grain boundaries.
The electrochemical etching current was carefully adjusted to prevent the occurrence of electropolishing in the polysilicon layer 80 under the edge of the photoresist mask 84. In electrochemical etching, when the current density is higher than that of the first peak in the current-potential curve, electropolishing will take place instead of pore formation. However, higher current density and hence higher pore growth rate is preferred in this process in order to prevent the photoresist mask 84 from peeling off in the HF-ethanol electrochemical etching solution and to minimize etching undercut. Generally, a high-enough current density to keep the photoresist mask 84 intact during electrochemical etching but low-enough to prevent the lateral electropolishing was found when the current density was around 4 mA/cm2. After 255 seconds of etching, no electropolishing was observed, while the partly etched PSG layer 76 indicated that pores are formed through the entire thickness of the polysilicon 80 in the unmasked area.
Once the free standing encapsulation structure 70 was released, wrinkles and cracks were observed on most of the porous polysilicon structures 80, indicating the presence of high compressive stress in the layer 80. Prior to introduction of the pores, the polysilicon layer 80 was in a low stress condition. It is believed that the compressive stress was introduced in the porous polysilicon layer 80 due to large amount of H2 generated during the electrochemical etching process. Excessive hydrogen atoms tend to bond to silicon atoms, resulting in a lattice expansion of the Si—Si bond length and thus introducing the compressive stress in porous silicon layer 80. Although the hydrogen can be desorbed from the Si—H bond by annealing at medium temperature (e.g., above 400° C.), a challenge was presented because the porous polysilicon layer 80 starts to free-stand as a membrane or the like soon after the electrochemical etching process is complete, i.e., before annealing can be applied.
In this process, the time window for annealing is thus after the electrochemical etching front reaches the interface of the polysilicon layer 80 and the sacrificial PSG layer 76 and before the HF-based etching solution attacks PSG layer 76 enough to free the polysilicon layer 80 into a free standing structure. It was found that this operating window (i.e., when the pores reached the interface) can be determined by the observation of a sharp increase in electrode potential during the electrochemical etching step.
After the free standing encapsulation structure 70 was taken out of the etching setup and thoroughly cleaned, annealing was then performed using a rapid thermal annealing (RTA) process. In particular, the device 70 was quickly heated at 700° C. for 5 minutes in a nitrogen environment. The effect of the annealing process was noticeable. Porous polysilicon membranes 80 that were not subject to the annealing process were formed with thicknesses of only 100 μm in size. In contrast, porous polysilicon membranes 80 subject to the annealing process were formed with thicknesses as large as 600 μm without any cracks.
Because the HF-based electrochemical etching solution etches the sacrificial PSG layer 76 quickly after diffusing through the porous polysilicon layer 80, the window for annealing is small and accurate determination of this point is needed to stop the etching process. While the process was successful using one die at a time, it may not be as practical for an entire wafer under production conditions. However, a barrier layer (not shown) resistant to the electrolyte (e.g., silicon nitride) may be placed between the polysilicon layer 80 and the PSG layer 76 to solve the problem. The barrier layer can be later removed during the device release process.
With reference to
With reference to
With reference to
Then, as illustrated in
The sample was then thoroughly rinsed in DI water and methanol, followed by a supercritical CO2 drying step. Next, as seen in
The pressure inside the sealed cavity was measured from the encapsulated Pirani gauge 90. The resistance vs. current characteristics of a Pirani gauge 90 was first obtained while vacuum encapsulated. Without affecting the performance of the Pirani gauge 90, the seal on the top empty cavity was then broken intentionally with a probe tip. The entire sample was then placed in a pressure-controlled chamber, where the Pirani gauge 90 was calibrated against known pressures. The pressure inside the sealed cavity, extracted by matching the resistance of the Pirani gauge 90 while sealed with the calibration data obtained above, was around 200 mTorr.
A better interpretation of the data plotted in
where PE is the electrical power, Tavg is the average temperature across the Pirani gauge, ξ is the temperature coefficient of resistance (1000 ppm/° C. for polysilicon), Rb and R0 are the resistances of the microbridge at a given pressure and ambient pressure, respectively. After the thermal impedance of the Pirani gauge 90 was extracted by a linear curve fit applied to the power vs. temperature data measured at each calibration pressure, the data was plotted as shown in
To demonstrate the usefulness of this technique for common surface micromachining processes, the Multi-User MEMS Processes, or MUMPS, was selected to fabricate a micro-bridge device 120 encapsulated by the porous polysilicon shell 122. MUMPS is a popular commercial foundry service that provides cost-effective, proof-of-concept MEMS fabrication. One of the standard processes in the MUMPS program is PolyMUMPs, a three-layer polysilicon surface micromachining process, whose thickness data is listed in Table 1 below.
While embodiments of the present invention have been shown and described, various modifications may be made without departing from the scope of the present invention. The invention, therefore, should not be limited, except to the following claims, and their equivalents.
This Application claims priority to U.S. Provisional Patent Application No. 60/686,713 filed on Jun. 2, 2005. U.S. Provisional Patent Application No. 60/686,713 is incorporated by reference as if set forth fully herein.
The U.S. Government may have a paid-up license in this invention and the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Grant No. DAAH01-99-C-R220 and W31P4Q-05-P-R012 awarded by DARPA.
Number | Date | Country | |
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60686713 | Jun 2005 | US |