Patent Application
20190279869
The present disclosure generally relates to semiconductor devices and, more particularly, to enhanced materials and fabrication techniques for semiconductor devices.
Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of the charge carriers. For example, U.S. Patent Application No. 2003/0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices. Published U.S. Patent Application No. 2003/0034529 to Fitzgerald et al. discloses a CMOS inverter also based upon similar strained silicon technology.
U.S. Pat. No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an re-channel MOSFET is asserted to have a higher mobility.
U.S. Pat. No. 4,937,204 to Ishibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.
U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, U.S. Pat. No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.
U.S. Pat. No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO2/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.
An article entitled “Phenomena in silicon nanostructure devices” also to Tsu and published online Sep. 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/O superlattice is disclosed as useful in a silicon quantum and light-emitting devices. In particular, a green electroluminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density. One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon. An article to Luo et al. entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” published in Physical Review Letters, Vol. 89, No. 7 (Aug. 12, 2002) further discusses the light emitting SAS structures of Tsu.
Published International Application WO 02/103,767 A1 to Wang, Tsu and Lofgren, discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude. The insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer.
Published Great Britain Patent Application 2,347,520 to Mears et al. discloses that principles of Aperiodic Photonic Band-Gap (APBG) structures may be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, for example, the location of band minima, effective mass, etc., can be tailored to yield new aperiodic materials with desirable band-structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.
Furthermore, U.S. Pat. No. 6,376,337 to Wang et al. discloses a method for producing an insulating or barrier layer for semiconductor devices which includes depositing a layer of silicon and at least one additional element on the silicon substrate whereby the deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite.
Despite the existence of such approaches, further enhancements may be desirable for using advanced semiconductor processing techniques in certain applications.
A method for making a semiconductor device may include forming a recess in a substrate including a first Group IV semiconductor, forming an active layer comprising a Group III-V semiconductor within the recess, and forming a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The method may further include forming an impurity and point defect blocking superlattice layer adjacent the buffer layer.
More particularly, forming the impurity and point defect blocking superlattice layer may include forming a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and forming at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By way of example, the base semiconductor layers may comprise silicon and/or germanium. Moreover, the at least one non-semiconductor monolayer may include at least one of oxygen, nitrogen, fluorine, carbon and carbon-oxygen.
In accordance with one example embodiment, the impurity and point defect blocking superlattice layer may be formed between the substrate and the buffer layer. In accordance with another example, a first impurity and point defect blocking superlattice layer may be formed between the substrate and the buffer layer, and a second impurity and point defect blocking superlattice layer may be formed between the buffer layer and the active layer.
By way of example, the first Group IV semiconductor may comprise silicon, and the second Group IV semiconductor may comprise germanium. Furthermore, the Group III-V semiconductor may comprise InP, for example. Additionally, the method may also include forming a channel layer on the active layer, a gate on the channel layer, and a source and a drain on opposite sides of the gate. Moreover, the group III-V semiconductor of the active layer may comprise a first group III-V semiconductor, and the channel layer may comprise a second Group III-V semiconductor different than the first Group III-V semiconductor. By way of example, the second Group III-V semiconductor may comprise InGaAs. The source and drain may also comprise the second Group III-V semiconductor.
The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. However, many different forms may be implemented based upon the teachings set forth herein, and the disclosure should not be construed as limited to the specific example embodiments provided. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosed concepts to those skilled in the art. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.
Applicants theorize, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a “conductivity reciprocal effective mass tensor”, and Me−1 and Mh−1 for electrons and holes respectively, defined as:
for electrons and:
for holes, where f is the Fermi-Dirac distribution, EF is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nth energy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B.Z.), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.
Applicants' definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again Applicants theorize without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.
Applicants have identified improved materials or structures for use in semiconductor devices. More specifically, the Applicants have identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.
Referring now to
Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon. The energy band-modifying layers 50 are indicated by stippling in
The energy band-modifying layer 50 illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By “constrained within a crystal lattice of adjacent base semiconductor portions” it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bound together through the non-semiconductor monolayer 50 therebetween, as seen in
In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.
Applicants theorize without wishing to be bound thereto that energy band-modifying layers 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers 50 may also cause the superlattice 25 to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.
Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice 25. These properties may thus advantageously allow the superlattice 25 to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.
It is also theorized that semiconductor devices including the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.
The superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45n. The cap layer 52 may comprise a plurality of base semiconductor monolayers 46. The cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.
Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.
Each energy band-modifying layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example
It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to the atomic diagram of
In other embodiments and/or with different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.
Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.
It is theorized without Applicants wishing to be bound thereto that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The 4/1 repeating structure shown in
While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons and holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.
The lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice 25 may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.
Indeed, referring now additionally to
In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.
In
It can be seen that the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.
Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicants to further theorize that the 5/1/3/1 superlattice 25′ should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.
Turning to
However, the dislocations have a negative impact on the electronic devices that will eventually be built in the epitaxial material. Some approaches that have been used to reduce the number of defects that extend into the active area include graded buffer layers, aspect ratio trapping in pattern wafers, and elevated temperature annealing applied to the growth and post processing. Dislocation defects may also act as pathways for elements in the alloyed and compound semiconductors to diffuse into the underlying buffers and silicon. Atoms that diffuse along dislocations into the silicon may act as dopants in the silicon. An example would be indium gallium arsenide (InGaAs), and indium phosphide (InP) growth on a germanium buffer on a silicon substrate. An example of such a structure is set forth in Waldron et al., “Integration of InGaAs Channel n-MOS Devices on 200 mm Si Wafers Using the Aspect-Ratio-Trapping Technique”, Journal ECSTrans. Volume 45, Issue 4, Pages 115-128 (2012), which is hereby incorporated herein in its entirety by reference.
In accordance with an example implementation, one or more MST layers, such as those described above, may be incorporated in semiconductor devices such as the FINFET described in Waldron et al. to advantageously reduce dislocation defects. More particularly, beginning with a silicon substrate 101 with shallow trench isolation (STI) regions 102, a recess 103 is etched in the silicon between adjacent STI regions (
Rather than forming a germanium buffer layer directly on the silicon substrate 101 within the trench 103, as in the above-noted FINFET device, an MST impurity and point defect blocking superlattice layer 125a may first be formed (
Germanium with a diamond cubic structure, which has a lattice parameter of 5.658 Å, may be used as the buffer layer 104 above the silicon substrate 101, which also has a diamond cubic crystal structure with a lattice parameter of 5.431 Å. The germanium lattice parameter is more closely matched to the Group III-V semiconductor active layer 105 that will be subsequently deposited. In the present example, the Group III-V compound semiconductor is InP, which has a zinc blend crystal structure with a lattice parameter of 5.869 Å, although other suitable materials may also be used. For example, tin is larger than Ge and buffers of GeSn may be deposited such that an alloy with lattice matching to the compound semiconductor (i.e., compound semiconductors with lattice parameter greater than Ge) may be achieved.
In a typical process where the germanium is deposited directly on a silicon substrate, many dislocations are generated, relaxing the strain due to germanium lattice mismatch with silicon. The geometry of the recess 103 bottom, in conjunction with epitaxial growth between the STI side walls 102, cause many of the dislocations to propagate along <111> planes that are at 57.7° angles to the bottom growth surface, to be annihilated when they meet the STI side walls. Yet, the advantageous “Aspect Ratio Trapping” (ART) defect reduction provided by the superlattice layer 125a may not be possible with growth on un-patterned substrates. More particularly, even with the current state of the art techniques noted above, there may still be dislocations that make it to the surface where the active devices will be built, as will be appreciated by those skilled in the art.
In the present example, an additional MST impurity and point defect blocking superlattice layer 125b is also formed above the germanium layer, and prior to formation of the active layer 105, to provide further dopant blocking and defect trapping as well. By way of example, the first and second superlattice'layers 125a, 125b may have a 4/1 or 3/1-5/1 configuration as described above, or other configurations (e.g., 12/1, etc.). They may have the same layer configuration, or different layer configurations may be used for the two superlattices 125a, 125b. Moreover, the same or different materials may be used for the different superlattices. For example, the base semiconductor in the lower superlattice layer 125a may be silicon, while the base semiconductor in the upper superlattice layer 125b may be silicon germanium or pure germanium. However, it should be noted that the second superlattice layer 125b is optional and need not be included in all embodiments. It should also be noted that the superlattices 125a, 125b are schematically shown as exaggerated long and short dash lines in the drawings, and the buffer layer 103 is schematically shown as an exaggerated solid line, for clarity of illustration.
Without the impurity and point defect blocking superlattice layer 125a and/or 125b, regions of silicon in the substrate 101 just below the germanium buffer layer 104 will tend to form that are heavily doped with phosphorus from the active InP layer 105 diffusing into the silicon. These impurities make their way into the silicon substrate 101, at an enhanced rate, along the above-described defects. Yet, the blocking/gettering features of the MST material will advantageously inhibit the movement of impurities into the substrate.
In addition to dopant blocking of impurities from one layer to the next, use of the MST superlattice layer 125a and/or 125b provide a compliant substrate to allow stress related defects to be generated earlier in the growth process. The early nucleation will increase the probability of the growth defects being annihilated early such that fewer reach the active area of the device 100. Early nucleation and annihilation of defects may advantageously reduce the height necessary for the compound semiconductor to be grown between the STI regions 102 before acceptable defect levels have been achieved.
After formation of the active layer 105, a Group III-V channel layer 106 is formed on the active layer (
Generally speaking, the above-described approach of including one or more MST impurity and point defect blocking layers to epitaxially grown structures may be used where it is desired to reduce/eliminate strain related to epitaxial mismatch, and to prevent elements of each individual layer from intermixing. That is, this approach provides a way to block the intermixing of elemental species between epitaxial layers of different materials. It also takes advantage of the MST material as a compliant layer for reducing defects that result when performing heteroepitaxial growth. By way of example, the above described approach may advantageously be implemented in logic devices (e.g., including FINFETs), as well as for heteroepitaxial growth related to optical material integration into silicon technology.
Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.
