The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. In the figures:
Embodiments of the present invention provide a method of fabricating a plurality of planar nanowires surround gate semiconductor device. The planar nanowires can be formed between a source and a drain over an insulating layer of a semiconductor substrate. The gate stack can then be grown or deposited all-around the planar nanowires. The gate stack can then be etched and patterned. During this process, the planar nanowires can be severed between the gate and the source, and between the gate and the drain, leaving portions of the gate-all-around planar nanowires remaining between the source and the drain. These portions can serve as the active region of the channel. The remaining gate-all-around planar nanowires can then be epitaxially regrown to reconnect to the source and the drain.
Reference will now be made in detail to the exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, merely exemplary.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of “less than 10” can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, any and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5.
The insulating layer 120 formed on the semiconductor substrate 110 can be any dielectric insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, or other known dielectric. Several commercial Silicon-on-Insulator (SOI) methods can be used to fabricate the insulating layer 120. For example, a silicon oxide layer can be thermally grown on the semiconductor substrate 110 in an O2 or H2O ambient. Alternatively, a silicon nitride layer can be formed by nitrifying the semiconductor substrate 110 in a nitrogen ambient. Moreover, a silicon oxynitride layer can be deposited on the surface of semiconductor substrate 110 by chemical vapor deposition (CVD). The thickness of the silicon oxide or silicon nitride layer can be from about 10 angstroms to a few thousand angstroms.
The source 130, the drain 131 and the gap 132 can be formed in a semiconductor layer that is formed over the insulating layer 120. When the semiconductor layer is formed of single crystal silicon, a silicon-on-insulator (SOI) substrate can be used. In certain embodiments, the semiconductor layer can be germanium (Ge), an alloy semiconductor, such as silicon-germanium (SiGe), silicon-germanium carbon (SiGeC), silicon-carbon (SiC), or a compound semiconductor, such as gallium arsenide (GaAs), gallium nitride (GaN), indium antimonide (InSb), gallium indium arsenide (GaInAs). In some embodiments, a channel is then formed in the gap 132 between the source 130 and the drain 131.
The planar semiconductor fins 133 can be formed in one or more steps. For example, the planar semiconductor fins 133 can be formed by patterning the semiconductor layer overlying the insulating layer 120 using a lithographical and etching process, such as a wet etching process or a dry etching process (e.g. plasma etching or reactive ion etching (RIE). Lithographical and the etching process are well-known to one of the ordinary skills in the art.
According to various embodiments, the planar semiconductor nanowires 134 can be formed by annealing the planar semiconductor fins 133 in a hydrogen gas ambient. The annealing process encourages the migration of semiconductor atoms in the semiconductor fins 133 and facilitates the rounding of planar nanowires 134 into more rounded cross-sections. The annealing temperature can range from about 600 to about 1000 degrees Celsius. And, the annealing pressure can range from about a few mTorr to about 760 mTorr. For example, the semiconductor fins 133 shown in
The diameter of the annealed nanowires 134 can be from about 40 nm to less than about 5 nm. After the annealing process, the nanowires 134 can be suspended above the insulating layer 120 as shown in
The gate pattern 141 can be formed by patterning the gate stack 140 and source and drain regions. For example, a lithographical process and a subsequent etching process can be used to pattern the gate stack 140 to form a certain shaped gate, such as the T-shaped gate 141 as shown in
The gate dielectric 151 can be any high-k dielectric material. For example, the gate dielectric 151 can be a thermal oxide layer or a thermal nitride layer that is formed through thermal oxidation or thermal nitrification. Alternatively, the gate dielectric 151 can comprise at least one of: a transition metal oxide, such as tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), hafnium oxide (HfO2), gadolinium oxide (Ga2O3), scandium oxide (Sc2O3), a silicate alloy, such as zirconium silicate alloy or hafnium silicate alloy, or a complex oxide, such as gadolinium scandium oxide (GdScO3), dysprosium oxide (DyScO3) or hafnium titanium oxide (HfTiO4), and other high k dielectrics. The gate dielectric 151 can be formed by, for example, CVD techniques or atomic layer deposition (ALD) techniques.
The gate electrode 152 can then be stacked on the gate dielectric 151. The gate electrode 152 can be formed of any conductive materials, such as a metal including copper, gold, platinum, palladium, aluminum, ruthenium, titanium or tantalum, a metal compound including tantalum carbide (TaC), tantalum nitride (TaN), titanium nitride (TiN), tantalum silicon nitride (TaSiN)), or a semiconductor material (e.g. poly-silicon or poly-silicon-germanium, and others. The deposition of the gate electrode 152 can be performed by physical vapor deposition (PVD) techniques such as e-beam techniques or sputtering, CVD techniques, ALD techniques, or electroplating techniques.
During the formation of the gate 141, etching processes can be performed in steps. For example, the gate dielectric 151 can be etched after an etching step of the gate electrode 152. The gate electrode 152 can be etched using a wet etching process or a dry etching process (e.g. plasma etching or RIE). The high k gate dielectric 151 can be etched using a dry etching process (e.g. plasma etching, RIE) or a wet etching process.
The portions 150 may be epitaxially regrown to reconnect them to the source 130 and the drain 131. The reconnection occurs in such a way that the epitaxial growth from the portions of nanowires 150 meet the epitaxial growth from the source 130 and drain 131. Typically, in epitaxial regrowth, a single crystalline material is desired to initiate the growth. Therefore, any single-crystalline material can be used as the re-grown nanowires in the portions 150. Materials in single crystalline form are known to those skilled in the art, and include, but are not limited to, silicon (Si), germanium (Ge), gallium (Ga), gallium arsenide (GaAs), indium phosphide (InP), silicon germanium (SiGe), gallium aluminum arsenide (GaAlAs), etc.
In some embodiments, the crystal orientation of the facets at portions of nanowires 150 can match the crystal orientation of the source and drain materials. Accordingly, during epitaxially regrowth, the crystals growing from both portions of nanowires 150 and the source 130 and the drain 131 can have the same crystal orientation. It should be noted that the crystal-matched regrowth can meet at the source and drain region other than in the gate. Therefore, any mismatches in plane during the epitaxial regrowth will be in the source and drain region. In some cases, such plane-mismatches can affect the performance of the device 100. For example, plane-mismatches may cause junction leakage. Yet any junction leakage can be terminated at the interface with the insulating layer 120, as shown in
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. Nonetheless, it is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.