Patent Grant
8093114
Not applicable
Not applicable
The present invention is directed to integrated circuits. More particularly, the invention provides a method for making a split dual gate field effect transistor. Merely by way of example, the invention has been applied to a logic system. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as a given process, device layout, and/or system design often work down to only a certain feature size.
An example of such a limit is how to reduce the transistor leakage current and improve the transistor drive current. For example, reducing the source-drain voltage of a transistor can lower the active power, but doing so often reduces the transistor drive current. The transistor drive current can be improved by reducing the threshold voltage and thinning the gate dielectric, but such actions often raise the transistor leakage current.
From the above, it is seen that an improved method for making a transistor structure is desired.
The present invention is directed to integrated circuits. More particularly, the invention provides a method for making a split dual gate field effect transistor. Merely by way of example, the invention has been applied to a logic system. But it would be recognized that the invention has a much broader range of applicability.
In a specific embodiment, the invention provides a method for making a semiconductor device with at least two gate regions. The method includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface. The forming a first gate region and a second gate region includes forming an insulation region on the surface by at least removing a part of the gate layer, and the first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region, and the first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region, and the second channel is from the source region to the drain region.
According to another embodiment of the present invention, a method for making a semiconductor device with at least two gate regions includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region, and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first spacer region. The first spacer region is in contact with the gate layer. Also, the method includes forming a second spacer region, and the second spacer region is in contact with the gate layer. Additionally, the method includes removing at least a part of the gate layer to form a first gate region, a second gate region, and an insulation region on the surface. The first gate region and the second gate region are separated by the insulation region.
According to yet another embodiment of the present invention, a method for making a semiconductor device with at least two gate regions includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region, and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface, and forming a first spacer region. The first spacer region is in contact with the gate layer. Also, the method includes forming a second spacer region, and the second spacer region is in contact with the gate layer. Additionally, the method includes removing at least a part of the gate layer to form a first gate region, a second gate region, and an insulation region on the surface. The first gate region and the second gate region are separated by the insulation region. The first gate region is associated with a first channel related to a first channel length, and the first channel length is equal to or shorter than 200 nm. The insulation region is associated with a width in a direction from the first gate region to the second gate region, and the width ranges from 10 nm to 10,000 nm.
Many benefits are achieved by way of the present invention over conventional techniques. Some embodiments of the present invention provide a new method for making a new planar split dual gate transistor device. Certain embodiments of the present invention provide a method for making dual gates that can be biased independently. For example, the independent gate biases can provide dynamical control of the device characteristics such as threshold voltage, sub-threshold swing, and/or the saturation drain current. Some embodiments of the present invention can be used to make a device that significantly reduces transistor leakage current. Certain embodiments of the present invention provide a method for making a device that has adjustable threshold voltage without varying gate oxide thickness or doping profile.
Various additional objects, features and advantages of the present invention can be more fully appreciated with reference to the detailed description and accompanying drawings that follow.
The present invention is directed to integrated circuits. More particularly, the invention provides a method for making a split dual gate field effect transistor. Merely by way of example, the invention has been applied to a logic system. But it would be recognized that the invention has a much broader range of applicability.
The above sequence of processes provides a method according to an embodiment of the present invention. Other alternatives can also be provided where processes are added, one or more processes are removed, or one or more processes are provided in a different sequence without departing from the scope of the claims herein. Future details of the present invention can be found throughout the present specification and more particularly below.
At the process 2110, one or more shallow trench isolations are formed.
As shown in
In one embodiment, the following processes are performed:
At the process 2115, one or more doped wells are formed.
As shown in
In one embodiment, the following processes are performed:
For example, the following additional processes are performed for NMOS transistor:
In another example, the following additional processes are performed for PMOS transistor:
At the process 2120, one or more gate regions are formed for splitting.
As shown in
In one embodiment, the following processes are performed:
At the process 2125, one or more LDD regions and one or more spacer regions are formed.
As shown in
In one embodiment, the following processes are performed:
At the process 2130, one or more heavily doped source regions and one or more heavily doped drain regions are formed.
As shown in
In one embodiment, the following processes are performed:
At the process 2135, split dual gates are formed.
As shown in
In one embodiment, the following processes are performed:
In another embodiment, the following processes are performed to form the dual gate regions 2710 and 2720:
At the process 2140, one or more salicide layers are formed.
As shown in
In one embodiment, the following processes are performed:
In another embodiment, to form the insulation layer 2822, a photolithography is performed to pattern the SAB layer. The SAB photo mask is aligned to Active Area (AA) layer mark, for example, OVERLAY SAB/AA=±0.07 μm. After the photolithography, the SAB layer is etched by plasmas dry etch and then wet etch. For example, the wet etch process uses the chemical 49% HF: H2O (1:100) solvent at the temperature of 22.5° C.˜23.5° C. for 270 seconds.
At the process 2145, one or more inter-layer dielectric layer is formed.
As shown in
In one embodiment, the following processes are performed:
At the process 2150, one or more contact layers are formed.
As shown in
In one embodiment, the following processes are performed:
At the process 2155, one or more metal layers are formed.
As shown in
In one embodiment, the following processes are performed to form a metal layer:
In another embodiment, at least the following additional processes are performed to form additional metal layers:
At the process 2160, one or more passivation layers are formed.
As shown in
In one embodiment, the following processes are performed to form a metal layer:
According to yet another embodiment of the present invention, a method for making a semiconductor device with at least two gate regions includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first gate region and a second gate region on the surface. The forming a first gate region and a second gate region includes forming an insulation region on the surface by at least removing a part of the gate layer, and the first gate region and the second gate region are separated by the insulation region. The first gate region is capable of forming a first channel in the substrate region, and the first channel is from the source region to the drain region. The second gate region is capable of forming a second channel in the substrate region, and the second channel is from the source region to the drain region. For example, the method is implemented according to the method 2100 and/or the method 3300.
According to yet another embodiment of the present invention, a method for making a semiconductor device with at least two gate regions includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region, and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface and forming a first spacer region. The first spacer region is in contact with the gate layer. Also, the method includes forming a second spacer region, and the second spacer region is in contact with the gate layer. Additionally, the method includes removing at least a part of the gate layer to form a first gate region, a second gate region, and an insulation region on the surface. The first gate region and the second gate region are separated by the insulation region. For example, the method is implemented according to the method 2100 and/or the method 3300.
According to yet another embodiment of the present invention, a method for making a semiconductor device with at least two gate regions includes providing a substrate region including a surface. Additionally, the method includes forming a source region in the substrate region by at least implanting a first plurality of ions into the substrate region, and forming a drain region in the substrate region by at least implanting a second plurality of ions into the substrate region. The drain region and the source region are separate from each other. Moreover, the method includes depositing a gate layer on the surface, and forming a first spacer region. The first spacer region is in contact with the gate layer. Also, the method includes forming a second spacer region, and the second spacer region is in contact with the gate layer. Additionally, the method includes removing at least a part of the gate layer to form a first gate region, a second gate region, and an insulation region on the surface. The first gate region and the second gate region are separated by the insulation region. The first gate region is associated with a first channel related to a first channel length, and the first channel length is equal to or shorter than 200 nm. The insulation region is associated with a width in a direction from the first gate region to the second gate region, and the width ranges from 10 nm to 10,000 nm. For example, the method is implemented according to the method 2100 and/or the method 3300.
Although the above has been shown using a selected group of components for the device 100, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. For example, the device 100 is an NMOS transistor. In another example, the device 100 is a PMOS transistor. Further details of these components are found throughout the present specification and more particularly below.
In one embodiment, the substrate region 110 is made of a semiconductor material. For example, the semiconductor material is silicon. The semiconductor substrate region 110 is intrinsic or doped to p-type or n-type. For example, the substrate region 110 is doped to p-type, with a dopant concentration ranging from 1.0×1015 cm−3 to 2.0×1015 cm−3. In another example, the substrate region 110 is doped to n-type, with a dopant concentration ranging from 1.0×1015 cm−3 to 2.0×1015 cm−3.
The source region 120 and the drain region 130 are doped to n-type or p-type. For example, the source region 120 is doped to n-type with a dopant concentration ranging from 1.0×1018 cm−3 to 1.0×1019 cm−3, and the drain region 130 is doped to n-type with a dopant concentration ranging from 1.0×1018 cm−3 to 1.0×1019 cm−3. In another example, the source region 120 is doped to p-type with a dopant concentration ranging from 1.0×1018 cm−3 to 1.0×1019 cm−3, and the drain region 130 is doped to p-type with a dopant concentration ranging from 1.0×1018 cm−3 to 1.0×1019 cm−3.
The gate dielectric region 180 is located on the top surface 112 of the substrate region 110. For example, the gate dielectric region 180 is made of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In another example, the gate dielectric region is a dielectric layer. The gate regions 140 and 150 and the insulation region 160 are located on the gate dielectric region 180. For example, the gate regions 140 and 150 each are made of polysilicon. As shown in
The spacer regions 170 and 172 are located on the top surface 112. The spacer region 170 is in direct contact with the gate regions 140 and 150 and the insulation region 160 on one side, and the spacer region 172 is in direct contact with the gate regions 140 and 150 and the insulation region 160 on another side. For example, the spacer regions 170 and 172 each are made of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.
As shown in
The source region 120 has a width 124, and the drain region 130 has a width 134. For example, the width 124 ranges from 10 nm to 20,000 nm. In another example, the width 134 ranges from 10 nm to 10,000 nm. In one embodiment, the widths 124 and 134 are the same. In another embodiment, the widths 124 and 134 are different. The gate region 140 has a length 146, and the gate region 150 has a length 156. For example, the length 146 ranges from 10 nm to 1,000 nm. In another example, the length 156 ranges from 10 nm to 1,000 nm. In one embodiment, the lengths 146 and 156 are the same. In another embodiment, the lengths 146 and 156 are different. The gate region 140 has a width 148, the gate region 150 has a width 158, and the insulation region 160 has a width 168. For example, the total width for the width 148, the width 158, and the width 168 is equal to the width 124 and/or the width 134. In another example, the width 148 ranges from 10 nm to 15,000 nm. In yet another example, the width 158 ranges from 10 nm to 15,000 nm. In yet another example, the width 168 ranges from 10 nm to 15,000 nm. In yet another example, the width 168 ranges from 10 nm to 10,000 nm. In one embodiment, the widths 148 and 158 are the same. In another embodiment, the widths 148 and 158 are different.
As shown in
The present invention has various advantages. Some embodiments of the present invention provide a new method for making a new planar split dual gate transistor device. Certain embodiments of the present invention provide a method for making dual gates that can be biased independently. For example, the independent gate biases can provide dynamical control of the device characteristics such as threshold voltage, sub-threshold swing, and/or the saturation drain current. Some embodiments of the present invention can be used to make a device that significantly reduces transistor leakage current. Certain embodiments of the present invention provide a method for making a device that has adjustable threshold voltage without varying gate oxide thickness or doping profile.
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006 1 0023749 | Feb 2006 | CN | national |
This application is a divisional application and claims priority to U.S. patent application Ser. No 11,377,236, now U.S. Pat. No. 7,582,517, which will issue on Sep. 1, 2009, which claims priority to Chinese Patent Application No. 200610023749.3, filed Feb. 6, 2006, commonly assigned and incorporated by reference herein for all purposes. The following two commonly-owned co-pending applications, including this one, are being filed concurrently and the other one is hereby incorporated by reference in its entirety for all purposes: 1. U.S. patent application Ser. No. 11/377,936, in the name of Deyuan Xiao, Gary Chen, Tan Leong Seng, and Roger Lee, titled, “Split Dual Gate Field Effect Transistor,”; and 2. U.S. patent application Ser. No. 11/377,236, in the name of Deyuan Xiao, Gary Chen, Tan Leong Seng, and Roger Lee, titled, “Method for Making Split Dual Gate Field Effect Transistor,”.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4047199 | Kataoka et al. | Sep 1977 | A |
| 4063273 | Mueller | Dec 1977 | A |
| 5442209 | Chung | Aug 1995 | A |
| 5691215 | Dai et al. | Nov 1997 | A |
| 5751033 | Miya | May 1998 | A |
| 5828079 | Mizuno et al. | Oct 1998 | A |
| 5885887 | Hause et al. | Mar 1999 | A |
| 5923067 | Voldman | Jul 1999 | A |
| 6157062 | Vasanth et al. | Dec 2000 | A |
| 6548870 | Lee | Apr 2003 | B1 |
| 6689650 | Gambino et al. | Feb 2004 | B2 |
| 6714456 | Ogura et al. | Mar 2004 | B1 |
| 7045849 | Chen et al. | May 2006 | B2 |
| 7199434 | Li et al. | Apr 2007 | B2 |
| 7279740 | Bhattacharyya et al. | Oct 2007 | B2 |
| 7582517 | Xiao et al. | Sep 2009 | B2 |
| 20020127763 | Arafa et al. | Sep 2002 | A1 |
| 20040161919 | Cha et al. | Aug 2004 | A1 |
| 20050272256 | Wang | Dec 2005 | A1 |
| 20060008964 | Mineji | Jan 2006 | A1 |
| 20060154424 | Yang et al. | Jul 2006 | A1 |
| 20060270239 | Triyoso | Nov 2006 | A1 |
| 20060279332 | Wich | Dec 2006 | A1 |
| 20070020900 | Jain | Jan 2007 | A1 |
| Number | Date | Country |
|---|---|---|
| 2038669 | May 1989 | CN |
| 1198008 | Nov 1998 | CN |
| Number | Date | Country | |
|---|---|---|---|
| 20100087040 A1 | Apr 2010 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11377236 | Mar 2006 | US |
| Child | 12549192 | US |
