METHOD FOR MANUFACTURING CONDUCTIVE CIRCUIT BOARD AND CONDUCTIVE CIRCUIT BOARD MADE THEREFROM

Abstract

A method for manufacturing a conductive circuit board includes the steps of: preparing a substrate having opposite upper and lower surfaces, and at least one via hole extending through the upper and lower surfaces and defined by an inner surface; forming a compound metal layer on at least one of the upper surface and the lower surface of the substrate and on the inner surface; etching the compound metal layer by a laser beam, so that a patterned metal circuit layer having a predetermined pattern formed on the substrate; and forming a surface finish layer on a top surface of the patterned metal circuit layer, so as to form a conductive circuit layer. A conductive circuit board manufactured therefrom is also enclosed.

Description

FIELD OF THE DISCLOSURE

The disclosure relates to a method for manufacturing a conductive circuit board and a conductive circuit board made therefrom.

BACKGROUND OF THE DISCLOSURE

The demand for high power light emitting diode (LED) has multiplied in recent years, so that ceramic circuit boards with good heat dissipation have also attracted the attention of the lighting industry. In the related technology industry of ceramic circuit boards, direct plated copper (DPC) substrates are widely favored by the industry.

Referring to FIGS. 1A to 1G, an existing method for manufacturing a DPC substrate includes steps (A) to (G).

In step (A), with reference to FIG. 1A, a ceramic substrate 10 is formed with a plurality of via holes 100 (only one via hole 100 is shown in FIGS. 1A to 1G to simplify the drawings) that extend through an upper surface 101 and a lower surface 102 thereof by laser drilling. Each via hole 100 is defined by an inner surface 1001. In step (B), with reference to FIG. 1B, a metal base layer 111 is sputtered on the ceramic substrate 10 to cover the upper and lower surfaces 101 and 102 of the ceramic substrate 10 and the inner surfaces 1001 defining the via holes 100.

In step (C), with reference to FIG. 1C, a patterned dry film 12 having a predetermined pattern is covered on the metal base layer 111 by photolithography. The predetermined pattern of the patterned dry film 12 can expose portions 1111 of the metal base layer 111 corresponding to the upper and lower surfaces 101 and 102 of the ceramic substrate 10. In step (D), with reference to FIG. 1D, a patterned copper plating layer 13 is directly plated on the metal base layer 111 to increase the thickness thereof.

In step (E), with reference to FIG. 1E, the patterned strip film 12 is stripped from the metal base layer 111 to expose another portions 1112 of the metal base layer 111 covered by the same. In step (F), with reference to FIG. 1F, the another portions 1112 of the metal base layer 111 are etched, so that each portion 1111 of the metal base layer 111 forms a patterned metal base layer 11 that partially exposes a corresponding one of the upper and lower surfaces 101 and 102 of the ceramic substrate 10. The patterned metal base layer 11 and the patterned copper plating layer 13 located at each portion 1111 of the metal base layer 111 together form a patterned metal circuit layer 14. In step (G), with reference to FIG. 1G, a metal protective layer 15 is electroplated on the patterned metal circuit layer 14.

Although the existing method for manufacturing a DPC substrate can achieve the purpose of forming the patterned metal circuit layer 14 and the metal protective layer 15 on the ceramic substrate 10, to complete the patterned metal circuit layer 14, apart from the need to perform the yellow light lithography process in step (C), there is still the need to strip the patterned dry film 12 in step (E) and to etch away the another portions 1112 of the metal base layer 111 in step (F), only then can the patterned metal base layer 11 and the patterned copper plating layer 13 together form the patterned metal circuit layer 14. It is well known to those skilled in the related technical field of DPC that the yellow light lithography process described in step (C) must go through the following three substeps: (C1) attaching a dry film; (C2) covering the dry film with a photomask to expose the dry film through an exposure machine; and (C3) developing the exposed dry film to obtain the patterned dry film 12. Through the aforesaid description, it is apparent that, in order to complete the patterned metal circuit layer 14, multiple steps must be performed, so that the manufacturing process of the existing method is very complicated.

Furthermore, it should be noted that a predetermined pattern defining the patterned metal circuit layer 14 is designed according to the application requirements of the downstream industry. However, the patterned metal circuit layer 14 can only expose partial areas of the upper and lower surfaces 101 and 102 of the ceramic substrate 10, but not the inner surfaces 1001. Therefore, the patterned metal circuit layer 14 cannot meet the requirements of circuit design for the relevant manufacturers who need to design circuit patterns in the via holes 100 of the ceramic substrate 10.

SUMMARY OF THE DISCLOSURE

Therefore, an object of the present disclosure is to provide a method for manufacturing a conductive circuit board that can simplify the production process and meet the needs of the industry in circuit design.

According to this disclosure, the method for manufacturing a conductive circuit board comprises the steps of: preparing a substrate, the substrate having an upper surface and a lower surface opposite to each other, and at least one via hole extending through the upper surface and the lower surface and defined by an inner surface; forming a compound metal layer on at least one of the upper surface and the lower surface of the substrate and on the inner surface of the substrate; etching the compound metal layer by a laser beam, so that the at least one of the upper surface and the lower surface of the substrate and the inner surface are formed with a patterned metal circuit layer having a predetermined pattern for exposing a portion of the at least one of the upper surface and the lower surface of the substrate and a portion of the inner surface; and forming a surface finish layer on a top surface of the patterned metal circuit layer, so as to form a conductive circuit layer.

Another object of this disclosure is to provide a conductive circuit board manufactured from the above method.

According to this disclosure, the conductive circuit board includes a substrate and a metal circuit layer. The substrate has opposite upper and lower surfaces, and at least one via hole extending through the upper and lower surfaces and defined by an inner surface. The metal circuit layer is formed on the at least one of the upper and lower surfaces of the substrate and on the inner surface. The metal circuit layer has a predetermined pattern for exposing a portion of the at least one of the upper and lower surfaces of the substrate and a portion of the inner surface.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiment with reference to the accompanying drawings. It is noted that various features may not be drawn to scale.

FIGS. 1A to 1G are fragmentary sectional views illustrating the steps involved in an existing method for manufacturing a direct plated copper (DPC) substrate.

FIGS. 2A to 2E are fragmentary sectional views illustrating the steps involved in a method for manufacturing a conductive circuit board according to a first embodiment of the present disclosure.

FIG. 3 is a schematic top view of a substrate prepared in step (a) of the first embodiment.

FIG. 4 is a schematic top view of an alternative form of the substrate.

FIG. 5 is a fragmentary sectional view of the conductive circuit board obtained after step (e) of the first embodiment.

FIG. 6 is an enlarged perspective view of an encircled portion of FIG. 5.

FIGS. 7A to 7D are fragmentary sectional views illustrating the steps involved in a method for manufacturing the conductive circuit board according to a second embodiment of the present disclosure.

FIGS. 8A to 8B are fragmentary sectional views illustrating the steps involved in a method for manufacturing the conductive circuit board according to a third embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

First Embodiment

A method for manufacturing a conductive circuit board according to an embodiment of the present disclosure includes steps (a) to (e), which will be described in detail below in combination with FIGS. 2A to 2E.

In step (a), with reference to FIG. 2A, a substrate 2 is prepared. The substrate 2 has opposite upper and lower surfaces 21, 22, and a plurality of via holes 20 (only one via hole 20 is shown in FIGS. 2A to 2E to simplify the drawings) extending through the upper and lower surfaces 21, 22. Each via hole 20 is defined by an inner surface 201, and is formed by laser drilling or blade dicing. Each via hole 20 may be an elongated through hole having two opposite closed ends, as shown in FIG. 3, or one end closed and the other end open, as shown in FIG. 4. Further, the substrate 2 suitable for use in this step is made of an insulating material selected from the group consisting of ceramics and polymers. The substrate 2 made of a ceramic material is exemplified in this embodiment, but not limited thereto.

In step (b), with reference to FIG. 2B, a metal base layer 301 is formed on each of the upper and lower surfaces 21, 22 of the substrate 2 and on each inner surface 201 that defines each via hole 20. The metal base layer 301 may be formed by a physical vapor deposition (PVD) or chemical vapor deposition (CVD) method. In this embodiment, the metal base layer 301 is formed by a physical vapor deposition (PVD) method. The PVD method may be selected from one of sputtering and evaporation. In this step, the metal base layer 301 is a titanium-copper (Ti/Cu) multilayer film formed by sputtering, but not limited thereto.

In step (c), with reference to FIG. 2C, the metal base layer 301 formed on each of the upper surface 21, the lower surface 22 and the inner surface 201 is etched by a laser beam 6, so that each of the upper surface 21, the lower surface 22, and the inner surface 201 forms a patterned metal base layer 3 having a predetermined pattern for exposing a portion 211 thereof. It should be noted that the wavelength, output power, frequency and moving speed of the laser beam 6 are adjusted according to the thickness and the material of the metal base layer 301. In this step, the laser beam 6 has a wavelength in the range of 157 nm to 10.6 μm, and an output power in the range of 2 W to 200 W. It should be further noted that, as shown in FIG. 2C, when the laser beam 6 is etching the metal base layer 301 formed on the inner surface 201, the substrate 2 is inclined at an angle relative to a ground surface (not shown), so that a travel path of an optical axis of the laser beam 6 can directly enter the via hole 20 to partially remove/etch away the metal base layer 301 formed on the inner surface 201.

The etching action performed by the laser beam 6 in step (c) is performed using a six-axis laser engraving machine (not shown). More specifically, the six-axis laser engraving machine can be used to adjust an angle between the optical axis of the laser beam 6 and each inner surface 201, so that the optical axis of the laser beam 6 can directly point to each inner surface 201 to partially etch away the metal base layer 301 formed thereon. When an aspect ratio of each via hole 20 is high, the substrate 2 can also be inclined at an angle so that the optical axis of the laser beam 6 can directly enter each via hole 20 to partially remove/etch away the metal base layer 301 formed on each inner surface 201.

In step (d), with reference to FIG. 2D, the thickness of the patterned metal base layer 3 formed on each of the upper surface 21, the lower surface 22, and the inner surface 201 is increased to form a metal circuit layer 4. The means for increasing the thickness of the patterned metal base layer 3 suitable for this step may be selected from one of electroplating and chemical plating. In this embodiment, the means for increasing the thickness of the patterned metal base layer 3 is electroplating. It should be noted herein that the patterned metal base layer 3 obtained in step (c) is used as a seed layer when performing the electroplating of step (d). Specifically, in the whole process of electroplating, the thickness of the metal circuit layer 4 is increased according to the predetermined pattern of the patterned metal base layer (seed layer) 3. Therefore, the metal circuit layer 4 has a predetermined pattern that is identical to and that overlaps the predetermined pattern of the patterned metal base layer 3, and can also expose the portion 211 of each of the upper surface 21, the lower surface 22, and the inner surface 201.

In step (e), with reference to FIG. 2E, a metal protective layer 5 is formed on the metal circuit layer 4 electroplated on the patterned metal base layer 3 formed on each of the upper surface 21, the lower surface 22, and the inner surface 201. The metal protective layer 5 is a film layer structure selected from the group consisting of nickel (Ni), silver (Ag), nickel/palladium/gold (Ni/Pd/Au), titanium/palladium/gold (Ti/Pd/Au), titanium/platinum/gold (Ti/Pt/Au), titanium/nickel/gold (Ti/Ni/Au), gold/palladium/gold (Au/Pd/Au), and nickel/gold (Ni/Au), but not limited thereto. The forming means suitable for this step may be selected from one of electroplating and chemical plating. In this embodiment, the forming means is electroplating. The metal protective layer 5 has a predetermined pattern that is identical to and that overlaps the predetermined pattern of the metal circuit layer 4, and can also expose the portion 211 of each of the upper surface 21, the lower surface 22, and the inner surface 201.

Referring to FIGS. 5 and 6, it can be seen from the above detailed description that a conductive circuit board of this disclosure obtained by using the method of this embodiment includes the substrate 2, the patterned metal base layer 3, the metal circuit layer 4, and the metal protective layer 5.

Specifically, the substrate 2 has the opposite upper and lower surfaces 21, 22, and the via holes 20 extending through the upper and lower surfaces 21, 22 and respectively defined by the inner surfaces 201. The patterned metal base layer 3 is obtained by implementing the aforesaid steps (b) and (c), and is formed on each of the upper surface 21, the lower surface 22, and the inner surface 201. The patterned metal base layer 3 has a predetermined pattern that exposes the portion 211 of each of the upper surface 21, the lower surface 22, and the inner surface 201. The metal circuit layer 4 is formed on the patterned metal base layer 3, has a predetermined pattern that is identical to and that overlaps the predetermined pattern of the patterned metal base layer 3, and can also expose the portion 211 of each of the upper surface 21, the lower surface 22, and the inner surface 201. The metal protective layer 5 is formed on the metal circuit layer 4, has a predetermined pattern that is identical to and that overlaps the predetermined pattern of the metal circuit layer 4, and can also expose the portion 211 of each of the upper surface 21, the lower surface 22, and the inner surface 201.

From the above detailed description of the method and the conductive circuit board made therefrom, it can be seen that, not only the metal base layer 301 formed on each of the upper surface 21, the lower surface 22 and the inner surface 201 of the substrate 20 can be directly etched away through the laser beam 6 in step (c) to expose the portion 211 of each of the upper surface 21, the lower surface 22 and the inner surface 201, but also the six-axis laser engraving machine (not shown) can be used to adjust the angle between the optical axis of the laser beam 6 and each inner surface 201 of the substrate 2. Further, by tilting the substrate 2 at an angle, the optical axis of the laser beam 6 can directly point to each inner surface 201 to partially etch away the metal base layer 301 formed thereon. The manufacturing method of this embodiment does not need to perform the substep (C1) of attaching the dry film, the substep (C2) of exposing the dry film and the substep (C3) of developing the exposed dry film to obtain the patterned dry film 12 as described in the existing method for manufacturing a DPC substrate. There is also no need to perform the step (E) of stripping the patterned strip film 12 and the step (F) of etching away the portions 1111 of the metal base layer 111 at positions corresponding to where the patterned strip films 12 are stripped in the existing method. Compared with the existing method of manufacturing the DPC substrate, the manufacturing method of this disclosure can omit many steps of the existing manufacturing method. Moreover, the manufacturing method of this disclosure can also partially expose each inner surface 201 of the substrate 2 which can satisfy the requirements of the related industry who needs to design circuit patterns at the via holes 20 of the substrate 2.

Second Embodiment

Referring to FIG. 7A to FIG. 7D, a method for manufacturing the conductive circuit board according to a second embodiment is provided as follows.

In step (2a), with reference to FIG. 7A, similar to the steps (a) and (b) of the first embodiment, a substrate 2 is prepared. The substrate 2 has opposite upper and lower surfaces 21, 22, and at least one via hole 20 extending through the upper and lower surfaces 21, 22. The substrate 2 can have a plurality of via holes 20, but only one via hole 20 is shown in FIG. 7A to 7D to simplify the drawings. Each via hole 20 is defined by an inner surface 201, and is formed by laser drilling or blade dicing.

In step (2b), with reference to FIG. 7B, a compound metal layer 4C is formed on the substrate 2. In this embodiment, the compound metal layer 4C is fully covered on the substrate 2. In other words, the compound metal layer 4C is formed on each of the upper and lower surfaces 21, 22 of the substrate 2 and on each inner surface 201 that defines each via hole 20. The compound metal layer 4C is a film layer structure that can be titanium/platinum/gold (Ti/Pt/Au), but it is not limited thereto. For example, the compound metal layer 4C can be titanium/palladium/gold (Ti/Pd/Au), nickel/palladium/gold (Ni/Pd/Au), titanium/nickel/gold (Ti/Ni/Au), gold/palladium/gold (Au/Pd/Au), or nickel/gold (Ni/Au). The forming means suitable for this step may be Physical vapor deposition, PVD. For example, it can be selected from one of sputtering and evaporation. In this embodiment, the compound metal layer 4C includes titanium/platinum/gold (Ti/Pt/Au) film layers, that is a titanium (Ti) film layer 41, a platinum (Pt) film layer 42, and a gold (Au) film layer 43. The compound metal layer 4C in this embodiment is a surface treatment layer, and the total thickness of the compound metal layer 4C can be 1 μm.

In step (2c) of etching, with reference to FIG. 7C, a laser beam 6 is used to etch the compound metal layer 4C on at least one of the upper surface 21 and the lower surface 22 of the substrate 2 and on the inner surface 201, so as to form a patterned metal circuit layer 4P. In this embodiment, each of the upper surface 21, the lower surface 22, and the inner surface 201 forms the patterned metal circuit layer 4P having a predetermined pattern for exposing a portion 211 thereof. It should be noted that the wavelength, output power, frequency and moving speed of the laser beam 6 are adjusted according to the thickness and the material of the compound metal layer 4C.

In step (2d) of a surface finish process, with reference to FIG. 7D, a surface finish layer 44 is formed on a top surface of the patterned metal circuit layer 4P, so as to form a metal (or conductive) circuit layer 4 finally. The forming means suitable for this step may be electroplating. The surface finish layer 44 can be treated as a protective layer or a soldering portion that is used to protect and strengthen a solder connection and the patterned metal circuit layer 4P. In this embodiment, the material of the surface finish layer 44 can be AuSn, electroless nickel immersion gold (ENIG), or electroless plating Nickel palladium immersion gold (ENEPIG). ENIG is also known as nickel-gold, immersion nickel-gold or electroless nickel-gold plating, that includes a nickel layer, and the nickel is coated with a layer of gold. ENIG can play a role in the long-term use of the conductive circuit board and obtain good electrical properties. Different types of surface finish layer have different shelf lives.

A feature of this embodiment provides a method for manufacturing a conductive circuit board that can simplify the production process and meet the needs of the industry in circuit design. The manufacturing method of this embodiment can replace the conventional processes, such as dry film lamination, exposure, developing, etching and stripping.

Third Embodiment

Referring to FIG. 8A to FIG. 8B, a method for manufacturing the conductive circuit board according to a third embodiment is provided as follows.

The difference between this embodiment and the above-mentioned embodiments is that, the compound metal layer is formed on a thick metal base layer and the method according to the present disclosure can only be applied on the compound metal layer.

In step (3a), with reference to FIG. 8A, similar to the steps (a) and (b) of the first embodiment, a substrate 2 is prepared. The substrate 2 has opposite upper and lower surfaces 21, 22 The substrate can be a ceramic substrate.

A metal base layer 301 is further provided on the substrate 2, and specifically, between the substrate 2 and the compound metal layer 4C. The metal base layer 301 is formed on the upper and lower surfaces 21, 22 of the substrate 2. The metal base layer 301 may be formed by a physical vapor deposition (PVD) or chemical vapor deposition (CVD) method along with an electroplating method. The PVD method may be selected from one of sputtering and evaporation. In this step, the metal base layer 301 includes a titanium/copper (Ti/Cu) layer film formed by sputtering and a plated copper layer formed by electroplating.

Specifically, the substrate 2 is processed with a DPC (Direct Plated Copper) process, that is by magnetron sputtering technology to deposit a metal layer (Ti/Cu seed layer) on the surface of the ceramic substrate 2 along with an electroplating method which result in plated copper deposited on the Ti/Cu seed layer. The thickness of the metal base layer 301 could range between 10 μm to 130 μm. In this embodiment, the thickness of the metal base layer 301 ranges between 50 μm to 60 μm.

In step (3a), a compound metal layer 4C is formed on the metal base layer 301. In this embodiment, the compound metal layer 4C is covered on the metal base layer 301 and has a pattern corresponding with that of the metal base layer 301. The compound metal layer 4C is a film layer structure that can be titanium/platinum/gold (Ti/Pt/Au), titanium/palladium/gold (Ti/Pd/Au), nickel/palladium/gold (Ni/Pd/Au), titanium/nickel/gold (Ti/Ni/Au), gold/palladium/gold (Au/Pd/Au), and nickel/gold (Ni/Au), but not limited thereto. The forming means suitable for this step may be selected from one of electroplating and chemical plating. In this embodiment, the forming means is electroplating. In this embodiment, the compound metal layer 4C includes titanium/platinum/gold (Ti/Pt/Au) film layers, that is a titanium (Ti) film layer 41, a platinum (Pt) film layer 42, and a gold (Au) film layer 43. The compound metal layer 4C in this embodiment is a surface treatment layer, and the total thickness of the compound metal layer 4C can be 1 μm.

In this embodiment, the metal base layer 301 and the compound metal layer 4C are further formed with a predetermined pattern, which may be formed by a photomasking process.

In step (3b) of etching, with reference to FIG. 8B, a laser beam 6 is used to etch the compound metal layer 4C, but not etch the metal base layer 301, so as to form a patterned metal circuit layer 4P. It should be noted that the wavelength, output power, frequency and moving speed of the laser beam 6 are adjusted according to the thickness and the material of the compound metal layer 4C.

A feature of this embodiment is to reduce the CTE mismatch so as to improve the quality of the conductive circuit layer. In a practical situation, the CTE mismatch between the compound metal layer 4C and the metal base layer 301 is lower than the CTE mismatch between the compound metal layer 4C and the substrate 2. The CTE mismatch may result in a crack problem at edges or corners of the conductive circuit layer. In this embodiment, the metal base layer 301 is arranged between the substrate 2 and the compound metal layer 4C, so that the CTE mismatch between the substrate 2 and the conductive circuit layer can be reduced.

In summary, the method of manufacturing the conductive circuit board not only has simple manufacturing steps, but also can meet the requirements of the downstream industry in circuit design. Therefore, the object of this disclosure can indeed be achieved.

While the disclosure has been described in connection with what is considered the exemplary embodiment, it is understood that this disclosure is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.

Claims

1. A method for manufacturing a conductive circuit board, comprising the steps of: preparing a substrate, the substrate having an upper surface and a lower surface opposite to each other, and at least one via hole extending through the upper surface and the lower surface and defined by an inner surface;forming a compound metal layer on at least one of the upper surface and the lower surface of the substrate and on the inner surface of the substrate;etching the compound metal layer by a laser beam, so that the at least one of the upper surface and the lower surface of the substrate and the inner surface are formed with a patterned metal circuit layer having a predetermined pattern for exposing a portion of the at least one of the upper surface and the lower surface of the substrate and a portion of the inner surface; andforming a surface finish layer on a top surface of the patterned metal circuit layer, so as to form a conductive circuit layer.

2. The method as claimed in claim 1, wherein the substrate is made of an insulating material selected from the group consisting of ceramics and polymers.

3. The method as claimed in claim 1, wherein, in the step of preparing the substrate, the at least one via hole is formed by laser drilling or blade dicing.

4. The method as claimed in claim 1, wherein the compound metal layer is fully covered on the substrate, and a thickness of the compound metal layer is 1 μm.

5. The method as claimed in claim 1, wherein the compound metal layer is a film layer structure selected from the group consisting of titanium/platinum/gold, titanium/palladium/gold, nickel/palladium/gold, titanium/nickel/gold, gold/palladium/gold, and nickel/gold.

6. The method as claimed in claim 1, wherein a material of the surface finish layer is selected from the group consisting of AuSn, electroless nickel immersion gold, and electroless plating Nickel palladium immersion gold.

7. The method as claimed in claim 1, further comprising a step of forming a metal base layer between the substrate and the compound metal layer, wherein the metal base layer is formed on at least one of the upper surface and the lower surface of the substrate and on the inner surface of the substrate.

8. The method as claimed in claim 7, wherein the metal base layer is a copper layer film formed by sputtering.

9. The method as claimed in claim 8, wherein the metal base layer is formed by the physical vapor deposition method, and the physical vapor deposition method is selected from one of sputtering and evaporation.

10. The method as claimed in claim 7, wherein a thickness of the metal base layer ranges between 50 μm to 60 μm.

11. The method as claimed in claim 7, wherein the metal base layer is formed by a physical vapor deposition or chemical vapor deposition method.

12. A conductive circuit board, comprising: a substrate having an upper surface and a lower surface opposite to each other, and at least one via hole extending through the upper surface and the lower surface and defined by an inner surface;a compound metal layer formed the substrate;a metal circuit layer formed on at least one of the upper surface and the lower surface of the substrate and on the inner surface, the metal circuit layer having a predetermined pattern for exposing a portion of the at least one of the upper surface and the lower surface of the substrate and a portion of the inner surface; anda surface finish layer formed on a top surface of the patterned metal circuit layer, so as to form a conductive circuit layer.

13. The conductive circuit board as claimed in claim 12, further comprising a metal base layer formed between the compound metal layer and the substrate, wherein the metal base layer is formed on at least one of the upper surface and the lower surface of the substrate and on the inner surface of the substrate.

14. The conductive circuit board as claimed in claim 13, wherein a thickness of the metal base layer ranges between 50 μm to 60 μm.

15. The conductive circuit board as claimed in claim 12, wherein the compound metal layer is a film layer structure selected from the group consisting of titanium/platinum/gold, titanium/palladium/gold, nickel/palladium/gold, titanium/nickel/gold, gold/palladium/gold, and nickel/gold.

16. The conductive circuit board as claimed in claim 12, wherein the compound metal layer is formed on the metal base layer, and a thickness of the compound metal layer is 1 μm.

17. The conductive circuit board as claimed in claim 12, wherein the substrate is made of an insulating material selected from the group consisting of ceramics and polymers.

18. The conductive circuit board as claimed in claim 12, wherein the compound metal layer is fully covered on the metal base layer.

19. The conductive circuit board as claimed in claim 12, wherein the surface finish layer is selected from the group consisting of AuSn, electroless nickel immersion gold, and electroless plating Nickel palladium immersion gold.