Claims
- 1. A method for manufacturing a contact structure, comprising the steps of:
- forming a first insulating layer on a semiconductor substrate;
- forming a first conductive layer on said first insulating layer;
- forming a silicon nitride layer on said first conductive layer;
- forming a first pattern layer on said silicon nitride layer;
- anisotropically etching said silicon nitride layer and said first conductive layer with a mask of said first pattern layer;
- removing said first pattern layer;
- isotropically etching said first conductive layer with a mask of said silicon nitride layer and said first insulating layer;
- forming a second insulating layer on the entire surface after said first conductive layer is isotropically etched;
- forming a second pattern layer on said second insulating layer;
- perforating a contact hole in said second insulating layer and said first insulating layer;
- removing said second pattern layer; and
- burying a second conductive layer in said contact hole.
- 2. A method as set forth in claim 1, wherein said first conductive layer is made of refractory metal.
- 3. A method as set forth in claim 1, wherein said first conductive layer is made of refractory metal silicide.
- 4. A method as set forth in claim 1, wherein said first conductive layer is made of refractory metal nitride.
- 5. A method as set forth in claim 1, wherein said second insulating layer is made of a triple structure of non-doped silicon, boron-including phospho-silicated glass and non-doped silicon.
- 6. A method as set forth in claim 5, further comprising a step of reflowing said second insulating layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
6-280399 |
Nov 1994 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 08/558, 090, filed Nov. 13, 1995, U.S. Pat. No. 5,654,236.
US Referenced Citations (13)
Foreign Referenced Citations (4)
Number |
Date |
Country |
58-180 |
Jan 1983 |
JPX |
2-111031 |
Apr 1990 |
JPX |
3-106027 |
May 1991 |
JPX |
4-359521 |
Dec 1992 |
JPX |
Non-Patent Literature Citations (2)
Entry |
M. Fukumoto et al., "Double Self-Aligned Contact Technology for Shielded Bit Line Type Stacked Capacitor Cell of 16 MDRAM", IEICE Transactions, vol. E 74, No. 4, pp. 818-826, Apr. 1991. |
T. Fukase et al., "A Margin-Free Contact Process Using an A1.sub.2 O.sub.3 Etch-Stop Layer for High Density Devices", IEDM Tech. Dig., pp. 837-840, 1992. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
558090 |
Nov 1995 |
|