Patent Application
20230187279
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-200229, filed Dec. 9, 2021, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a method for manufacturing a semiconductor device and the semiconductor device.
In the manufacturing process of a semiconductor device, a wafer on which a semiconductor element is formed may be fragmented into a semiconductor chip by dicing. However, dicing defects such as film peeling may occur during dicing.
Poor dicing may adversely affect the semiconductor element and may lead to a decrease in yield.
Embodiments provide a method for manufacturing a semiconductor device capable of more appropriately performing fragmentation and the semiconductor device.
In general, according to at least one embodiment, a method for manufacturing a semiconductor device includes forming a first stacked body having a plurality of first material films and a plurality of second material films that are alternately stacked, in a divided region of a semiconductor wafer including a chip region in which a semiconductor element is provided and the divided region between the adjacent chip regions, a plurality of times in a normal line direction of a substrate surface of the semiconductor wafer. The semiconductor wafer is fragmented by a blade having a width wider than the width of the first stacked body.
Hereinafter, embodiments according to the present disclosure will be described with reference to drawings. The present embodiment is not limited to the present disclosure. In the following embodiments, the vertical direction of a semiconductor substrate indicates a relative direction when the surface on which a semiconductor element is provided is facing up, and may be different from the vertical direction according to the gravitational acceleration. The drawings are schematic or conceptual, and the ratio of each part is not always the same as an actual one. In the specification and the drawings, the same elements as those described above with respect to the existing drawings are designated by the same reference numerals, and a detailed description thereof will be omitted as appropriate.
The substrate 10 is a semiconductor substrate such as a silicon substrate. The substrate 10 indicates a substrate before the semiconductor manufacturing process, and the semiconductor wafer W indicates a substrate after the semiconductor manufacturing process. Therefore, the semiconductor wafer W indicates the substrate 10 including semiconductor elements, an interlayer insulating film, and the like.
The control circuit 11 is provided on the substrate 10 as a part of the semiconductor elements. The control circuit 11 is provided under the stacked body ST_chip and controls the stacked body ST_chip (that is, the memory cell array MCA). The control circuit 11 includes, for example, a complementary metal oxide semiconductor (CMOS) circuit.
The stacked body ST_chip is provided on the chip region Rchip of the substrate 10. The stacked body ST_chip is configured by alternately stacking conductive films 21 and a first insulating film 22, and includes a columnar portion CL therein. A memory cell MC is configured at the intersection of the stacked body ST_chip and the columnar portion CL. The detailed configuration of the columnar portion CL and the memory cell MC will be described later with reference to
The stacked body ST_chip includes a plurality of stages of second stacked bodies ST_chip_1 in a Z direction. The second stacked body ST_chip_1 is a one-stage stacked body provided in the stacked body ST_chip. In the example shown in
A conductive metal such as tungsten is used for the conductive film 21, and an insulating material such as a silicon oxide film is used for the first insulating film 22 as a first material film. Each of the conductive films 21 functions as a word line. The first insulating film 22 is provided between the conductive films 21 adjacent to the stacked body ST_chip in the stacking direction (Z direction), and electrically separates the conductive films 21.
The stacked body ST_d is provided on the dicing region Rd of the substrate 10. The stacked body ST_d is configured by alternately stacking the first insulating film 22 and a second insulating film 23, and is not provided with the columnar portion CL. The stacked body ST_d may be used, for example, as a test pattern TEG. For the second insulating film 23 as a second material film, a material different from that of the first insulating film 22, for example, an insulating material such as a silicon nitride film is used.
The stacked body ST_d includes a plurality of stages of first stacked bodies ST_d_1 in the Z direction. The first stacked body ST_d_1 is a one-stage stacked body provided in the stacked body ST_d. In the example shown in
The interlayer insulating film 20 is provided between the stacked body ST_chip and the stacked body ST_d, and covers the periphery of the stacked body ST_d. For the interlayer insulating film 20, for example, an insulating material such as a TetraEthOxySilane (TEOS) film is used.
The passivation film 30 is provided on the stacked body ST_chip in the chip region Rchip. For the passivation film 30, for example, an insulating material such as polyimide is used.
The guard ring 40 is provided between the chip region Rchip and the dicing region Rd, and extends in the Z direction from the uppermost layer to the lowest layer of the stacked bodies ST_chip and ST_d. The guard ring 40 protects the semiconductor elements on the chip region Rchip side so that cracks generated when the dicing region Rd is cut do not propagate to the chip region Rchip. Therefore, the guard ring 40 is provided over the entire dicing region Rd so as to surround the entire periphery of the chip region Rchip. For the guard ring 40, for example, a single layer of a metal material such as tungsten, copper, aluminum, titanium, and tantalum, or a stacked layer of a plurality of these materials is used.
The metal film 50 is provided on the stacked body ST_d of the dicing region Rd and the interlayer insulating film 20. The metal film 50 functions as an alignment mark at the time of device formation and a pad in the chip region Rchip. For the metal film 50, for example, a metal material such as aluminum is used.
The stacked body ST_d of the dicing region Rd is formed separately from the lower stacked body ST_b and the upper stacked body ST_t. In the cross section perpendicular to the stretching direction of the dicing region Rd, both the lower stacked body ST_b and the upper stacked body ST_t have a taper on the side surface. The widths of the side surfaces of the lower stacked body ST_b and the upper stacked body ST_t become narrower in the upward direction (from the lower layer to the upper layer) in the stacking direction, respectively. The “width” here is a width in a direction (X or Y direction) substantially perpendicular to the stacking direction of the stacked body ST_d.
The stacked body ST_chip of the chip region Rchip is different from the stacked body ST_d in the planar layout, but is the same in that the stacked body ST_chip is formed separately from the lower stacked body and the upper stacked body. The side surfaces of the lower stacked body and the upper stacked body of the stacked body ST_chip have the same taper as the lower stacked body ST_b and the upper stacked body ST_t of the stacked body ST_d, respectively. As described above, the stacked body ST_d differs in the planar pattern, but has the same stacked structure as the stacked body ST_chip. This is because the stacked bodies ST_d and ST_chip are formed at the same time. By forming the stacked bodies ST_d and ST_chip at the same time, the manufacturing process can be shortened.
The stacked bodies ST_chip and ST_d are initially formed as a stacked body of the first insulating film 22 (for example, a silicon oxide film) and the second insulating film 23 (for example, a silicon nitride film) in the manufacturing process. That is, the stacked bodies ST_chip and ST_d are initially composed of the same material. However, thereafter, the second insulating film 23 of the stacked body ST_chip is replaced with the conductive film 21 (for example, tungsten) that functions as a word line WL. Therefore, as the finished semiconductor wafer W, the stacked body ST_chip and the stacked body ST_d may be made of different materials. It is noted that the second insulating film 23 of the stacked body ST_d may be replaced with the conductive film 21 (for example, tungsten) in the same manner as the second insulating film 23 of the stacked body ST_chip. That is, the second material film is a tungsten film (conductive film 21). In this case, the stacked body ST_chip and the stacked body ST_d differ in the planar layout, but have the same configuration in the stacked structure and material in the Z direction.
The semiconductor chip C has a first surface F1, a second surface F2 on the opposite side of the first surface F1, and a side surface F3 between the first surface F1 and the second surface F2.
Since the semiconductor chip C is cut at the dicing region Rd, the dicing region Rd as a divided region is located on an outer edge E (outer periphery) of the first surface F1. At the outer edge E, the side surface F3 has a cut surface in a dicing process. Further, the substrate 10, the interlayer insulating film 20, and the metal film 50 are exposed on the side surface F3. However, the stacked body ST_d is not exposed on the side surface F3. As will be described later, the stacked body ST_d exposed on the cut surface during blade dicing may easily become a starting point of dicing defects such as film peeling and cracks. By preventing the stacked body ST_d from being exposed on the side surface F3, poor dicing can be reduced, and fragmentation can be performed more appropriately.
Other configurations of the semiconductor chip C may be the same as the corresponding configurations of the semiconductor wafer W.
Next, the configuration of the columnar portion CL in the stacked body ST_chip will be described.
As shown in
The shape of the semiconductor body 210 is, for example, a cylindrical shape having a bottom. The semiconductor body 210 contains, for example, silicon. Silicon is, for example, polysilicon obtained by crystallizing amorphous silicon. The semiconductor body 210 is, for example, undoped polysilicon. The semiconductor body 210 may be p-type silicon. The semiconductor body 210 serves as a channel for each of a drain-side select transistor, a source side select transistor, and the memory cell MC.
The memory film 220 is provided with a portion other than the block insulating film 21a between the inner wall of the memory pillar MH and the semiconductor body 210. The shape of the memory film 220 is, for example, a cylindrical shape. A plurality of memory cells MC have a storage region between the semiconductor body 210 and the conductive film 21 serving as the word line WL, and are stacked in the Z-axis direction. The memory film 220 includes, for example, a cover insulating film 221, a charge trapping film 222, and a tunnel insulating film 223. Each of the semiconductor body 210, the charge trapping film 222, and the tunnel insulating film 223 extends in the Z-axis direction.
The cover insulating film 221 is provided between the insulating film 22 and the charge trapping film 222. The cover insulating film 221 contains, for example, a silicon oxide. The cover insulating film 221 protects the charge trapping film 222 from being etched when a sacrifice film (not shown) is replaced with the conductive film 21 (replacement process). The cover insulating film 221 may be removed from between the conductive film 21 and the memory film 220 in the replacement process. In this case, as shown in
The charge trapping film 222 is provided between the block insulating film 21a and the cover insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 contains, for example, a silicon nitride and has a trap site that traps charges in the film. The portion of the charge trapping film 222 sandwiched between the conductive film 21 serving as the word line WL and the semiconductor body 210 includes a storage region of the memory cell MC as a charge trapping portion. The threshold voltage of the memory cell MC changes depending on the presence or absence of charges in the charge trapping portion or the amount of charges trapped in the charge trapping portion. As a result, the memory cell MC can store the information.
The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 includes, for example, a silicon oxide, or a silicon oxide and a silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when an electron is injected from the semiconductor body 210 into the charge trapping portion (write operation) and when a hole is injected from the semiconductor body 210 into the charge trapping portion (erasing operation), the electron and the hole each pass through (tunneling) the potential barrier of the tunnel insulating film 223.
The core layer 230 embeds the internal space of the cylindrical semiconductor body 210. The shape of the core layer 230 is, for example, a columnar shape. The core layer 230 contains, for example, a silicon oxide and is insulating.
The memory cell array MCA includes the semiconductor substrate 10, the conductive film 21, the interlayer insulating film (first insulating film) 22, and the memory pillar MH. The main surface of the semiconductor substrate 10 corresponds to the XY plane. A plurality of conductive films 21 are stacked on the semiconductor substrate 10 via the interlayer insulating film 22. The conductive film 21 is formed in a flat plate shape along the XY plane and functions as a source line SL. The control circuit 11 shown in
A plurality of slit SLTs along a YZ plane are located in the X direction on the conductive film 21. The structure on the conductive film 21 and between the adjacent slits SLT corresponds to, for example, one string unit SU. Specifically, the conductive film 21 and the interlayer insulating film 22 are alternately provided on the conductive film 21 and between the adjacent slit SLTs in order from the lower layer. In these conductive films 21, the conductive films adjacent to each other in the Z direction are stacked via the interlayer insulating film 22. The conductive film 21 and the interlayer insulating film 22 are each formed in a flat plate shape along the XY plane.
The lowermost layer conductive film 21 functions as a select gate line SGS. The 48 conductive films 21 on the select gate line SGS function as word lines WL0 to WL47, respectively, in order from the lower layer. The uppermost conductive film 21 of the lower stacked body ST_chip_b and the lowermost conductive film 21 of the upper stacked body ST_chip_t function as dummy word lines WLDL and WLDU, respectively. The 48 conductive films 21 on the dummy word line WLDU function as word lines WL48 to WL95 in order from the lower layer. The uppermost conductive film 21 of the upper stacked body ST_chip_t functions as a select gate line SGD.
That is, the lower stacked body ST_chip_b includes a plurality of first insulating films 22 and the plurality of conductive films 21 that are alternately stacked. The upper stacked body ST_chip_t is provided on the lower stacked body ST_chip_b and includes the plurality of first insulating films 22 and the plurality of conductive films 21 which are alternately stacked.
A plurality of memory pillars MH are located in a staggered pattern in the Y direction (not shown), and each functions as one NAND string NS. Each memory pillar MH is provided through the conductive film 21 and the interlayer insulating film 22 so as to reach the upper surface of the conductive film 21 from the upper surface of the select gate wire SGD. Each memory pillar MH also includes a lower pillar LMH, an upper pillar UMH, and a joint portion JT between the lower pillar LMH and the upper pillar UMH.
The upper pillar UMH is provided on the lower pillar LMH, and the lower pillar LMH and the upper pillar UMH are joined via the joint portion JT. That is, the lower pillar LMH is provided on the conductive film 31, and the upper pillar UMH is provided on the lower pillar LMH via the joint portion JT. For example, the outer diameter of the joint portion JT has a taper from the upper end of the lower pillar LMH to the lower end of the upper pillar UMH.
That is, the lower pillar LMH penetrates the lower stacked body ST_chip_b in the Z direction. The upper pillar UMH is provided on the lower pillar LMH and penetrates the upper stacked body ST chip t in the Z direction.
The memory pillar MH includes, for example, the block insulating film 40, a charge storage film (also referred to as a charge storage layer) 41, a tunnel insulating film 42, and a semiconductor layer 43. Specifically, the block insulating film 40 is provided on the inner wall of the memory hole for forming the memory pillar MH. The charge storage film 41 is provided on the inner wall of the block insulating film 40. The tunnel insulating film 42 is provided on the inner wall of the charge storage film 41. Further, the semiconductor layer 43 is provided in the tunnel insulating film 42. The memory pillar MH may have a structure in which a core insulating film is provided in the semiconductor layer 43.
In such a configuration of the memory pillar MH, the portion where the memory pillar MH and the select gate line SGS intersect functions as a select gate transistor ST2. The portions where the memory pillar MH and the word lines WL0 to WL47 intersect function as memory cell transistors MT0 to MT47, respectively. Each memory cell transistor MT0 to MT47 is a memory cell in which data is stored or can be stored. The portions where the memory pillar MH and the dummy word lines WLDL and WLDU intersect function as dummy transistors DLT and DUT, respectively. Each of the dummy transistors DLT and DUT is a memory cell in which data is not stored. The portions where the memory pillar MH and the word lines WL48 to WL95 intersect function as memory cell transistors MT48 to MT95, respectively. Each of the memory cell transistors MT48 to MT95 is a memory cell in which data is stored or can be stored. Further, the portion where the memory pillar MH and the select gate line SGD intersect functions as a select gate transistor ST1.
The semiconductor layer 43 functions as a channel layer of the memory cell transistor MT, the dummy transistors DLT and DUT, and the select gate transistors ST1 and ST2. A current path of the NAND string NS is formed in the semiconductor layer 43.
The charge storage film 41 has a function of storing the charges injected from the semiconductor layer 43 in the memory cell transistor MT. The charge storage film 41 includes, for example, a silicon nitride film.
The tunnel insulating film 42 functions as a potential barrier when charges are injected from the semiconductor layer 43 into the charge storage film 41 or when the charges stored in the charge storage film 41 diffuse into the semiconductor layer 43. The tunnel insulating film 42 includes, for example, a silicon oxide film.
The block insulating film 40 prevents the charges stored in the charge storage film 41 from diffusing into the word lines WL0 to WL95. The block insulating film 40 includes, for example, a silicon oxide film and a silicon nitride film.
The configuration of the memory cell array MCA is not limited to the above configuration. For example, the numbers of the memory cell transistors MT, the dummy transistors DLT and DUT, and the select gate transistors ST1 and ST2 provided in each NAND string NS may be any numbers, respectively.
The numbers of the word lines WL, the dummy word lines WLDL and WLDU, and the select gate lines SGD and SGS are changed according to the numbers of the memory cell transistors MT, the dummy transistors DLT and DUT, and the select gate transistors ST1 and ST2, respectively. The select gate line SGS may be composed of a plurality of conductive films provided on each of a plurality of layers. The select gate line SGD may be composed of a plurality of conductive films provided on each of the plurality of layers.
Other configurations of the memory cell array MCA are described in, for example, “Three-dimensional Stacked Nonvolatile Semiconductor Memory”, U.S. Pat. Application No. 12/407, 403 filed on Mar. 19, 2009. The configurations are described in “Three-dimensional stacked nonvolatile semiconductor memory”, U.S. Pat. Application No. 12/406, 524 filed on Mar. 18, 2009, “Nonvolatile Semiconductor Storage Device and Method for Manufacturing the Same”, U.S. Pat. Application No. 12/679, 991 filed on Mar. 25, 2010, and “Semiconductor Memory and Method for Manufacturing the Same”, U.S. Pat. Application No. 12/532, 030 filed on Mar. 23, 2009, respectively. These patent applications are incorporated herein by reference in the entirety thereof.
Next, a method for manufacturing a semiconductor wafer according to the present embodiment will be described.
Next, the first insulating film 22 and the second insulating film 23 are alternately stacked above the control circuit 11. For example, a silicon oxide is used for the first insulating film 22. For example, a silicon nitride is used for the second insulating film 23. As a result, as shown in
Next, a memory hole is formed in order to form the columnar portion CL in the stacked body ST_chip by using the lithography technique and the etching technique. At the time of forming the memory hole or thereafter, by using the lithography technique and the etching technique, the first insulating film 22 and the second insulating film 23 between the stacked body ST_d and the stacked body ST_chip are removed to separate the stacked body ST_d and the stacked body ST_chip. As a result, the structure shown in
That is, in the process shown in
Next, the interlayer insulating film 20 is deposited on the stacked body ST_d and the stacked body ST_chip. For the interlayer insulating film 20, for example, an insulating film such as a TEOS film is used. Next, the interlayer insulating film 20 is flattened until the upper surfaces of the stacked body ST_d and the stacked body ST_chip are exposed. The interlayer insulating film 20 is left in the groove between the stacked body ST_d and the stacked body ST_chip. As a result, the structure shown in
Next, the first insulating film 22 and the second insulating film 23 are alternately stacked on the lower portion of the stacked body ST_chip and the stacked body ST_d. As a result, as shown in
Next, a memory hole is formed in order to form the columnar portion CL on the upper portion of the stacked body ST chip by using the lithography technique and the etching technique. Further, the upper portion of the columnar portion CL is formed in the memory hole.
At the time of forming the memory hole or thereafter, by using the lithography technique and the etching technique, the first insulating film 22 and the second insulating film 23 between the upper portion of the stacked body ST_d and the upper portion of the stacked body ST_chip are removed to separate the stacked body ST_d and the stacked body ST_chip. As a result, the structure shown in
That is, in the process shown in
In the process shown in
Next, the interlayer insulating film 20 is deposited on the stacked body ST_d and the stacked body ST_chip. Next, the interlayer insulating film 20 is flattened until the upper surfaces of the stacked body ST_d and the stacked body ST_chip are exposed. The interlayer insulating film 20 is left in the groove between the stacked body ST_d and the stacked body ST_chip. As a result, the structure shown in
That is, in the process shown in
Next, a slit (not shown) is formed, and as shown in
That is, in the process shown in
Next, by using the lithography technique and the etching technique, the metal film 50 is processed to remove the metal film 50 in the chip region Rchip, and the metal film 50 is left in the dicing region Rd. At this time, the conductive film 21 of the stacked body ST_chip is also left.
Next, as shown in
Next, the passivation film 30 in the dicing region Rd is removed. As a result, the semiconductor wafer W shown in
As shown in
The width of each of the upper pillar UMH and the lower pillar LMH decreases from the upper side of the paper surface to the lower side of the paper surface in
As the second material film of the stacked bodies ST_chip and ST_d, a phosphorus (P)-doped polysilicon film may be formed instead of the second insulating film 23. In this case, the replacement of the second insulating film 23 with the conductive film 21 does not have to be performed.
In the process shown in
Next, the dicing process will be described. More specifically, the details of blade dicing will be described.
As shown in
In the blade dicing shown in
Therefore, the semiconductor wafer W is fragmented by the blade BLD having a width Wb wider than a width Wd of the first stacked body ST_d_1 (stacked body ST_d). By preventing the stacked body ST_d from appearing on the cut surface, dicing defects such as film peeling and cracks can be reduced, and the semiconductor wafer W can be more appropriately fragmented. The width Wb of the blade BLD is, for example, about 60 µm or more. The width Wd of the stacked body ST_d is, for example, about 30 µm or more.
More specifically, the semiconductor wafer W is fragmented by the blade BLD having the width Wb wider than the width Wd of the lower stacked body ST_b and the upper stacked body ST_t.
More specifically, the semiconductor wafer W is fragmented by the blade BLD passing through the dicing region Rd so that the width Wb of the blade BLD covers the width Wd of the first stacked body ST_d_1 (stacked body ST_d). As a result, the entire stacked body ST_d is cut off from the semiconductor wafer W by passing the blade BLD once. As a result, the semiconductor wafer W is fragmented so that the stacked body ST_d does not remain.
It is more preferable to fragment the semiconductor wafer W by the blade BLD having the width Wb wider than the width Wd of the stacked body ST_d so that the area where side surfaces BLDs of the blade BLD are in contact with the interlayer insulating film 20 is large. That is, the dicing position is adjusted so that the area of the interlayer insulating film 20 exposed on the cut surface becomes large and the stacked body ST_d does not appear on the cut surface. This is because the stacked body ST_d in contact with the side surfaces BLDs of the blade BLD may easily become a starting point of dicing defects such as film peeling and cracks.
Next, the details of the configuration of the end portion of the semiconductor chip C will be described. Although
The semiconductor element which is the stacked body ST chip includes the plurality of stages of second stacked bodies ST_chip_1 having the plurality of first insulating films 22 and the plurality of conductive films 21 which are alternately stacked in the normal line direction. The semiconductor element is provided on the semiconductor substrate 10. As shown in
As shown in
The stacked body ST_d hardly appears on the side surface F3 which is a cut surface. Almost only the interlayer insulating film 20 is exposed on the side surface F3 between the semiconductor substrate 10 and the metal film 50. That is, the stacked body having the plurality of first insulating films 22 and the plurality of second material films which are alternately stacked is not exposed on the side surface F3. The second material film is, for example, a silicon nitride film, a tungsten (W) film, or a phosphorus (P)-doped polysilicon film.
Even when the blade BLD having a large width Wb is used, it is necessary not to cut the semiconductor element. Therefore, the dicing position is set so that the interlayer insulating film 20 remains between the side surface F3 and the semiconductor element (guard ring 40). The interlayer insulating film 20 is provided with a width of a second predetermined value or more from the side surface F3 along the outer edge E toward the stacked body ST chip which is a semiconductor element. The second predetermined value is, for example, about 3 µm. In the example shown in
The side surface F3 has a predetermined surface roughness. Due to blade dicing, the entire surface of the side surface F3, which is the cut surface, is roughened. Therefore, the side surface F3 according to the first embodiment is different from the cut surface by laser dicing such as laser ablation or stealth dicing (registered trademark), for example. The surface roughness of the side surface F3 is determined by the count (side surface roughness) of the blade BLD. The count of the blade BLD is, for example, #5000 or less.
As described above, in the first embodiment, the semiconductor wafer W is fragmented by the blade BLD having the width Wb wider than the width of the stacked body ST_d. As a result, the semiconductor wafer W can be fragmented so that the stacked body ST_d is not exposed on the side surface F3 along the outer edge E. As a result, dicing defects such as film peeling and cracks can be reduced, and fragmentation can be performed more appropriately.
Next, as a modification example, a case where blade dicing is performed by using a thin blade BLD will be described.
In the example shown in
In the example shown in
On the other hand, in the first embodiment, the entire stacked body ST_d is cut out at once by the blade BLD. As a result, film peeling and cracks starting from the stacked body ST_d can be reduced. As a result, fragmentation can be performed more appropriately.
As the numbers of stacked layers ST_chip and ST_d increase, the number of places where film peeling and cracks occur may increase. Normally, it is preferable that the number of stacked layers is large in order to increase the density and capacity of the memory. However, as the number of layers increases, the aspect ratio of the memory hole increases as described above, and the number of damage starting points increases, which may lead to dicing defects such as film peeling. In order to reduce the aspect ratio of the memory hole, the stacked bodies ST_chip and ST_d may be formed a plurality of times as described above. Even when the number of stages of the second stacked body ST_cip_1 is large, if the total number of stacked bodies is the same, the susceptibility to dicing defects such as film peeling is almost the same. Therefore, as the number of stages of the stacked body is larger, it is more preferable to use a thick blade BLD as in the first embodiment.
When the stacked bodies ST_chip and ST_d are formed a plurality of times, the columnar portion CL is formed a plurality of times. The columnar portion CL (memory pillar MH) may have the shape of the joint portion JT and the surroundings thereof, as shown in
In the first embodiment, the stacked body ST_chip includes the two-stage second stacked body ST_chip_1 in the Z direction, and the stacked body ST_d includes the two-stage first stacked body ST_d_1 in the Z direction. However, the stacked body ST_chip may have a three or more stages of a second stacked body ST_chip_1 in the Z direction, and the stacked body ST_d may have a three or more stages of first stacked bodies ST_d_1 in the Z direction. In this case, the upper stacked body and the lower stacked body indicate a continuous two-stage stacked body among the three or more stages of stacked bodies.
The stacked body ST_d is stacked in the same manner as the stacked body ST_chip of the chip region Rchip. That is, in the dicing region Rd, the interlayer insulating film (first insulating film) 22 and the second insulating film 23 are alternately provided above the substrate 10. In the chip region Rchip, since the second insulating film 23 is replaced with the conductive film 21, the second insulating film 23 is not provided, but in the dicing region Rd, the second insulating film 23 is left on the same layer as the conductive film 21.
The gap GP corresponding to the joint portion JT of the chip region Rchip is provided between the lower stacked body ST_b and the upper stacked body ST_t. The width (thickness) of the gap GP in the Z direction is larger (thick) than the distance (thickness of the interlayer insulating film 22) between the second insulating films 23 in the lower stacked body ST_b and the upper stacked body ST_t. The gap GP is provided with the same material as the interlayer insulating film 22.
The side surface of the stacked body ST_d has a taper similar to the taper of the end side surface of the stacked body ST_chip. This is because the stacked bodies ST_d and ST chip are stacked in the same stacking process and processed in the same etching process.
In the first embodiment described with reference to
The outer diameter of the joint portion JT is, for example, larger than the outer diameter of the contact portion between the lower pillar LMH and the joint portion JT, and larger than the outer diameter of the contact portion between the upper pillar UMH and the joint portion JT. The distance in the Z direction (distance between the dummy word lines WLDL and WLDU) of the junction layer provided with the joint portion JT is wider than the distance between adjacent word lines among the word lines WL0 to WL47 and WL48 to WL95.
As in the second embodiment, the gap GP may be provided between the lower stacked body ST_b and the upper stacked body ST_t.
The width (thickness) of the gap GP in the Z direction may be smaller (thinner) than the spacing between the second insulating films 23. Normally, the distance between the conductive films 21 in the second stacked body ST_chip_1 having one stage is almost the same. On the other hand, the distance between the uppermost conductive film 21 in the lower stacked body ST_chip_b and the lowermost conductive film 21 in the upper stacked body ST_chip_t may be larger or smaller than the distance between the conductive films 21 in a one-stage stacked body.
The semiconductor device 100 (semiconductor chip C) according to the second embodiment can obtain the same effect as that of the first embodiment.
The stacked body ST_d is disposed above the interlayer insulating film 20 of the same layer as wiring layers GC and D0 to D2 in which the control circuit 11 is disposed. The control circuit 11 includes a CMOS circuit composed of a transistor Tr.
The transistor Tr is electrically connected to the wiring of the wiring layer D0 and the wiring of the wiring layers D1 and D2 (not shown). Power is supplied to the transistor Tr via the wiring of the wiring layers D0 to D2. The gate electrode of the transistor Tr is provided as a wiring layer GC. A wiring layer DP is provided in the upward direction of the wiring layer D2. The wiring layer DP is a conductive layer containing polysilicon, and may be used as a source layer of a memory transistor.
The guard ring 40 includes, for example, wirings of wiring layers M0 to M2 and D0 to D2, and contacts C1 to C3, Cs, vias V0 to V2, and the like.
As in the third embodiment, the interlayer insulating film 20 may be disposed between the stacked body ST_d and the semiconductor substrate 10.
The semiconductor device 100 (semiconductor chip C) according to the third embodiment can obtain the same effect as that of the first embodiment.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-200229 | Dec 2021 | JP | national |
