Patent Application
20220189785
The present application is based on and claims priority to Japanese Priority Application No. 2020-208800 filed on Dec. 16, 2020, the entire contents of which are hereby incorporated herein by reference.
The present disclosure relates to a method for manufacturing a semiconductor device and a substrate processing device.
Japanese Laid-Open Patent Application Publication No. 2017-228580 discloses a method for manufacturing a semiconductor device for filling a recess with a silicon film by repeating a cycle of supplying a film deposition gas containing silicon to a workpiece including the recess formed in a surface to form a silicon film in the recess, supplying a process gas including a halogen gas for etching a silicon film and a roughness inhibiting gas for inhibiting the roughness of the surface of the silicon film after etching by the halogen gas, supplying thermal energy to the process gas to activate the process gas, and expanding the opening width of the recess. Such a filling method is referred to as a DED (Deposition Etch Deposition) process because the method repeats deposition and etching.
In an embodiment, the present disclosure provides a method for manufacturing a semiconductor device and a substrate processing apparatus in which a recess is filled with a silicon film without generating a void by bottom-up film deposition without repeating a DED process.
According to one embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device. In the method, an amorphous silicon film is deposited in a recess provided in a surface of a substrate by supplying a silicon-containing gas to the substrate. The amorphous silicon film is etched by supplying an etching gas to the substrate so as to leave the amorphous silicon film on a bottom of the recess. A silicon film is deposited on the amorphous silicon film by supplying dichlorosilane to the substrate.
Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
The vertical heat processing apparatus performs a DED process to form a logic device of a semiconductor device in a substrate that is a wafer W. That is, the film deposition process and the etching process are performed on a wafer W. The film deposition process is performed by a thermal CVD (Chemical Vapor Deposition), and the etching process is performed by a reactive gas etching in which thermal energy is supplied to the etching gas.
The logical device to be manufactured includes a logical device using, for example, a FinFET that is the next generation transistor of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in addition to the logical device manufactured by conventional art.
The vertical heat processing apparatus includes a reactor tube 11 that is an approximately cylindrical vacuum chamber and the longitudinal direction thereof is oriented to the vertical direction. The reactor tube 11 has a dual tube structure including an inner tube 12, and an outer tube 13 with a ceiling formed so as to cover the inner tube 12 and to have a constant distance from the inner tube 12. The inner tube 12 and the outer tube 13 are formed of a heat resistant material such as quartz. The reactor tube 11 forms a closed space for processing the substrate and may therefore be referred to as a processing chamber.
A manifold 14 made of stainless steel (SUS) formed into a cylindrical shape is disposed below the outer tube 13. The manifold 14 is hermetically connected to the lower end of the outer tube 13. The inner tube 12 protrudes from the inner wall of the manifold 14 and is supported by a support ring 15 integrally formed with the manifold 14.
A lid 16 is disposed below the manifold 14, and a boat elevator 10 allows the lid 16 to be moved up and down between an elevated position and a lowered position.
At the manifold 14, below the support ring 15 described above, a process gas inlet tube 21 and a purge gas inlet tube 31 are inserted, and the downstream end of each gas inlet tube 21, 31 is arranged so as to supply a gas to a wafer W within the inner tube 12. For example, the upstream side of the process gas introduction tube 21 branches to form branches 22A to 22E, and each upstream end of the branches 22A to 22E is connected to a supply source 23A of diisopropylaminosilane (DIPAS) gas, a supply source 23B of disilane (Si2H6) gas, a supply source 23C of monoaminosilane (SiH4) gas, a supply source 23D of chlorine (Cl2) gas, and a supply source 23E of dichlorosilane (SiH2Cl2, Dichlorosilane, hereinafter referred to as “DCS”). The branches 22A to 22E include gas supply mechanisms 24A to 24E, respectively. The gas supply mechanisms 24A to 24E each include valves and mass flow controllers configured to control the flow rate of the process gas supplied from the gas supply sources 23A to 23E to the process gas introduction tube 21, respectively.
DIPAS gas is a gas for forming a seed layer to form a first seed layer on a surface of a silicon oxide film formed on a surface of a wafer W, and the gas supply source 23A and the gas supply mechanism 24A constitute a DIPAS gas supply part.
Si2H6 gas is a gas for forming a second seed layer on the surface of the first seed layer, and the gas supply source 23B and the gas supply mechanism 24B constitute a Si2H6 (disilane) gas supply part.
Also, Si2H6 gas may be used as a silicon-containing gas to further deposit an amorphous silicon film on the second seed layer. Details are described below.
DIPAS gas supply part and the disilane gas supply part are gas supply parts for forming the seed layer, and thus may be referred to as a seed layer forming gas supply part.
In the present embodiment, two types of gases for forming the seed layer are described, but any one type of gas for forming the seed layer may be used. In addition, when the film is formed on the wafer W on which the seed layer is already formed, the seed layer forming gas supply part may not be disposed. In addition, gases other than DIPAS gas and Si2H6 gas may be used, even if a seed layer forming gas supply part is used. Thus, the DIPAS gas supply part, the disilane gas supply part, and the seed layer forming gas supply part may be provided as necessary.
SiH4 gas is a deposition gas for depositing a silicon (Si) film on the wafer W on which the seed layer is formed, and the gas supply source 23C and the gas supply mechanism 24C constitute a silicon-containing gas supply part. Because the silicon-containing gas is a gas used for depositing the film, the silicon-containing gas supply part may be referred to as a film deposition gas supply part.
Cl2 gas is an etching gas for etching the Si film, and the gas supply source 23D and the gas supply mechanism 24D constitute a chlorine gas supply part. Because chlorine gas is supplied as an etching gas, the chlorine gas supply part may be referred to as an etching gas supply part.
DCS gas is a silicon-containing gas for bottom-up deposition, that is, filling of a recess with a silicon film. The gas supply source 23E and the gas supply mechanism 24E constitute a DCS gas supply part. The DCS gas supply part may be referred to as a filling gas supply part, because DCS gas is a gas used for film filling deposition.
The upstream side of the purge gas introduction tube 31 is connected to a supply source 32 of nitrogen (N2) gas, which is a purge gas. A gas supply mechanism 33 is disposed in the purge gas introduction tube 31. The gas supply mechanism 33 is configured similar to the gas supply mechanisms 24A to 24E to control a flow rate of the purge gas downstream of the introduction tube 31.
In addition, an exhaust port 25 opens in a lateral surface of the support ring 15, and an exhaust gas generated in the inner tube 12 passes through a space formed between the inner tube 12 and the outer tube 13 and is exhausted to the exhaust port 25. An exhaust pipe 26 is hermetically connected to the exhaust port 25. A valve 27 and a vacuum pump 28 are disposed in this order from an upstream side of the exhaust pipe 26. By adjusting the opening of the valve 27, the pressure in the reactor tube 11 is controlled to the desired pressure.
The vertical heat processing apparatus includes a controller 30 that is constituted of a computer, and the controller 30 includes a program. In this program, a group of steps is configured so that a control signal can be output to each part of the vertical heat processing apparatus 1 to control the operation of each part so that a series of processing operations described below can be performed on a wafer W. Specifically, a control signal is output to control the elevation of the lid 16 by the boat elevator 10, the output of the heater 19 (that is, the temperature of the wafer W), the opening of the valve 27, and the flow rate of each gas into the reactor tube 11 by the gas supply mechanisms 24A to 24C, and 33. The program is stored in a storage medium such as a hard disk, a flexible disk, a compact disk, a magneto optical disk (MO), a memory card, or the like in the controller 30.
In
First, a general method for filling the recesses 42 with a silicon film by applying a DED process to the recess 42 as illustrated in
While such a filling method is the DED process, high aspect ratio recesses 42 may not have been necessarily filled with the silicon films 45 and 45a by a single DED process, and repeated DED processes have been required to fill the recesses 42. This has caused a problem of requiring a longer process period.
In contrast, a method has been proposed in which SiH4 and DCS are supplied to a substrate in parallel, and incubation time (a period from the time when supplying a silicon-containing gas to the time when actual film deposition starts) is reset by supplying an etching gas to the silicon oxide film before the incubation time ends.
By repeating the cycle consisting of
Thus, etching gas can be used to reset the incubation time to selectively grow the silicon films 45 and 45a to 45c, and to improve the filling performance in the recess 42. However, due to the repetition of the DE processes, a problem of requiring a long process period has not been solved.
Accordingly, the present disclosure proposes a method for manufacturing a semiconductor device and a substrate processing apparatus that remove the repetition of the DE process and selectively grow a silicon film from the bottom.
First, the wafer W described in
For example, SiH4 gas may be in the range of 440 degrees C. to 530 degrees C. when used as a film deposition gas.
After the wafer W is heated, the purge gas supply is stopped and DIPAS gas is supplied into the reactor tube 11. DIPAS gas is deposited on the surface of the silicon oxide film 43 of the wafer W, and a first seed layer 44 is formed so as to coat the silicon oxide film 43 (not illustrated).
Thereafter, the DIPAS gas supply is stopped; the purge gas is supplied to the reactor tube 11; DIPAS gas is purged from the reactor tube 11; and Si2H6 gas is supplied to the reactor tube 11. Si2H6 gas is deposited on the first seed layer, and a second seed layer is formed to coat the first seed layer. Thereafter, the Si2H6 gas supply is stopped and the purge gas is supplied to the reactor tube 11 to purge Si2H6 gas from the reactor tube 11.
After the seed layer forming step, the purge gas supply is stopped and SiH4 gas is supplied into the reactor tube 11. As illustrated in
In the first film deposition step, the silicon film 45 is preferably deposited so that the gap from opposing sides of the silicon film 45 is as narrow as possible as long as the opposing sides of the silicon film 45 do not contact each other. In the next etching step, in order to perform etching while leaving the silicon film 45 on the bottom of the recess 42, the etching is preferably performed so that the etching gas does not easily reach the bottom of the recess 42. Incidentally, the gap of the opposing sides of the silicon films 45 is, for example, 10 nm to 100 nm.
Here, Si2H6 gas may be used instead of SiH2 gas. In this case, the first film deposition step may be carried out consecutively from the seed layer forming step.
In the first film deposition step, an amorphous silicon film 45 is formed on the inner surface of the recess 42 and on the top surface of the wafer W.
After the SiH4 gas supply or Si2H6 gas supply is stopped, a purge gas is supplied into the reactor tube 11, and SiH4 gas or Si2H6 gas is purged from the reactor tube 11.
Cl2 gas is an etching gas for the silicon film 45, and produces active species such as Cl radicals by being heated and receiving thermal energy in the reactor tube 11. Because the active species are relatively reactive to Si, the active species react with Si outside the recess 42 and on the upper side of the recess 42, and produce SiCl4 (silicon tetrachloride) and etch the silicon film 45 until the active species reach the lower part in the recess 42 of the wafer W. Accordingly, etching is performed so that the decrease in thickness of the upper-side Si film 45 within the recess 42 is greater than the decrease in thickness of the lower-side Si film 45 within the recess 42, thereby increasing the opening width on the upper side within the recess 42. One mole of Cl2 produces two moles of Cl radicals. In other words, because relatively many active species are generated, expanding the opening width of the recess can proceed at a relatively high rate.
On this occasion, the etching gas is supplied under the supply limited mode conditions such that the silicon film 45 remains on the bottom of the recess 42. Specifically, the flow rate and/or concentration of the etching gas is controlled so that the silicon film 45 remains only on the bottom. That is, etching removes the silicon film 45 and the seed layer 44 from the upper portion of the recess 42 and the top surface of the wafer W, and exposes the silicon oxide film 43, but the etching gas is supplied so that the silicon film 45 remains on the bottom of the recess 42. Ideally, the silicon film 45 is completely removed from the upper portion of the recess 42 and the top surface of the wafer W, and the silicon film 45 remains only on the bottom of the recess 42. However, even if some silicon film 45 remains on the upper portion of the recess 42 and on the top surface of the wafer, as long as the surrounding silicon oxide film 43 is exposed, the process will not be significantly affected. However, because the silicon film may be grown therefrom, the silicon film 45 and the seed layer 44 are preferably removed as completely as possible except for those on the bottom and the lower portion of the recess 42.
Incidentally, in order to set the etching gas to the supply limited mode, for example, the temperature is set to be 250 degrees C. or more.
Thereafter, the second film deposition step is continued and the silicon film 45a fills the recess 42. The silicon film 45a is a polysilicon film. Thus, the polysilicon film 45a selectively grows in the recess 42 without generating a void.
Once all recesses 42a have been filled with a silicon film, the temperature in the reactor tube 11 is lowered. During the process, the temperature is maintained at a constant deposition temperature, but when the process is completed, the temperature in the reactor tube 11 is decreased to take out the wafer W. This causes the wafer W to cool down.
Subsequently, after the lid 16 is lowered and the wafer boat 3 is unloaded from the reactor tube 11, the wafer W is removed from the wafer boat 3 by a transport mechanism (not illustrated) and one batch of a wafer W process is completed. Because the processing temperature can be kept constant during the process, the filling process can be performed in a short time.
Thus, according to the method for manufacturing the semiconductor device according to the present embodiment, the polysilicon film can be selectively grown in the recess 42 by etching the amorphous silicon film 45 so as to leave the amorphous silicon film 45 on the bottom of the recess 42 during the etching process, and the recess 42 can be filled with a silicon film without generating a void.
As shown in
In
As shown in the left column of
As the right column indicates, the wafer W is greatly bent in the conventional DED process after annealing, but in the method for manufacturing the semiconductor device according to the present embodiment, the bending degree is not appreciably changed compared to the time of film deposition.
This is because, when heated at a high temperature, the silicon film of the conventional DED process is deposited in the amorphous state, causing the silicon film to shrink greatly due to the loss of hydrogen. In contrast, because the silicon film manufactured by the method for manufacturing the semiconductor device according to the present embodiment is a polysilicon film and the silicon film is crystallized, the state of the silicon film does not change when heated, and the wafer W is not bent.
As described above, according to the method for manufacturing the semiconductor device and the substrate processing apparatus according to the present embodiment, a high quality silicon film without causing fin bending can fill a recess without generating a void in the recess.
According to the present embodiment, the recess can be filled with a silicon film without repeating a DED process.
All examples recited herein are intended for pedagogical purposes to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority or inferiority of the disclosure. Although the embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-208800 | Dec 2020 | JP | national |
