Patent Application
20080299686
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-280785 filed on Oct. 13, 2006; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device where a plurality of semiconductor devices are formed from at least one wafer.
2. Background Art
When a plurality of semiconductor devices are formed from at least one wafer, it is important to reduce characteristics variations among these semiconductor devices. Many semiconductor devices have a structure where a plurality of semiconductor layers are formed on a semiconductor substrate. Such a structure is formed by processes including crystal growth, doping, etching, and polishing on the semiconductor substrate.
JP-A 2004-128079 (Kokai) discloses a technique for etching an active silicon layer of an SOI (silicon on insulator) wafer to a required thickness by using local dry etching.
According to an aspect of the invention, there is provided a method for manufacturing a semiconductor device, including: measuring a within-wafer distribution of a physical quantity of at least one of a plurality of semiconductor layers provided in a wafer; determining a within-wafer distribution of etching amount for the at least one of the plurality of semiconductor layers based on the measured within-wafer distribution of the physical quantity; and etching the at least one of the plurality of semiconductor layers based on the determined within-wafer distribution of the etching amount so that the etching amount is locally varied within the wafer.
According to an aspect of the invention, there is provided a method for manufacturing a semiconductor device, including: measuring a within-wafer distribution of a physical quantity; and etching the wafer so that the physical quantity get close to constant within the wafer.
An embodiment of the invention will now be described with reference to the drawings.
In this embodiment, a primary process is first performed (step S102). This illustratively includes, in the example shown in
These various processes may involve within-wafer variations.
For example, the p+-type silicon substrate 110 serving as a starting material may initially include variations in thickness and dopant concentration. In
Moreover, as shown in
More specifically, in grinding a wafer, the wafer is stuck on a tape 620 and mounted on a stage 610 serving as a reference plane. The wafer surface is successively ground by a rotated grindstone 630, and further polished. Here, for example, the thickness of the tape 620 and the gap formed between the wafer and the tape 620 may have uneven distribution. Furthermore, the amount of contact of the grindstone 630 may have uneven distribution. These factors may cause within-wafer thickness variations after grinding. Similar variations may occur also in the case of wet etching and dry etching.
In the example shown in
If a wafer having such variations in thickness or dopant concentration is directly used to form semiconductor devices, the characteristics of the semiconductor devices obtained from this wafer will not be uniform, but will be varied. As described later in detail, in manufacturing an IGBT (insulated gate bipolar transistor) or a diode, for example, the thickness and dopant concentration of the p+-type silicon substrate 110 are the factors determining the threshold and operating voltage of the device. Hence, to equalize device characteristics, the thickness and dopant concentration of the p+-type silicon substrate 110 need to be equalized within a wafer.
In this respect, in this embodiment, the wafer after the completion of the primary process is measured for the within-wafer distribution of physical quantities (step S104). The physical quantities measured here relate to the thickness, dopant concentration, and the amount of dopant, for example. However, the measurement is not limited to direct measurement of thickness and dopant concentration, but physical quantities related thereto may be measured. In the example shown in
Here, a 6-inch silicon wafer having an initial thickness of 625 micrometers was ground to a target thickness of 155 micrometers. Then the sheet resistance distribution of the wafer was measured. The horizontal axis of
As seen from
As described later in detail, sheet resistance is a physical quantity reflecting thickness and dopant concentration. The distribution of thickness and dopant concentration of the p+-type silicon substrate 110 can be known by measuring the sheet resistance distribution.
The physical quantity measured in this embodiment is not limited to sheet resistance. For example, the thickness and dopant concentration may be each measured by separate methods. Specifically, the thickness distribution may be measured by an optical method, and the dopant concentration distribution may be measured by the C-V (capacitance-voltage) method using a mercury probe. Furthermore, the physical quantity measured is not limited to its absolute value, but its relative distribution within a wafer may be measured.
Moreover, while the physical quantity of the p+-type silicon substrate 110 is measured in this example, other silicon layers may be measured, or the total thickness and electrical characteristics thereof may be measured.
After the within-wafer distribution of the physical quantity is measured in this manner, the etching amount is next calculated (step S106). More specifically, the within-wafer distribution of the measured physical quantity is used to calculate the etching amount required for substantially equalizing it to a prescribed value of the physical quantity. For example, to equalize the thickness of the p+-type silicon substrate 110, as viewed within the wafer, the etching amount is increased in a thick portion of the p+-type silicon substrate 110 and decreased in a thin portion thereof.
On the other hand, to substantially equalize the sheet concentration of carriers in the p+-type silicon substrate 110, on the basis of the distribution of thickness and dopant concentration measured in step S104, the etching amount is increased at positions with high sheet carrier concentration in the p+-type silicon substrate 110, and decreased at positions with low sheet carrier concentration. In
After calculating the within-wafer distribution of etching amount in this manner, local etching is performed (step S108). More specifically, in contrast to uniformly etching the entire surface of a wafer, the distribution of etching amount calculated in step S106 is used to locally etch individual portions of the wafer as shown in
More specifically, an etchant 200E is locally supplied through a nozzle 210, for example, to the surface of a wafer 100 to be etched. Then, as shown by arrow A, the wafer 100 and the nozzle 210 are relatively displaced. Here, at a position where the etching amount is to be increased, the etching amount can be increased by extending etching time or increasing the concentration or amount supplied of the etchant. At a position where the etching amount is to be decreased, the nozzle 210 can be rapidly passed, or supply of etchant can be stopped.
Here, the etching method may be whether wet etching or dry etching. In the case of wet etching, a chemical liquid is dropped or squirted from the nozzle 210 to the surface of the wafer 100. Here, to prevent the portion other than the position directly below the nozzle 210 from being etched, for example, as shown in
For example, in the case where the surface of a wafer 100 has irregularities as shown in
The inner diameter of the nozzle 210 for supplying an etchant can be substantially several hundred micrometers to 10 millimeters, for example. As the inner diameter of the nozzle 210 becomes smaller, a finer region can be selectively etched. On the other hand, if the nozzle 210 has a large inner diameter, the etching rate can be easily increased. Decreasing the speed or pitch of relative displacement of the wafer 100 and the nozzle 210 facilitates selectively etching a finer region.
More specifically, an X-Y movable stage 224 is provided in a vacuum chamber 220, and a wafer 100 is mounted on the stage 224. The vacuum chamber 220 is evacuated by a vacuum pump 230 and can maintain a reduced-pressure atmosphere. A nozzle 210 is placed opposite to the wafer 100. The nozzle 210 is in communication with an electric discharge tube 244 provided outside the chamber 220. The discharge tube 244 is supplied with an etching or diluting gas 250 through a gas supply controller 252. The discharge tube 244 is further supplied with a microwave M through a waveguide 242, and thereby a plasma of the gas 250 is generated.
For example, in the case where the gas 250 is a fluorine-based gas such as SF6, generation of its plasma results in generating an active species such as fluorine radicals. The active species 200E is supplied from the nozzle 210 to the surface of the wafer 100. The fluorine active species 200E supplied to the surface of the wafer 100 locally etches silicon. Hence, on the basis of the distribution of etching amount calculated in step S106, a prescribed physical quantity such as within-wafer thickness or dopant concentration can be substantially equalized by increasing the etching time in a portion of large etching amount and decreasing the etching time in a portion of small etching amount during moving the stage 224.
As described above, by local etching, the within-wafer distribution of a physical quantity can be substantially equalized to a prescribed value of the physical quantity. In the example shown in
Subsequently, a secondary process is performed (step S110). The secondary process is needed to complete semiconductor devices after local etching, and suitably includes formation of additional semiconductor layers, formation of electrodes, and formation of protective film, for example. However, the secondary process is not essential to the invention, but the semiconductor devices may be completed with local etching.
As described above, according to this embodiment, the within-wafer characteristics variations can be restrained by measuring the within-wafer distribution of a physical quantity and locally etching the wafer on the basis thereof. Consequently, the characteristics of a plurality of semiconductor devices obtained from at least one wafer can be equalized.
For example, in the case where IGBT or other semiconductor devices 50A, . . . , 50B are connected in parallel, if one of the semiconductor devices 50A, . . . , 50B has a particularly low resistance during energization (ON resistance), the current concentrates on this semiconductor device (50A), which may result in overheat, decreased lifetime, or breakdown.
In contrast, according to this embodiment, within-wafer characteristics variations are prevented, and semiconductor devices with uniform characteristics can be stably manufactured. Furthermore, when the physical quantity measured in step S104 is controlled by its absolute value, the characteristics of semiconductor devices can be equalized not only in one wafer but also among a plurality of wafers.
In the following, the embodiment of the invention is described in more detail with reference to examples.
The semiconductor device shown in
From the surface of the emitter region 7 corresponding to the first major surface of the semiconductor layer 10, a trench is formed through the emitter region 7 and the base region 6 to the n−-type base layer 5. The trench is filled in with a control electrode 19 via an insulating film 18. In the base region 6, the portion opposed to the control electrode 19 across the insulating film 18 functions as a channel formation region.
A first main electrode 1 is provided on the surface of the emitter region 7 and the base region 6 (the surface corresponding to the first major surface of the semiconductor layer 10). An interlayer insulating film 20 is interposed between the first main electrode 1 and the control electrode 19.
A second main electrode 2 is provided on the backside of the collector layer 3, which corresponds to the second major surface of the semiconductor layer 10.
In the IGBT described above, upon application of a desired control voltage (gate voltage) to the control electrode 19, an n-channel is formed in the channel formation region opposed to the control electrode 19 across the insulating film 18, and the path between the first main electrode 1 and the second main electrode 2 (emitter-collector path) is turned into the ON state. In an IGBT, electrons and holes are injected from the emitter and the collector, respectively, and carriers are accumulated in the n−-type base layer 5, thereby causing conductivity modulation. Hence the ON resistance can be made lower than in the vertical MOSFET (metal-oxide-semiconductor field effect transistor).
First, as the primary process, the process shown in
Subsequently, as shown in
Next, as shown in
The calculation of etching amount (step S106 shown in
The following relation holds between the thickness t of the p+-type silicon layer 3 and the sheet resistance ρs:
σ=1/ρ=1/(ρs×t)=q×μp×p (1)
σ: conductivity
ρ: resistivity
q: elementary charge
μp: hole mobility
p: dopant concentration in the p+-type silicon layer 3
The following relation can be derived from formula (1);
ρs=1/(q×μp×p×t)
That is, if the mobility μp is constant, the sheet resistance ρs is inversely proportional to the sheet dopant concentration p×t. Hence, if local etching is performed so as to equalize the sheet resistance of the p+-type silicon layer 3, the sheet dopant concentration p×t can be also equalized.
For example, for a target value Qo (cm−2) of sheet dopant concentration p×t in the p+-type silicon layer 3 after local etching, the target value of sheet resistance, ρso, can be expressed as:
ρso=1/(q×μp×Qo) (2)
On the other hand, from formula (1), the thickness t can be expressed as:
t=1/(q×μp×p×ps)
A correction coefficient A is introduced for taking into consideration the measurement error of sheet resistance ρs. Then the etching amount Δt for the p+-type silicon layer 3 can be expressed as:
Δt=(1/Aρs−1/ρso)/(q×μp×p×ρs) (3)
If the target value Qo (cm−2) of sheet dopant concentration p×t in the p+-type silicon layer 3 is determined, the etching amount for the p+-type silicon layer 3 can be calculated from the sheet resistance ρs on the basis of formulas (2) and (3). Here, the correction coefficient A can be suitably determined by characterizing the IGBT through preliminary experiments.
As described above, in this example, the p+-type silicon layer 3 is locally etched (
As shown in
For example, if the total thickness of the wafer is measured and the measurement value is used to control the thickness of the p+-type silicon layer 3, the control is inaccurate in that it is also affected by variations in thickness of the n+-type buffer layer 4 and the n−-type base layer 5. In contrast, according to this example, by measuring the sheet resistance of the p+-type silicon layer 3 using the four-probe method or the like instead of simply measuring the thickness, its sheet dopant concentration p×t can be reliably and easily measured.
In this example, an n−-type base layer 5 is used as a substrate. More specifically, as shown in
Hence, next, as shown in
After the thickness distribution of the silicon layer is thus measured, as shown in
Subsequently, as shown in
Then, as shown in
As described above, in this example, variations in thickness of the n−-type base layer 5 can be eliminated so that it attains the target value throughout the wafer. Consequently, IGBTs with uniform characteristics can be stably manufactured.
In this example, an n+-type buffer layer 4 is used as a substrate. More specifically, as shown in
Hence, next, as shown in
After the sheet resistance distribution of the n+-type buffer layer 4 is thus measured, as shown in
Subsequently, as shown in
Then, as shown in
As described above, in this example, variations in sheet resistance of the n+-type buffer layer 4 can be eliminated so that it attains the target value throughout the wafer. Consequently, IGBTs with uniform characteristics can be stably manufactured.
The semiconductor device of this example is a MOSFET (metal-oxide-semiconductor field effect transistor) of the trench gate type. This MOSFET has a structure similar to that of the IGBT described above with reference to
In this example, an n+-type buffer layer 4 is used as a substrate. More specifically, as shown in
After the thickness distribution of the n−-type base layer 5 is thus measured, as shown in
Subsequently, as shown in
Then, the structure from the p+-type base region 6 to the first main electrode 1 is formed on the n−-type base layer 5, and a second main electrode 2 is formed on the backside of the n+-type buffer layer 4. Thus a MOSFET shown in
As described above, in this example, variations in thickness of the n−-type base layer 5 can be eliminated so that it is substantially equalized to a target value throughout the wafer. Consequently, MOSFETs with uniform characteristics can be stably manufactured.
The embodiment of the invention has been described with reference to examples. However, the invention is not limited to these examples.
The semiconductor device of this example is an IGBT of the planar gate structure. This IGBT includes an n+-type buffer layer 4 and an n−-type base layer 5 sequentially on a p+-type silicon layer (collector layer) 3. In this structure, a p+-type base region 6 is selectively provided in the surface portion of the n−-type base layer 5, and an n+-type emitter region 7 is selectively provided in the surface of the base region 6.
A control electrode 9 is provided via an insulating film 8 on the surface extending from a portion of the emitter region 7 through the base region 6 to the n−-type base layer 5 (the surface corresponding to the first major surface of the semiconductor layer 10). The surface portion of the base region 6 opposed to the control electrode 9 across the insulating film 8 functions as a channel formation region.
The control electrode 9 is covered with an interlayer insulating film 11, and a first main electrode 1 is provided in contact with the emitter region 7 so as to cover the interlayer insulating film 11.
A second main electrode 2 is provided on the backside of the collector layer 3, which corresponds to the second major surface of the semiconductor layer 10.
Also to such an IGBT of the planar gate structure, a manufacturing method similar to that described above with reference to the first to third example, for instance, can be applied, and similar advantageous effects can be achieved.
Furthermore, in each of the above examples, the invention is also applicable to structures with semiconductors having reversed conductivity types, and various other IGBTs, MOSFETs, and diodes, achieving similar advantageous effects.
Besides silicon, various semiconductor materials such as GaAs, SiC, GaN, Ge, and SiGe can be used.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-280785 | Oct 2006 | JP | national |
